src/mesa/drivers/dri/radeon/radeon_state_init.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v 1.3 2003/02/22 06:21:11 dawes Exp $ */
   2 /*
   3  * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
   4  *
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * on the rights to use, copy, modify, merge, publish, distribute, sub
  11  * license, and/or sell copies of the Software, and to permit persons to whom
  12  * the Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  24  * OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Gareth Hughes <gareth@valinux.com>
  28  *    Keith Whitwell <keith@tungstengraphics.com>
  29  */
  30
  31 #include "glheader.h"
  32 #include "imports.h"
  33 #include "api_arrayelt.h"
  34
  35 #include "swrast/swrast.h"
  36 #include "array_cache/acache.h"
  37 #include "tnl/tnl.h"
  38 #include "tnl/t_pipeline.h"
  39 #include "swrast_setup/swrast_setup.h"
  40
  41 #include "radeon_context.h"
  42 #include "radeon_ioctl.h"
  43 #include "radeon_state.h"
  44 #include "radeon_tcl.h"
  45 #include "radeon_tex.h"
  46 #include "radeon_swtcl.h"
  47 #include "radeon_vtxfmt.h"
  48
  49 #include "xmlpool.h"
  50
  51 /* =============================================================
  52  * State initialization
  53  */
  54
  55 void radeonPrintDirty( radeonContextPtr rmesa, const char *msg )
  56 {
  57    struct radeon_state_atom *l;
  58
  59    fprintf(stderr, msg);
  60    fprintf(stderr, ": ");
  61
  62    foreach(l, &rmesa->hw.atomlist) {
  63       if (l->dirty || rmesa->hw.all_dirty)
  64          fprintf(stderr, "%s, ", l->name);
  65    }
  66
  67    fprintf(stderr, "\n");
  68 }
  69
  70 static int cmdpkt( int id )
  71 {
  72    drm_radeon_cmd_header_t h;
  73    h.i = 0;
  74    h.packet.cmd_type = RADEON_CMD_PACKET;
  75    h.packet.packet_id = id;
  76    return h.i;
  77 }
  78
  79 static int cmdvec( int offset, int stride, int count )
  80 {
  81    drm_radeon_cmd_header_t h;
  82    h.i = 0;
  83    h.vectors.cmd_type = RADEON_CMD_VECTORS;
  84    h.vectors.offset = offset;
  85    h.vectors.stride = stride;
  86    h.vectors.count = count;
  87    return h.i;
  88 }
  89
  90 static int cmdscl( int offset, int stride, int count )
  91 {
  92    drm_radeon_cmd_header_t h;
  93    h.i = 0;
  94    h.scalars.cmd_type = RADEON_CMD_SCALARS;
  95    h.scalars.offset = offset;
  96    h.scalars.stride = stride;
  97    h.scalars.count = count;
  98    return h.i;
  99 }
 100
 101 #define CHECK( NM, FLAG )                       \
 102 static GLboolean check_##NM( GLcontext *ctx )   \
 103 {                                               \
 104    return FLAG;                                 \
 105 }
 106
 107 #define TCL_CHECK( NM, FLAG )                           \
 108 static GLboolean check_##NM( GLcontext *ctx )           \
 109 {                                                       \
 110    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);        \
 111    return !rmesa->TclFallback && (FLAG);                \
 112 }
 113
 114
 115 CHECK( always, GL_TRUE )
 116 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
 117 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
 118 CHECK( fog, ctx->Fog.Enabled )
 119 TCL_CHECK( tcl, GL_TRUE )
 120 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
 121 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
 122 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
 123 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
 124 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
 125 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
 126 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
 127 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
 128 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
 129 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
 130 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
 131 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
 132 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
 133 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
 134 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
 135 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
 136 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
 137 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
 138 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
 139
 140 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
 141 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
 142
 143
 144
 145 /* Initialize the context's hardware state.
 146  */
 147 void radeonInitState( radeonContextPtr rmesa )
 148 {
 149    GLcontext *ctx = rmesa->glCtx;
 150    GLuint color_fmt, depth_fmt, i;
 151
 152    switch ( rmesa->radeonScreen->cpp ) {
 153    case 2:
 154       color_fmt = RADEON_COLOR_FORMAT_RGB565;
 155       break;
 156    case 4:
 157       color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 158       break;
 159    default:
 160       fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
 161       exit( -1 );
 162    }
 163
 164    rmesa->state.color.clear = 0x00000000;
 165
 166    switch ( ctx->Visual.depthBits ) {
 167    case 16:
 168       rmesa->state.depth.clear = 0x0000ffff;
 169       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffff;
 170       depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 171       rmesa->state.stencil.clear = 0x00000000;
 172       break;
 173    case 24:
 174       rmesa->state.depth.clear = 0x00ffffff;
 175       rmesa->state.depth.scale = 1.0 / (GLfloat)0xffffff;
 176       depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 177       rmesa->state.stencil.clear = 0xffff0000;
 178       break;
 179    default:
 180       fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
 181                ctx->Visual.depthBits );
 182       exit( -1 );
 183    }
 184
 185    /* Only have hw stencil when depth buffer is 24 bits deep */
 186    rmesa->state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
 187                                      ctx->Visual.depthBits == 24 );
 188
 189    rmesa->Fallback = 0;
 190
 191    if ( ctx->Visual.doubleBufferMode && rmesa->sarea->pfCurrentPage == 0 ) {
 192       rmesa->state.color.drawOffset = rmesa->radeonScreen->backOffset;
 193       rmesa->state.color.drawPitch  = rmesa->radeonScreen->backPitch;
 194    } else {
 195       rmesa->state.color.drawOffset = rmesa->radeonScreen->frontOffset;
 196       rmesa->state.color.drawPitch  = rmesa->radeonScreen->frontPitch;
 197    }
 198    rmesa->state.pixel.readOffset = rmesa->state.color.drawOffset;
 199    rmesa->state.pixel.readPitch  = rmesa->state.color.drawPitch;
 200
 201    rmesa->hw.max_state_size = 0;
 202
 203 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG )                          \
 204    do {                                                         \
 205       rmesa->hw.ATOM.cmd_size = SZ;                             \
 206       rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int));     \
 207       rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
 208       rmesa->hw.ATOM.name = NM;                                 \
 209       rmesa->hw.ATOM.is_tcl = FLAG;                                     \
 210       rmesa->hw.ATOM.check = check_##CHK;                               \
 211       rmesa->hw.ATOM.dirty = GL_TRUE;                           \
 212       rmesa->hw.max_state_size += SZ * sizeof(int);             \
 213    } while (0)
 214
 215
 216    /* Allocate state buffers:
 217     */
 218    ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
 219    ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
 220    ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
 221    ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
 222    ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
 223    ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
 224    ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
 225    ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
 226    ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
 227    ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
 228    ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
 229    ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
 230    ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
 231    ALLOC_STATE( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0 );
 232    ALLOC_STATE( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0 );
 233    ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
 234    ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
 235    ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
 236    ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
 237    ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
 238    ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
 239    ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
 240    ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
 241    ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
 242    ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
 243    ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
 244    ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
 245    ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
 246    ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
 247    ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
 248    ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
 249    ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
 250    ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
 251    ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
 252    ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 );
 253    ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 );
 254
 255    radeonSetUpAtomList( rmesa );
 256
 257    /* Fill in the packet headers:
 258     */
 259    rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(RADEON_EMIT_PP_MISC);
 260    rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(RADEON_EMIT_PP_CNTL);
 261    rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH);
 262    rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN);
 263    rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH);
 264    rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK);
 265    rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE);
 266    rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(RADEON_EMIT_SE_CNTL);
 267    rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS);
 268    rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(RADEON_EMIT_RE_MISC);
 269    rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0);
 270    rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0);
 271    rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1);
 272    rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1);
 273    rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR);
 274    rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
 275    rmesa->hw.mtl.cmd[MTL_CMD_0] =
 276       cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
 277    rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0);
 278    rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1);
 279    rmesa->hw.grd.cmd[GRD_CMD_0] =
 280       cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
 281    rmesa->hw.fog.cmd[FOG_CMD_0] =
 282       cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
 283    rmesa->hw.glt.cmd[GLT_CMD_0] =
 284       cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
 285    rmesa->hw.eye.cmd[EYE_CMD_0] =
 286       cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
 287
 288    for (i = 0 ; i < 5; i++) {
 289       rmesa->hw.mat[i].cmd[MAT_CMD_0] =
 290          cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
 291    }
 292
 293    for (i = 0 ; i < 8; i++) {
 294       rmesa->hw.lit[i].cmd[LIT_CMD_0] =
 295          cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
 296       rmesa->hw.lit[i].cmd[LIT_CMD_1] =
 297          cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
 298    }
 299
 300    for (i = 0 ; i < 6; i++) {
 301       rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
 302          cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
 303    }
 304
 305    rmesa->last_ReallyEnabled = -1;
 306
 307    /* Initial Harware state:
 308     */
 309    rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
 310                                      RADEON_CHROMA_FUNC_FAIL |
 311                                      RADEON_CHROMA_KEY_NEAREST |
 312                                      RADEON_SHADOW_FUNC_EQUAL |
 313                                      RADEON_SHADOW_PASS_1 |
 314                                      RADEON_RIGHT_HAND_CUBE_OGL);
 315
 316    rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
 317                                           RADEON_FOG_USE_DEPTH);
 318
 319    rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
 320
 321    rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
 322                                             RADEON_SRC_BLEND_GL_ONE |
 323                                             RADEON_DST_BLEND_GL_ZERO );
 324
 325    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
 326       rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation;
 327
 328    rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
 329       ((rmesa->radeonScreen->depthPitch &
 330         RADEON_DEPTHPITCH_MASK) |
 331        RADEON_DEPTH_ENDIAN_NO_SWAP);
 332
 333    if (rmesa->using_hyperz)
 334        rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
 335
 336    rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
 337                                                RADEON_Z_TEST_LESS |
 338                                                RADEON_STENCIL_TEST_ALWAYS |
 339                                                RADEON_STENCIL_FAIL_KEEP |
 340                                                RADEON_STENCIL_ZPASS_KEEP |
 341                                                RADEON_STENCIL_ZFAIL_KEEP |
 342                                                RADEON_Z_WRITE_ENABLE);
 343
 344    if (rmesa->using_hyperz) {
 345        rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
 346                                                    RADEON_Z_DECOMPRESSION_ENABLE;
 347       if (rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL) {
 348          /* works for q3, but slight rendering errors with glxgears ? */
 349 /*       rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
 350          /* need this otherwise get lots of lockups with q3 ??? */
 351          rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
 352       }
 353    }
 354
 355    rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
 356                                      RADEON_ANTI_ALIAS_NONE);
 357
 358    rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
 359                                        color_fmt |
 360                                        RADEON_ZBLOCK16);
 361
 362    switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) {
 363    case DRI_CONF_DITHER_XERRORDIFFRESET:
 364       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
 365       break;
 366    case DRI_CONF_DITHER_ORDERED:
 367       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
 368       break;
 369    }
 370    if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) ==
 371         DRI_CONF_ROUND_ROUND )
 372       rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE;
 373    else
 374       rmesa->state.color.roundEnable = 0;
 375    if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) ==
 376         DRI_CONF_COLOR_REDUCTION_DITHER )
 377       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
 378    else
 379       rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable;
 380
 381    rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset +
 382                                                rmesa->radeonScreen->fbLocation)
 383                                               & RADEON_COLOROFFSET_MASK);
 384
 385    rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch &
 386                                               RADEON_COLORPITCH_MASK) |
 387                                              RADEON_COLOR_ENDIAN_NO_SWAP);
 388    /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
 389    if (rmesa->sarea->tiling_enabled) {
 390       rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
 391    }
 392
 393    rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
 394                                      RADEON_BFACE_SOLID |
 395                                      RADEON_FFACE_SOLID |
 396 /*                           RADEON_BADVTX_CULL_DISABLE | */
 397                                      RADEON_FLAT_SHADE_VTX_LAST |
 398                                      RADEON_DIFFUSE_SHADE_GOURAUD |
 399                                      RADEON_ALPHA_SHADE_GOURAUD |
 400                                      RADEON_SPECULAR_SHADE_GOURAUD |
 401                                      RADEON_FOG_SHADE_GOURAUD |
 402                                      RADEON_VPORT_XY_XFORM_ENABLE |
 403                                      RADEON_VPORT_Z_XFORM_ENABLE |
 404                                      RADEON_VTX_PIX_CENTER_OGL |
 405                                      RADEON_ROUND_MODE_TRUNC |
 406                                      RADEON_ROUND_PREC_8TH_PIX);
 407
 408    rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
 409 #ifdef MESA_BIG_ENDIAN
 410                                             RADEON_VC_32BIT_SWAP;
 411 #else
 412                                             RADEON_VC_NO_SWAP;
 413 #endif
 414
 415    if (!(rmesa->radeonScreen->chipset & RADEON_CHIPSET_TCL)) {
 416      rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
 417    }
 418
 419    rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
 420       RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
 421       RADEON_TEX1_W_ROUTING_USE_Q1);
 422
 423
 424    rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
 425
 426    rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
 427       ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
 428        (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
 429
 430    rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
 431
 432    rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
 433       ((0x00 << RADEON_STENCIL_REF_SHIFT) |
 434        (0xff << RADEON_STENCIL_MASK_SHIFT) |
 435        (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
 436
 437    rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
 438    rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
 439
 440    rmesa->hw.msc.cmd[MSC_RE_MISC] =
 441       ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
 442        (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
 443        RADEON_STIPPLE_BIG_BIT_ORDER);
 444
 445    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE]  = 0x00000000;
 446    rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
 447    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE]  = 0x00000000;
 448    rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
 449    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE]  = 0x00000000;
 450    rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
 451
 452    for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
 453       rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
 454       rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
 455           (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
 456            RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
 457            (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
 458            (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
 459            (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
 460
 461       /* Initialize the texture offset to the start of the card texture heap */
 462       rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
 463           rmesa->radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
 464
 465       rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
 466       rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
 467           (RADEON_COLOR_ARG_A_ZERO |
 468            RADEON_COLOR_ARG_B_ZERO |
 469            RADEON_COLOR_ARG_C_CURRENT_COLOR |
 470            RADEON_BLEND_CTL_ADD |
 471            RADEON_SCALE_1X |
 472            RADEON_CLAMP_TX);
 473       rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
 474           (RADEON_ALPHA_ARG_A_ZERO |
 475            RADEON_ALPHA_ARG_B_ZERO |
 476            RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
 477            RADEON_BLEND_CTL_ADD |
 478            RADEON_SCALE_1X |
 479            RADEON_CLAMP_TX);
 480       rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
 481    }
 482
 483    /* Can only add ST1 at the time of doing some multitex but can keep
 484     * it after that.  Errors if DIFFUSE is missing.
 485     */
 486    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
 487       (RADEON_TCL_VTX_Z0 |
 488        RADEON_TCL_VTX_W0 |
 489        RADEON_TCL_VTX_PK_DIFFUSE
 490          );     /* need to keep this uptodate */
 491
 492    rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
 493       ( RADEON_TCL_COMPUTE_XYZW         |
 494         (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
 495         (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
 496         (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
 497
 498
 499    /* XXX */
 500    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
 501       ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
 502        (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
 503
 504    rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
 505       ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
 506        (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
 507        (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT));
 508
 509    rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
 510       (RADEON_UCP_IN_CLIP_SPACE |
 511        RADEON_CULL_FRONT_IS_CCW);
 512
 513    rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
 514
 515    rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
 516       (RADEON_SPECULAR_LIGHTS |
 517        RADEON_DIFFUSE_SPECULAR_COMBINE |
 518        RADEON_LOCAL_LIGHT_VEC_GL |
 519        (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
 520        (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
 521        (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
 522        (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
 523
 524    for (i = 0 ; i < 8; i++) {
 525       struct gl_light *l = &ctx->Light.Light[i];
 526       GLenum p = GL_LIGHT0 + i;
 527       *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
 528
 529       ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
 530       ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
 531       ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
 532       ctx->Driver.Lightfv( ctx, p, GL_POSITION, 0 );
 533       ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, 0 );
 534       ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
 535       ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
 536       ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
 537                            &l->ConstantAttenuation );
 538       ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
 539                            &l->LinearAttenuation );
 540       ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
 541                      &l->QuadraticAttenuation );
 542       *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
 543    }
 544
 545    ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
 546                              ctx->Light.Model.Ambient );
 547
 548    TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
 549
 550    for (i = 0 ; i < 6; i++) {
 551       ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
 552    }
 553
 554    ctx->Driver.Fogfv( ctx, GL_FOG_MODE, 0 );
 555    ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
 556    ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
 557    ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
 558    ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
 559    ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, 0 );
 560
 561    rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
 562    rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
 563    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
 564    rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
 565
 566    rmesa->hw.eye.cmd[EYE_X] = 0;
 567    rmesa->hw.eye.cmd[EYE_Y] = 0;
 568    rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
 569    rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
 570
 571    rmesa->hw.all_dirty = GL_TRUE;
 572 }