2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
34 #include "swrast/swrast.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
40 #include "radeon_context.h"
41 #include "radeon_cs.h"
42 #include "radeon_mipmap_tree.h"
43 #include "radeon_ioctl.h"
44 #include "radeon_state.h"
45 #include "radeon_tcl.h"
46 #include "radeon_tex.h"
47 #include "radeon_swtcl.h"
49 #include "../r200/r200_reg.h"
53 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
54 * 1.3 cmdbuffers allow all previous state to be updated as well as
55 * the tcl scalar and vector areas.
61 } packet
[RADEON_MAX_STATE_PACKETS
] = {
62 {RADEON_PP_MISC
, 7, "RADEON_PP_MISC"},
63 {RADEON_PP_CNTL
, 3, "RADEON_PP_CNTL"},
64 {RADEON_RB3D_COLORPITCH
, 1, "RADEON_RB3D_COLORPITCH"},
65 {RADEON_RE_LINE_PATTERN
, 2, "RADEON_RE_LINE_PATTERN"},
66 {RADEON_SE_LINE_WIDTH
, 1, "RADEON_SE_LINE_WIDTH"},
67 {RADEON_PP_LUM_MATRIX
, 1, "RADEON_PP_LUM_MATRIX"},
68 {RADEON_PP_ROT_MATRIX_0
, 2, "RADEON_PP_ROT_MATRIX_0"},
69 {RADEON_RB3D_STENCILREFMASK
, 3, "RADEON_RB3D_STENCILREFMASK"},
70 {RADEON_SE_VPORT_XSCALE
, 6, "RADEON_SE_VPORT_XSCALE"},
71 {RADEON_SE_CNTL
, 2, "RADEON_SE_CNTL"},
72 {RADEON_SE_CNTL_STATUS
, 1, "RADEON_SE_CNTL_STATUS"},
73 {RADEON_RE_MISC
, 1, "RADEON_RE_MISC"},
74 {RADEON_PP_TXFILTER_0
, 6, "RADEON_PP_TXFILTER_0"},
75 {RADEON_PP_BORDER_COLOR_0
, 1, "RADEON_PP_BORDER_COLOR_0"},
76 {RADEON_PP_TXFILTER_1
, 6, "RADEON_PP_TXFILTER_1"},
77 {RADEON_PP_BORDER_COLOR_1
, 1, "RADEON_PP_BORDER_COLOR_1"},
78 {RADEON_PP_TXFILTER_2
, 6, "RADEON_PP_TXFILTER_2"},
79 {RADEON_PP_BORDER_COLOR_2
, 1, "RADEON_PP_BORDER_COLOR_2"},
80 {RADEON_SE_ZBIAS_FACTOR
, 2, "RADEON_SE_ZBIAS_FACTOR"},
81 {RADEON_SE_TCL_OUTPUT_VTX_FMT
, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
82 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
, 17,
83 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
84 {R200_PP_TXCBLEND_0
, 4, "R200_PP_TXCBLEND_0"},
85 {R200_PP_TXCBLEND_1
, 4, "R200_PP_TXCBLEND_1"},
86 {R200_PP_TXCBLEND_2
, 4, "R200_PP_TXCBLEND_2"},
87 {R200_PP_TXCBLEND_3
, 4, "R200_PP_TXCBLEND_3"},
88 {R200_PP_TXCBLEND_4
, 4, "R200_PP_TXCBLEND_4"},
89 {R200_PP_TXCBLEND_5
, 4, "R200_PP_TXCBLEND_5"},
90 {R200_PP_TXCBLEND_6
, 4, "R200_PP_TXCBLEND_6"},
91 {R200_PP_TXCBLEND_7
, 4, "R200_PP_TXCBLEND_7"},
92 {R200_SE_TCL_LIGHT_MODEL_CTL_0
, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
93 {R200_PP_TFACTOR_0
, 6, "R200_PP_TFACTOR_0"},
94 {R200_SE_VTX_FMT_0
, 4, "R200_SE_VTX_FMT_0"},
95 {R200_SE_VAP_CNTL
, 1, "R200_SE_VAP_CNTL"},
96 {R200_SE_TCL_MATRIX_SEL_0
, 5, "R200_SE_TCL_MATRIX_SEL_0"},
97 {R200_SE_TCL_TEX_PROC_CTL_2
, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
98 {R200_SE_TCL_UCP_VERT_BLEND_CTL
, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
99 {R200_PP_TXFILTER_0
, 6, "R200_PP_TXFILTER_0"},
100 {R200_PP_TXFILTER_1
, 6, "R200_PP_TXFILTER_1"},
101 {R200_PP_TXFILTER_2
, 6, "R200_PP_TXFILTER_2"},
102 {R200_PP_TXFILTER_3
, 6, "R200_PP_TXFILTER_3"},
103 {R200_PP_TXFILTER_4
, 6, "R200_PP_TXFILTER_4"},
104 {R200_PP_TXFILTER_5
, 6, "R200_PP_TXFILTER_5"},
105 {R200_PP_TXOFFSET_0
, 1, "R200_PP_TXOFFSET_0"},
106 {R200_PP_TXOFFSET_1
, 1, "R200_PP_TXOFFSET_1"},
107 {R200_PP_TXOFFSET_2
, 1, "R200_PP_TXOFFSET_2"},
108 {R200_PP_TXOFFSET_3
, 1, "R200_PP_TXOFFSET_3"},
109 {R200_PP_TXOFFSET_4
, 1, "R200_PP_TXOFFSET_4"},
110 {R200_PP_TXOFFSET_5
, 1, "R200_PP_TXOFFSET_5"},
111 {R200_SE_VTE_CNTL
, 1, "R200_SE_VTE_CNTL"},
112 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, 1,
113 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
114 {R200_PP_TAM_DEBUG3
, 1, "R200_PP_TAM_DEBUG3"},
115 {R200_PP_CNTL_X
, 1, "R200_PP_CNTL_X"},
116 {R200_RB3D_DEPTHXY_OFFSET
, 1, "R200_RB3D_DEPTHXY_OFFSET"},
117 {R200_RE_AUX_SCISSOR_CNTL
, 1, "R200_RE_AUX_SCISSOR_CNTL"},
118 {R200_RE_SCISSOR_TL_0
, 2, "R200_RE_SCISSOR_TL_0"},
119 {R200_RE_SCISSOR_TL_1
, 2, "R200_RE_SCISSOR_TL_1"},
120 {R200_RE_SCISSOR_TL_2
, 2, "R200_RE_SCISSOR_TL_2"},
121 {R200_SE_VAP_CNTL_STATUS
, 1, "R200_SE_VAP_CNTL_STATUS"},
122 {R200_SE_VTX_STATE_CNTL
, 1, "R200_SE_VTX_STATE_CNTL"},
123 {R200_RE_POINTSIZE
, 1, "R200_RE_POINTSIZE"},
124 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, 4,
125 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
126 {R200_PP_CUBIC_FACES_0
, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
127 {R200_PP_CUBIC_OFFSET_F1_0
, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
128 {R200_PP_CUBIC_FACES_1
, 1, "R200_PP_CUBIC_FACES_1"},
129 {R200_PP_CUBIC_OFFSET_F1_1
, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
130 {R200_PP_CUBIC_FACES_2
, 1, "R200_PP_CUBIC_FACES_2"},
131 {R200_PP_CUBIC_OFFSET_F1_2
, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
132 {R200_PP_CUBIC_FACES_3
, 1, "R200_PP_CUBIC_FACES_3"},
133 {R200_PP_CUBIC_OFFSET_F1_3
, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
134 {R200_PP_CUBIC_FACES_4
, 1, "R200_PP_CUBIC_FACES_4"},
135 {R200_PP_CUBIC_OFFSET_F1_4
, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
136 {R200_PP_CUBIC_FACES_5
, 1, "R200_PP_CUBIC_FACES_5"},
137 {R200_PP_CUBIC_OFFSET_F1_5
, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
138 {RADEON_PP_TEX_SIZE_0
, 2, "RADEON_PP_TEX_SIZE_0"},
139 {RADEON_PP_TEX_SIZE_1
, 2, "RADEON_PP_TEX_SIZE_1"},
140 {RADEON_PP_TEX_SIZE_2
, 2, "RADEON_PP_TEX_SIZE_2"},
141 {R200_RB3D_BLENDCOLOR
, 3, "R200_RB3D_BLENDCOLOR"},
142 {R200_SE_TCL_POINT_SPRITE_CNTL
, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
143 {RADEON_PP_CUBIC_FACES_0
, 1, "RADEON_PP_CUBIC_FACES_0"},
144 {RADEON_PP_CUBIC_OFFSET_T0_0
, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
145 {RADEON_PP_CUBIC_FACES_1
, 1, "RADEON_PP_CUBIC_FACES_1"},
146 {RADEON_PP_CUBIC_OFFSET_T1_0
, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
147 {RADEON_PP_CUBIC_FACES_2
, 1, "RADEON_PP_CUBIC_FACES_2"},
148 {RADEON_PP_CUBIC_OFFSET_T2_0
, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
149 {R200_PP_TRI_PERF
, 2, "R200_PP_TRI_PERF"},
150 {R200_PP_TXCBLEND_8
, 32, "R200_PP_AFS_0"}, /* 85 */
151 {R200_PP_TXCBLEND_0
, 32, "R200_PP_AFS_1"},
152 {R200_PP_TFACTOR_0
, 8, "R200_ATF_TFACTOR"},
153 {R200_PP_TXFILTER_0
, 8, "R200_PP_TXCTLALL_0"},
154 {R200_PP_TXFILTER_1
, 8, "R200_PP_TXCTLALL_1"},
155 {R200_PP_TXFILTER_2
, 8, "R200_PP_TXCTLALL_2"},
156 {R200_PP_TXFILTER_3
, 8, "R200_PP_TXCTLALL_3"},
157 {R200_PP_TXFILTER_4
, 8, "R200_PP_TXCTLALL_4"},
158 {R200_PP_TXFILTER_5
, 8, "R200_PP_TXCTLALL_5"},
159 {R200_VAP_PVS_CNTL_1
, 2, "R200_VAP_PVS_CNTL"},
162 /* =============================================================
163 * State initialization
166 void radeonPrintDirty( r100ContextPtr rmesa
, const char *msg
)
168 struct radeon_state_atom
*l
;
170 fprintf(stderr
, msg
);
171 fprintf(stderr
, ": ");
173 foreach(l
, &rmesa
->radeon
.hw
.atomlist
) {
174 if (l
->dirty
|| rmesa
->radeon
.hw
.all_dirty
)
175 fprintf(stderr
, "%s, ", l
->name
);
178 fprintf(stderr
, "\n");
181 static int cmdpkt( r100ContextPtr rmesa
, int id
)
183 drm_radeon_cmd_header_t h
;
185 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
186 return CP_PACKET0(packet
[id
].start
, packet
[id
].len
- 1);
189 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
190 h
.packet
.packet_id
= id
;
195 static int cmdvec( int offset
, int stride
, int count
)
197 drm_radeon_cmd_header_t h
;
199 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
200 h
.vectors
.offset
= offset
;
201 h
.vectors
.stride
= stride
;
202 h
.vectors
.count
= count
;
206 static int cmdscl( int offset
, int stride
, int count
)
208 drm_radeon_cmd_header_t h
;
210 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
211 h
.scalars
.offset
= offset
;
212 h
.scalars
.stride
= stride
;
213 h
.scalars
.count
= count
;
217 #define CHECK( NM, FLAG ) \
218 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
220 return FLAG ? atom->cmd_size : 0; \
223 #define TCL_CHECK( NM, FLAG ) \
224 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
226 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
227 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
231 CHECK( always
, GL_TRUE
)
232 CHECK( never
, GL_FALSE
)
233 CHECK( tex0
, ctx
->Texture
.Unit
[0]._ReallyEnabled
)
234 CHECK( tex1
, ctx
->Texture
.Unit
[1]._ReallyEnabled
)
235 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
236 CHECK( tex2
, ctx
->Texture
._EnabledUnits
)
237 CHECK( cube0
, (ctx
->Texture
.Unit
[0]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
238 CHECK( cube1
, (ctx
->Texture
.Unit
[1]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
239 CHECK( cube2
, (ctx
->Texture
.Unit
[2]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
240 CHECK( fog
, ctx
->Fog
.Enabled
)
241 TCL_CHECK( tcl
, GL_TRUE
)
242 TCL_CHECK( tcl_tex0
, ctx
->Texture
.Unit
[0]._ReallyEnabled
)
243 TCL_CHECK( tcl_tex1
, ctx
->Texture
.Unit
[1]._ReallyEnabled
)
244 TCL_CHECK( tcl_tex2
, ctx
->Texture
.Unit
[2]._ReallyEnabled
)
245 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
246 TCL_CHECK( tcl_eyespace_or_lighting
, ctx
->_NeedEyeCoords
|| ctx
->Light
.Enabled
)
247 TCL_CHECK( tcl_lit0
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[0].Enabled
)
248 TCL_CHECK( tcl_lit1
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[1].Enabled
)
249 TCL_CHECK( tcl_lit2
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[2].Enabled
)
250 TCL_CHECK( tcl_lit3
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[3].Enabled
)
251 TCL_CHECK( tcl_lit4
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[4].Enabled
)
252 TCL_CHECK( tcl_lit5
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[5].Enabled
)
253 TCL_CHECK( tcl_lit6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[6].Enabled
)
254 TCL_CHECK( tcl_lit7
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[7].Enabled
)
255 TCL_CHECK( tcl_ucp0
, (ctx
->Transform
.ClipPlanesEnabled
& 0x1) )
256 TCL_CHECK( tcl_ucp1
, (ctx
->Transform
.ClipPlanesEnabled
& 0x2) )
257 TCL_CHECK( tcl_ucp2
, (ctx
->Transform
.ClipPlanesEnabled
& 0x4) )
258 TCL_CHECK( tcl_ucp3
, (ctx
->Transform
.ClipPlanesEnabled
& 0x8) )
259 TCL_CHECK( tcl_ucp4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x10) )
260 TCL_CHECK( tcl_ucp5
, (ctx
->Transform
.ClipPlanesEnabled
& 0x20) )
261 TCL_CHECK( tcl_eyespace_or_fog
, ctx
->_NeedEyeCoords
|| ctx
->Fog
.Enabled
)
263 CHECK( txr0
, (ctx
->Texture
.Unit
[0]._ReallyEnabled
& TEXTURE_RECT_BIT
))
264 CHECK( txr1
, (ctx
->Texture
.Unit
[1]._ReallyEnabled
& TEXTURE_RECT_BIT
))
265 CHECK( txr2
, (ctx
->Texture
.Unit
[2]._ReallyEnabled
& TEXTURE_RECT_BIT
))
267 #define OUT_VEC(hdr, data) do { \
268 drm_radeon_cmd_header_t h; \
270 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
272 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
273 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
274 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
275 OUT_BATCH_TABLE((data), h.vectors.count); \
278 #define OUT_SCL(hdr, data) do { \
279 drm_radeon_cmd_header_t h; \
281 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
282 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
283 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
284 OUT_BATCH_TABLE((data), h.scalars.count); \
287 static void scl_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
289 r100ContextPtr r100
= R100_CONTEXT(ctx
);
290 BATCH_LOCALS(&r100
->radeon
);
291 uint32_t dwords
= atom
->cmd_size
;
293 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
294 OUT_SCL(atom
->cmd
[0], atom
->cmd
+1);
299 static void vec_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
301 r100ContextPtr r100
= R100_CONTEXT(ctx
);
302 BATCH_LOCALS(&r100
->radeon
);
303 uint32_t dwords
= atom
->cmd_size
;
305 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
306 OUT_VEC(atom
->cmd
[0], atom
->cmd
+1);
310 static void ctx_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
312 r100ContextPtr r100
= R100_CONTEXT(ctx
);
313 BATCH_LOCALS(&r100
->radeon
);
314 struct radeon_renderbuffer
*rrb
;
317 uint32_t dwords
= atom
->cmd_size
;
318 GLframebuffer
*fb
= r100
->radeon
.dri
.drawable
->driverPrivate
;
320 /* output the first 7 bytes of context */
321 BEGIN_BATCH_NO_AUTOSTATE(dwords
+ 4);
322 OUT_BATCH_TABLE(atom
->cmd
, 5);
324 rrb
= r100
->radeon
.state
.depth
.rrb
;
329 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
330 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
334 OUT_BATCH(atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
]);
335 OUT_BATCH(atom
->cmd
[CTX_CMD_1
]);
336 OUT_BATCH(atom
->cmd
[CTX_PP_CNTL
]);
337 OUT_BATCH(atom
->cmd
[CTX_RB3D_CNTL
]);
339 rrb
= r100
->radeon
.state
.color
.rrb
;
340 if (r100
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
341 rrb
= (struct radeon_renderbuffer
*)fb
->Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
;
343 if (!rrb
|| !rrb
->bo
) {
344 OUT_BATCH(atom
->cmd
[CTX_RB3D_COLOROFFSET
]);
346 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
349 OUT_BATCH(atom
->cmd
[CTX_CMD_2
]);
351 if (!rrb
|| !rrb
->bo
) {
352 OUT_BATCH(atom
->cmd
[CTX_RB3D_COLORPITCH
]);
354 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
359 if (r100
->radeon
.sarea
->tiling_enabled
)
360 cbpitch
|= R200_COLOR_TILE_ENABLE
;
366 static void ctx_emit_cs(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
368 r100ContextPtr r100
= R100_CONTEXT(ctx
);
369 BATCH_LOCALS(&r100
->radeon
);
370 struct radeon_renderbuffer
*rrb
, *drb
;
371 uint32_t cbpitch
= 0;
372 uint32_t zbpitch
= 0;
373 uint32_t dwords
= atom
->cmd_size
;
374 GLframebuffer
*fb
= r100
->radeon
.dri
.drawable
->driverPrivate
;
376 rrb
= r100
->radeon
.state
.color
.rrb
;
377 if (r100
->radeon
.radeonScreen
->driScreen
->dri2
.enabled
) {
378 rrb
= (struct radeon_renderbuffer
*)fb
->Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
;
381 assert(rrb
->bo
!= NULL
);
382 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
383 if (r100
->radeon
.sarea
->tiling_enabled
)
384 cbpitch
|= R200_COLOR_TILE_ENABLE
;
387 drb
= r100
->radeon
.state
.depth
.rrb
;
389 zbpitch
= (drb
->pitch
/ drb
->cpp
);
391 /* output the first 7 bytes of context */
392 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
394 /* In the CS case we need to split this up */
395 OUT_BATCH(CP_PACKET0(packet
[0].start
, 3));
396 OUT_BATCH_TABLE((atom
->cmd
+ 1), 4);
399 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET
, 0));
400 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
402 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH
, 0));
406 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL
, 0));
407 OUT_BATCH(atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
]);
408 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL
, 1));
409 OUT_BATCH(atom
->cmd
[CTX_PP_CNTL
]);
410 OUT_BATCH(atom
->cmd
[CTX_RB3D_CNTL
]);
414 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET
, 0));
415 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
423 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH
, 0));
427 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
428 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
434 static void tex_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
436 r100ContextPtr r100
= R100_CONTEXT(ctx
);
437 BATCH_LOCALS(&r100
->radeon
);
438 uint32_t dwords
= atom
->cmd_size
;
440 radeonTexObj
*t
= r100
->state
.texture
.unit
[i
].texobj
;
442 if (t
&& t
->mt
&& !t
->image_override
)
444 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
445 OUT_BATCH_TABLE(atom
->cmd
, 3);
446 if (t
&& t
->mt
&& !t
->image_override
) {
447 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, 0,
448 RADEON_GEM_DOMAIN_VRAM
, 0, 0);
450 /* workaround for old CS mechanism */
451 OUT_BATCH(r100
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
]);
452 // OUT_BATCH(r100->radeon.radeonScreen);
455 OUT_BATCH_TABLE((atom
->cmd
+4), 5);
459 /* Initialize the context's hardware state.
461 void radeonInitState( r100ContextPtr rmesa
)
463 GLcontext
*ctx
= rmesa
->radeon
.glCtx
;
464 GLuint color_fmt
, depth_fmt
, i
;
465 GLint drawPitch
, drawOffset
;
467 switch ( rmesa
->radeon
.radeonScreen
->cpp
) {
469 color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
472 color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
475 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
479 rmesa
->radeon
.state
.color
.clear
= 0x00000000;
481 switch ( ctx
->Visual
.depthBits
) {
483 rmesa
->radeon
.state
.depth
.clear
= 0x0000ffff;
484 rmesa
->radeon
.state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
485 depth_fmt
= RADEON_DEPTH_FORMAT_16BIT_INT_Z
;
486 rmesa
->radeon
.state
.stencil
.clear
= 0x00000000;
489 rmesa
->radeon
.state
.depth
.clear
= 0x00ffffff;
490 rmesa
->radeon
.state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
491 depth_fmt
= RADEON_DEPTH_FORMAT_24BIT_INT_Z
;
492 rmesa
->radeon
.state
.stencil
.clear
= 0xffff0000;
495 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
496 ctx
->Visual
.depthBits
);
500 /* Only have hw stencil when depth buffer is 24 bits deep */
501 rmesa
->radeon
.state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
502 ctx
->Visual
.depthBits
== 24 );
504 rmesa
->radeon
.Fallback
= 0;
506 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->radeon
.sarea
->pfCurrentPage
== 0 ) {
507 drawOffset
= rmesa
->radeon
.radeonScreen
->backOffset
;
508 drawPitch
= rmesa
->radeon
.radeonScreen
->backPitch
;
510 drawOffset
= rmesa
->radeon
.radeonScreen
->frontOffset
;
511 drawPitch
= rmesa
->radeon
.radeonScreen
->frontPitch
;
514 rmesa
->radeon
.hw
.max_state_size
= 0;
516 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
518 rmesa->hw.ATOM.cmd_size = SZ; \
519 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
520 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
521 rmesa->hw.ATOM.name = NM; \
522 rmesa->hw.ATOM.is_tcl = FLAG; \
523 rmesa->hw.ATOM.check = check_##CHK; \
524 rmesa->hw.ATOM.dirty = GL_TRUE; \
525 rmesa->hw.ATOM.idx = IDX; \
526 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
529 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
530 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
532 /* Allocate state buffers:
534 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE
, "CTX/context", 0 );
535 if (rmesa
->radeon
.radeonScreen
->kernel_mm
)
536 rmesa
->hw
.ctx
.emit
= ctx_emit_cs
;
538 rmesa
->hw
.ctx
.emit
= ctx_emit
;
539 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
540 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
541 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
542 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
543 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
544 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
545 ALLOC_STATE( tcl
, always
, TCL_STATE_SIZE
, "TCL/tcl", 1 );
546 ALLOC_STATE( mtl
, tcl_lighting
, MTL_STATE_SIZE
, "MTL/material", 1 );
547 ALLOC_STATE( grd
, always
, GRD_STATE_SIZE
, "GRD/guard-band", 1 );
548 ALLOC_STATE( fog
, fog
, FOG_STATE_SIZE
, "FOG/fog", 1 );
549 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 1 );
550 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 1 );
551 ALLOC_STATE_IDX( tex
[0], tex0
, TEX_STATE_SIZE
, "TEX/tex-0", 0, 0);
552 ALLOC_STATE_IDX( tex
[1], tex1
, TEX_STATE_SIZE
, "TEX/tex-1", 0, 1);
553 ALLOC_STATE_IDX( tex
[2], tex2
, TEX_STATE_SIZE
, "TEX/tex-2", 0, 2 );
555 for (i
= 0; i
< 3; i
++)
556 rmesa
->hw
.tex
[i
].emit
= tex_emit
;
557 if (rmesa
->radeon
.radeonScreen
->drmSupportsCubeMapsR100
)
559 ALLOC_STATE_IDX( cube
[0], cube0
, CUBE_STATE_SIZE
, "CUBE/cube-0", 0, 0 );
560 ALLOC_STATE_IDX( cube
[1], cube1
, CUBE_STATE_SIZE
, "CUBE/cube-1", 0, 1 );
561 ALLOC_STATE_IDX( cube
[2], cube2
, CUBE_STATE_SIZE
, "CUBE/cube-2", 0, 2 );
565 ALLOC_STATE_IDX( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/cube-0", 0, 0 );
566 ALLOC_STATE_IDX( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/cube-1", 0, 1 );
567 ALLOC_STATE_IDX( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/cube-2", 0, 2 );
569 ALLOC_STATE( mat
[0], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 1 );
570 ALLOC_STATE( mat
[1], tcl_eyespace_or_fog
, MAT_STATE_SIZE
, "MAT/modelview", 1 );
571 ALLOC_STATE( mat
[2], tcl_eyespace_or_lighting
, MAT_STATE_SIZE
, "MAT/it-modelview", 1 );
572 ALLOC_STATE( mat
[3], tcl_tex0
, MAT_STATE_SIZE
, "MAT/texmat0", 1 );
573 ALLOC_STATE( mat
[4], tcl_tex1
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
574 ALLOC_STATE( mat
[5], tcl_tex2
, MAT_STATE_SIZE
, "MAT/texmat2", 1 );
575 ALLOC_STATE( ucp
[0], tcl_ucp0
, UCP_STATE_SIZE
, "UCP/userclip-0", 1 );
576 ALLOC_STATE( ucp
[1], tcl_ucp1
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
577 ALLOC_STATE( ucp
[2], tcl_ucp2
, UCP_STATE_SIZE
, "UCP/userclip-2", 1 );
578 ALLOC_STATE( ucp
[3], tcl_ucp3
, UCP_STATE_SIZE
, "UCP/userclip-3", 1 );
579 ALLOC_STATE( ucp
[4], tcl_ucp4
, UCP_STATE_SIZE
, "UCP/userclip-4", 1 );
580 ALLOC_STATE( ucp
[5], tcl_ucp5
, UCP_STATE_SIZE
, "UCP/userclip-5", 1 );
581 ALLOC_STATE( lit
[0], tcl_lit0
, LIT_STATE_SIZE
, "LIT/light-0", 1 );
582 ALLOC_STATE( lit
[1], tcl_lit1
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
583 ALLOC_STATE( lit
[2], tcl_lit2
, LIT_STATE_SIZE
, "LIT/light-2", 1 );
584 ALLOC_STATE( lit
[3], tcl_lit3
, LIT_STATE_SIZE
, "LIT/light-3", 1 );
585 ALLOC_STATE( lit
[4], tcl_lit4
, LIT_STATE_SIZE
, "LIT/light-4", 1 );
586 ALLOC_STATE( lit
[5], tcl_lit5
, LIT_STATE_SIZE
, "LIT/light-5", 1 );
587 ALLOC_STATE( lit
[6], tcl_lit6
, LIT_STATE_SIZE
, "LIT/light-6", 1 );
588 ALLOC_STATE( lit
[7], tcl_lit7
, LIT_STATE_SIZE
, "LIT/light-7", 1 );
589 ALLOC_STATE_IDX( txr
[0], txr0
, TXR_STATE_SIZE
, "TXR/txr-0", 0, 0 );
590 ALLOC_STATE_IDX( txr
[1], txr1
, TXR_STATE_SIZE
, "TXR/txr-1", 0, 1 );
591 ALLOC_STATE_IDX( txr
[2], txr2
, TXR_STATE_SIZE
, "TXR/txr-2", 0, 2 );
593 radeonSetUpAtomList( rmesa
);
595 /* Fill in the packet headers:
597 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_MISC
);
598 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CNTL
);
599 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(rmesa
, RADEON_EMIT_RB3D_COLORPITCH
);
600 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_RE_LINE_PATTERN
);
601 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_SE_LINE_WIDTH
);
602 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_RB3D_STENCILREFMASK
);
603 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_VPORT_XSCALE
);
604 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_CNTL
);
605 rmesa
->hw
.set
.cmd
[SET_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_SE_CNTL_STATUS
);
606 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_RE_MISC
);
607 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TXFILTER_0
);
608 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_BORDER_COLOR_0
);
609 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TXFILTER_1
);
610 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_BORDER_COLOR_1
);
611 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TXFILTER_2
);
612 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_BORDER_COLOR_2
);
613 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_FACES_0
);
614 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_OFFSETS_T0
);
615 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_FACES_1
);
616 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_OFFSETS_T1
);
617 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_FACES_2
);
618 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_OFFSETS_T2
);
619 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_ZBIAS_FACTOR
);
620 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT
);
621 rmesa
->hw
.mtl
.cmd
[MTL_CMD_0
] =
622 cmdpkt(rmesa
, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED
);
623 rmesa
->hw
.txr
[0].cmd
[TXR_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TEX_SIZE_0
);
624 rmesa
->hw
.txr
[1].cmd
[TXR_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TEX_SIZE_1
);
625 rmesa
->hw
.txr
[2].cmd
[TXR_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TEX_SIZE_2
);
626 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
627 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
628 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
629 cmdvec( RADEON_VS_FOG_PARAM_ADDR
, 1, 4 );
630 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
631 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
632 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
633 cmdvec( RADEON_VS_EYE_VECTOR_ADDR
, 1, 4 );
635 for (i
= 0 ; i
< 6; i
++) {
636 rmesa
->hw
.mat
[i
].cmd
[MAT_CMD_0
] =
637 cmdvec( RADEON_VS_MATRIX_0_ADDR
+ i
*4, 1, 16);
640 for (i
= 0 ; i
< 8; i
++) {
641 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
642 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
643 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
644 cmdscl( RADEON_SS_LIGHT_DCD_ADDR
+ i
, 8, 6 );
647 for (i
= 0 ; i
< 6; i
++) {
648 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
649 cmdvec( RADEON_VS_UCP_ADDR
+ i
, 1, 4 );
652 rmesa
->last_ReallyEnabled
= -1;
654 /* Initial Harware state:
656 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (RADEON_ALPHA_TEST_PASS
|
657 RADEON_CHROMA_FUNC_FAIL
|
658 RADEON_CHROMA_KEY_NEAREST
|
659 RADEON_SHADOW_FUNC_EQUAL
|
660 RADEON_SHADOW_PASS_1
/*|
661 RADEON_RIGHT_HAND_CUBE_OGL */);
663 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (RADEON_FOG_VERTEX
|
664 /* this bit unused for vertex fog */
665 RADEON_FOG_USE_DEPTH
);
667 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
669 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (RADEON_COMB_FCN_ADD_CLAMP
|
670 RADEON_SRC_BLEND_GL_ONE
|
671 RADEON_DST_BLEND_GL_ZERO
);
673 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
674 rmesa
->radeon
.radeonScreen
->depthOffset
+ rmesa
->radeon
.radeonScreen
->fbLocation
;
676 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
677 ((rmesa
->radeon
.radeonScreen
->depthPitch
&
678 RADEON_DEPTHPITCH_MASK
) |
679 RADEON_DEPTH_ENDIAN_NO_SWAP
);
681 if (rmesa
->using_hyperz
)
682 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] |= RADEON_DEPTH_HYPERZ
;
684 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
686 RADEON_STENCIL_TEST_ALWAYS
|
687 RADEON_STENCIL_FAIL_KEEP
|
688 RADEON_STENCIL_ZPASS_KEEP
|
689 RADEON_STENCIL_ZFAIL_KEEP
|
690 RADEON_Z_WRITE_ENABLE
);
692 if (rmesa
->using_hyperz
) {
693 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_COMPRESSION_ENABLE
|
694 RADEON_Z_DECOMPRESSION_ENABLE
;
695 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
696 /* works for q3, but slight rendering errors with glxgears ? */
697 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
698 /* need this otherwise get lots of lockups with q3 ??? */
699 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_FORCE_Z_DIRTY
;
703 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (RADEON_SCISSOR_ENABLE
|
704 RADEON_ANTI_ALIAS_NONE
);
706 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = (RADEON_PLANE_MASK_ENABLE
|
710 switch ( driQueryOptioni( &rmesa
->radeon
.optionCache
, "dither_mode" ) ) {
711 case DRI_CONF_DITHER_XERRORDIFFRESET
:
712 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_INIT
;
714 case DRI_CONF_DITHER_ORDERED
:
715 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_SCALE_DITHER_ENABLE
;
718 if ( driQueryOptioni( &rmesa
->radeon
.optionCache
, "round_mode" ) ==
719 DRI_CONF_ROUND_ROUND
)
720 rmesa
->radeon
.state
.color
.roundEnable
= RADEON_ROUND_ENABLE
;
722 rmesa
->radeon
.state
.color
.roundEnable
= 0;
723 if ( driQueryOptioni (&rmesa
->radeon
.optionCache
, "color_reduction" ) ==
724 DRI_CONF_COLOR_REDUCTION_DITHER
)
725 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
;
727 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->radeon
.state
.color
.roundEnable
;
729 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((drawOffset
+
730 rmesa
->radeon
.radeonScreen
->fbLocation
)
731 & RADEON_COLOROFFSET_MASK
);
733 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((drawPitch
&
734 RADEON_COLORPITCH_MASK
) |
735 RADEON_COLOR_ENDIAN_NO_SWAP
);
738 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
739 if (rmesa
->radeon
.sarea
->tiling_enabled
) {
740 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= RADEON_COLOR_TILE_ENABLE
;
743 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (RADEON_FFACE_CULL_CCW
|
746 /* RADEON_BADVTX_CULL_DISABLE | */
747 RADEON_FLAT_SHADE_VTX_LAST
|
748 RADEON_DIFFUSE_SHADE_GOURAUD
|
749 RADEON_ALPHA_SHADE_GOURAUD
|
750 RADEON_SPECULAR_SHADE_GOURAUD
|
751 RADEON_FOG_SHADE_GOURAUD
|
752 RADEON_VPORT_XY_XFORM_ENABLE
|
753 RADEON_VPORT_Z_XFORM_ENABLE
|
754 RADEON_VTX_PIX_CENTER_OGL
|
755 RADEON_ROUND_MODE_TRUNC
|
756 RADEON_ROUND_PREC_8TH_PIX
);
758 rmesa
->hw
.set
.cmd
[SET_SE_CNTL_STATUS
] =
759 #ifdef MESA_BIG_ENDIAN
760 RADEON_VC_32BIT_SWAP
;
765 if (!(rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
766 rmesa
->hw
.set
.cmd
[SET_SE_CNTL_STATUS
] |= RADEON_TCL_BYPASS
;
769 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = (
770 RADEON_VTX_W0_IS_NOT_1_OVER_W0
|
771 RADEON_TEX1_W_ROUTING_USE_Q1
);
774 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
776 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
777 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT
) |
778 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT
));
780 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
782 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
783 ((0x00 << RADEON_STENCIL_REF_SHIFT
) |
784 (0xff << RADEON_STENCIL_MASK_SHIFT
) |
785 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT
));
787 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = RADEON_ROP_COPY
;
788 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
790 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
791 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT
) |
792 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT
) |
793 RADEON_STIPPLE_BIG_BIT_ORDER
);
795 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
796 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
797 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
798 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
799 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
800 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
802 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
803 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = RADEON_BORDER_MODE_OGL
;
804 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
805 (RADEON_TXFORMAT_ENDIAN_NO_SWAP
|
806 RADEON_TXFORMAT_PERSPECTIVE_ENABLE
|
807 (i
<< 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
808 (2 << RADEON_TXFORMAT_WIDTH_SHIFT
) |
809 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT
));
811 /* Initialize the texture offset to the start of the card texture heap */
812 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
813 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
815 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
816 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXCBLEND
] =
817 (RADEON_COLOR_ARG_A_ZERO
|
818 RADEON_COLOR_ARG_B_ZERO
|
819 RADEON_COLOR_ARG_C_CURRENT_COLOR
|
820 RADEON_BLEND_CTL_ADD
|
823 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXABLEND
] =
824 (RADEON_ALPHA_ARG_A_ZERO
|
825 RADEON_ALPHA_ARG_B_ZERO
|
826 RADEON_ALPHA_ARG_C_CURRENT_ALPHA
|
827 RADEON_BLEND_CTL_ADD
|
830 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TFACTOR
] = 0;
832 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
833 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_0
] =
834 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
835 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_1
] =
836 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
837 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_2
] =
838 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
839 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_3
] =
840 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
841 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_4
] =
842 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
845 /* Can only add ST1 at the time of doing some multitex but can keep
846 * it after that. Errors if DIFFUSE is missing.
848 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] =
851 RADEON_TCL_VTX_PK_DIFFUSE
852 ); /* need to keep this uptodate */
854 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] =
855 ( RADEON_TCL_COMPUTE_XYZW
|
856 (RADEON_TCL_TEX_INPUT_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
) |
857 (RADEON_TCL_TEX_INPUT_TEX_1
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
) |
858 (RADEON_TCL_TEX_INPUT_TEX_2
<< RADEON_TCL_TEX_2_OUTPUT_SHIFT
));
862 rmesa
->hw
.tcl
.cmd
[TCL_MATRIX_SELECT_0
] =
863 ((MODEL
<< RADEON_MODELVIEW_0_SHIFT
) |
864 (MODEL_IT
<< RADEON_IT_MODELVIEW_0_SHIFT
));
866 rmesa
->hw
.tcl
.cmd
[TCL_MATRIX_SELECT_1
] =
867 ((MODEL_PROJ
<< RADEON_MODELPROJECT_0_SHIFT
) |
868 (TEXMAT_0
<< RADEON_TEXMAT_0_SHIFT
) |
869 (TEXMAT_1
<< RADEON_TEXMAT_1_SHIFT
) |
870 (TEXMAT_2
<< RADEON_TEXMAT_2_SHIFT
));
872 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
873 (RADEON_UCP_IN_CLIP_SPACE
|
874 RADEON_CULL_FRONT_IS_CCW
);
876 rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] = 0;
878 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] =
879 (RADEON_SPECULAR_LIGHTS
|
880 RADEON_DIFFUSE_SPECULAR_COMBINE
|
881 RADEON_LOCAL_LIGHT_VEC_GL
|
882 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_EMISSIVE_SOURCE_SHIFT
) |
883 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_AMBIENT_SOURCE_SHIFT
) |
884 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_DIFFUSE_SOURCE_SHIFT
) |
885 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_SPECULAR_SOURCE_SHIFT
));
887 for (i
= 0 ; i
< 8; i
++) {
888 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
889 GLenum p
= GL_LIGHT0
+ i
;
890 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
892 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
893 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
894 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
895 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, NULL
);
896 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, NULL
);
897 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
898 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
899 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
900 &l
->ConstantAttenuation
);
901 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
902 &l
->LinearAttenuation
);
903 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
904 &l
->QuadraticAttenuation
);
905 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
908 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
909 ctx
->Light
.Model
.Ambient
);
911 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
913 for (i
= 0 ; i
< 6; i
++) {
914 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
917 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, NULL
);
918 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
919 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
920 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
921 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
922 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, NULL
);
924 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
925 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
926 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
927 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
929 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
930 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
931 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
932 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
934 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
936 rcommonInitCmdBuf(&rmesa
->radeon
);