2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
34 #include "swrast/swrast.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
40 #include "radeon_context.h"
41 #include "radeon_mipmap_tree.h"
42 #include "radeon_ioctl.h"
43 #include "radeon_state.h"
44 #include "radeon_tcl.h"
45 #include "radeon_tex.h"
46 #include "radeon_swtcl.h"
47 #include "radeon_queryobj.h"
49 #include "../r200/r200_reg.h"
53 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
54 * 1.3 cmdbuffers allow all previous state to be updated as well as
55 * the tcl scalar and vector areas.
61 } packet
[RADEON_MAX_STATE_PACKETS
] = {
62 {RADEON_PP_MISC
, 7, "RADEON_PP_MISC"},
63 {RADEON_PP_CNTL
, 3, "RADEON_PP_CNTL"},
64 {RADEON_RB3D_COLORPITCH
, 1, "RADEON_RB3D_COLORPITCH"},
65 {RADEON_RE_LINE_PATTERN
, 2, "RADEON_RE_LINE_PATTERN"},
66 {RADEON_SE_LINE_WIDTH
, 1, "RADEON_SE_LINE_WIDTH"},
67 {RADEON_PP_LUM_MATRIX
, 1, "RADEON_PP_LUM_MATRIX"},
68 {RADEON_PP_ROT_MATRIX_0
, 2, "RADEON_PP_ROT_MATRIX_0"},
69 {RADEON_RB3D_STENCILREFMASK
, 3, "RADEON_RB3D_STENCILREFMASK"},
70 {RADEON_SE_VPORT_XSCALE
, 6, "RADEON_SE_VPORT_XSCALE"},
71 {RADEON_SE_CNTL
, 2, "RADEON_SE_CNTL"},
72 {RADEON_SE_CNTL_STATUS
, 1, "RADEON_SE_CNTL_STATUS"},
73 {RADEON_RE_MISC
, 1, "RADEON_RE_MISC"},
74 {RADEON_PP_TXFILTER_0
, 6, "RADEON_PP_TXFILTER_0"},
75 {RADEON_PP_BORDER_COLOR_0
, 1, "RADEON_PP_BORDER_COLOR_0"},
76 {RADEON_PP_TXFILTER_1
, 6, "RADEON_PP_TXFILTER_1"},
77 {RADEON_PP_BORDER_COLOR_1
, 1, "RADEON_PP_BORDER_COLOR_1"},
78 {RADEON_PP_TXFILTER_2
, 6, "RADEON_PP_TXFILTER_2"},
79 {RADEON_PP_BORDER_COLOR_2
, 1, "RADEON_PP_BORDER_COLOR_2"},
80 {RADEON_SE_ZBIAS_FACTOR
, 2, "RADEON_SE_ZBIAS_FACTOR"},
81 {RADEON_SE_TCL_OUTPUT_VTX_FMT
, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
82 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED
, 17,
83 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
84 {R200_PP_TXCBLEND_0
, 4, "R200_PP_TXCBLEND_0"},
85 {R200_PP_TXCBLEND_1
, 4, "R200_PP_TXCBLEND_1"},
86 {R200_PP_TXCBLEND_2
, 4, "R200_PP_TXCBLEND_2"},
87 {R200_PP_TXCBLEND_3
, 4, "R200_PP_TXCBLEND_3"},
88 {R200_PP_TXCBLEND_4
, 4, "R200_PP_TXCBLEND_4"},
89 {R200_PP_TXCBLEND_5
, 4, "R200_PP_TXCBLEND_5"},
90 {R200_PP_TXCBLEND_6
, 4, "R200_PP_TXCBLEND_6"},
91 {R200_PP_TXCBLEND_7
, 4, "R200_PP_TXCBLEND_7"},
92 {R200_SE_TCL_LIGHT_MODEL_CTL_0
, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
93 {R200_PP_TFACTOR_0
, 6, "R200_PP_TFACTOR_0"},
94 {R200_SE_VTX_FMT_0
, 4, "R200_SE_VTX_FMT_0"},
95 {R200_SE_VAP_CNTL
, 1, "R200_SE_VAP_CNTL"},
96 {R200_SE_TCL_MATRIX_SEL_0
, 5, "R200_SE_TCL_MATRIX_SEL_0"},
97 {R200_SE_TCL_TEX_PROC_CTL_2
, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
98 {R200_SE_TCL_UCP_VERT_BLEND_CTL
, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
99 {R200_PP_TXFILTER_0
, 6, "R200_PP_TXFILTER_0"},
100 {R200_PP_TXFILTER_1
, 6, "R200_PP_TXFILTER_1"},
101 {R200_PP_TXFILTER_2
, 6, "R200_PP_TXFILTER_2"},
102 {R200_PP_TXFILTER_3
, 6, "R200_PP_TXFILTER_3"},
103 {R200_PP_TXFILTER_4
, 6, "R200_PP_TXFILTER_4"},
104 {R200_PP_TXFILTER_5
, 6, "R200_PP_TXFILTER_5"},
105 {R200_PP_TXOFFSET_0
, 1, "R200_PP_TXOFFSET_0"},
106 {R200_PP_TXOFFSET_1
, 1, "R200_PP_TXOFFSET_1"},
107 {R200_PP_TXOFFSET_2
, 1, "R200_PP_TXOFFSET_2"},
108 {R200_PP_TXOFFSET_3
, 1, "R200_PP_TXOFFSET_3"},
109 {R200_PP_TXOFFSET_4
, 1, "R200_PP_TXOFFSET_4"},
110 {R200_PP_TXOFFSET_5
, 1, "R200_PP_TXOFFSET_5"},
111 {R200_SE_VTE_CNTL
, 1, "R200_SE_VTE_CNTL"},
112 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL
, 1,
113 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
114 {R200_PP_TAM_DEBUG3
, 1, "R200_PP_TAM_DEBUG3"},
115 {R200_PP_CNTL_X
, 1, "R200_PP_CNTL_X"},
116 {R200_RB3D_DEPTHXY_OFFSET
, 1, "R200_RB3D_DEPTHXY_OFFSET"},
117 {R200_RE_AUX_SCISSOR_CNTL
, 1, "R200_RE_AUX_SCISSOR_CNTL"},
118 {R200_RE_SCISSOR_TL_0
, 2, "R200_RE_SCISSOR_TL_0"},
119 {R200_RE_SCISSOR_TL_1
, 2, "R200_RE_SCISSOR_TL_1"},
120 {R200_RE_SCISSOR_TL_2
, 2, "R200_RE_SCISSOR_TL_2"},
121 {R200_SE_VAP_CNTL_STATUS
, 1, "R200_SE_VAP_CNTL_STATUS"},
122 {R200_SE_VTX_STATE_CNTL
, 1, "R200_SE_VTX_STATE_CNTL"},
123 {R200_RE_POINTSIZE
, 1, "R200_RE_POINTSIZE"},
124 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0
, 4,
125 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
126 {R200_PP_CUBIC_FACES_0
, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
127 {R200_PP_CUBIC_OFFSET_F1_0
, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
128 {R200_PP_CUBIC_FACES_1
, 1, "R200_PP_CUBIC_FACES_1"},
129 {R200_PP_CUBIC_OFFSET_F1_1
, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
130 {R200_PP_CUBIC_FACES_2
, 1, "R200_PP_CUBIC_FACES_2"},
131 {R200_PP_CUBIC_OFFSET_F1_2
, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
132 {R200_PP_CUBIC_FACES_3
, 1, "R200_PP_CUBIC_FACES_3"},
133 {R200_PP_CUBIC_OFFSET_F1_3
, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
134 {R200_PP_CUBIC_FACES_4
, 1, "R200_PP_CUBIC_FACES_4"},
135 {R200_PP_CUBIC_OFFSET_F1_4
, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
136 {R200_PP_CUBIC_FACES_5
, 1, "R200_PP_CUBIC_FACES_5"},
137 {R200_PP_CUBIC_OFFSET_F1_5
, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
138 {RADEON_PP_TEX_SIZE_0
, 2, "RADEON_PP_TEX_SIZE_0"},
139 {RADEON_PP_TEX_SIZE_1
, 2, "RADEON_PP_TEX_SIZE_1"},
140 {RADEON_PP_TEX_SIZE_2
, 2, "RADEON_PP_TEX_SIZE_2"},
141 {R200_RB3D_BLENDCOLOR
, 3, "R200_RB3D_BLENDCOLOR"},
142 {R200_SE_TCL_POINT_SPRITE_CNTL
, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
143 {RADEON_PP_CUBIC_FACES_0
, 1, "RADEON_PP_CUBIC_FACES_0"},
144 {RADEON_PP_CUBIC_OFFSET_T0_0
, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
145 {RADEON_PP_CUBIC_FACES_1
, 1, "RADEON_PP_CUBIC_FACES_1"},
146 {RADEON_PP_CUBIC_OFFSET_T1_0
, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
147 {RADEON_PP_CUBIC_FACES_2
, 1, "RADEON_PP_CUBIC_FACES_2"},
148 {RADEON_PP_CUBIC_OFFSET_T2_0
, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
149 {R200_PP_TRI_PERF
, 2, "R200_PP_TRI_PERF"},
150 {R200_PP_TXCBLEND_8
, 32, "R200_PP_AFS_0"}, /* 85 */
151 {R200_PP_TXCBLEND_0
, 32, "R200_PP_AFS_1"},
152 {R200_PP_TFACTOR_0
, 8, "R200_ATF_TFACTOR"},
153 {R200_PP_TXFILTER_0
, 8, "R200_PP_TXCTLALL_0"},
154 {R200_PP_TXFILTER_1
, 8, "R200_PP_TXCTLALL_1"},
155 {R200_PP_TXFILTER_2
, 8, "R200_PP_TXCTLALL_2"},
156 {R200_PP_TXFILTER_3
, 8, "R200_PP_TXCTLALL_3"},
157 {R200_PP_TXFILTER_4
, 8, "R200_PP_TXCTLALL_4"},
158 {R200_PP_TXFILTER_5
, 8, "R200_PP_TXCTLALL_5"},
159 {R200_VAP_PVS_CNTL_1
, 2, "R200_VAP_PVS_CNTL"},
162 /* =============================================================
163 * State initialization
165 static int cmdpkt( r100ContextPtr rmesa
, int id
)
167 drm_radeon_cmd_header_t h
;
169 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
170 return CP_PACKET0(packet
[id
].start
, packet
[id
].len
- 1);
173 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
174 h
.packet
.packet_id
= id
;
179 static int cmdvec( int offset
, int stride
, int count
)
181 drm_radeon_cmd_header_t h
;
183 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
184 h
.vectors
.offset
= offset
;
185 h
.vectors
.stride
= stride
;
186 h
.vectors
.count
= count
;
190 static int cmdscl( int offset
, int stride
, int count
)
192 drm_radeon_cmd_header_t h
;
194 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
195 h
.scalars
.offset
= offset
;
196 h
.scalars
.stride
= stride
;
197 h
.scalars
.count
= count
;
201 #define CHECK( NM, FLAG, ADD ) \
202 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
204 return FLAG ? atom->cmd_size + (ADD) : 0; \
207 #define TCL_CHECK( NM, FLAG, ADD ) \
208 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
210 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
211 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
215 CHECK( always
, GL_TRUE
, 0 )
216 CHECK( always_add2
, GL_TRUE
, 2 )
217 CHECK( always_add4
, GL_TRUE
, 4 )
218 CHECK( never
, GL_FALSE
, 0 )
219 CHECK( tex0_mm
, ctx
->Texture
.Unit
[0]._ReallyEnabled
, 3 )
220 CHECK( tex1_mm
, ctx
->Texture
.Unit
[1]._ReallyEnabled
, 3 )
221 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
222 CHECK( tex2_mm
, ctx
->Texture
._EnabledUnits
, 3 )
223 CHECK( tex0
, ctx
->Texture
.Unit
[0]._ReallyEnabled
, 2 )
224 CHECK( tex1
, ctx
->Texture
.Unit
[1]._ReallyEnabled
, 2 )
225 CHECK( tex2
, ctx
->Texture
._EnabledUnits
, 2 )
226 CHECK( cube0
, (ctx
->Texture
.Unit
[0]._ReallyEnabled
& TEXTURE_CUBE_BIT
), 3 + 3*5 - CUBE_STATE_SIZE
)
227 CHECK( cube1
, (ctx
->Texture
.Unit
[1]._ReallyEnabled
& TEXTURE_CUBE_BIT
), 3 + 3*5 - CUBE_STATE_SIZE
)
228 CHECK( cube2
, (ctx
->Texture
.Unit
[2]._ReallyEnabled
& TEXTURE_CUBE_BIT
), 3 + 3*5 - CUBE_STATE_SIZE
)
229 CHECK( cube0_mm
, (ctx
->Texture
.Unit
[0]._ReallyEnabled
& TEXTURE_CUBE_BIT
), 2 + 4*5 - CUBE_STATE_SIZE
)
230 CHECK( cube1_mm
, (ctx
->Texture
.Unit
[1]._ReallyEnabled
& TEXTURE_CUBE_BIT
), 2 + 4*5 - CUBE_STATE_SIZE
)
231 CHECK( cube2_mm
, (ctx
->Texture
.Unit
[2]._ReallyEnabled
& TEXTURE_CUBE_BIT
), 2 + 4*5 - CUBE_STATE_SIZE
)
232 CHECK( fog
, ctx
->Fog
.Enabled
, 0 )
233 CHECK( fog_add4
, ctx
->Fog
.Enabled
, 4 )
234 TCL_CHECK( tcl
, GL_TRUE
, 0 )
235 TCL_CHECK( tcl_add4
, GL_TRUE
, 4 )
236 TCL_CHECK( tcl_tex0
, ctx
->Texture
.Unit
[0]._ReallyEnabled
, 0 )
237 TCL_CHECK( tcl_tex1
, ctx
->Texture
.Unit
[1]._ReallyEnabled
, 0 )
238 TCL_CHECK( tcl_tex2
, ctx
->Texture
.Unit
[2]._ReallyEnabled
, 0 )
239 TCL_CHECK( tcl_tex0_add4
, ctx
->Texture
.Unit
[0]._ReallyEnabled
, 4 )
240 TCL_CHECK( tcl_tex1_add4
, ctx
->Texture
.Unit
[1]._ReallyEnabled
, 4 )
241 TCL_CHECK( tcl_tex2_add4
, ctx
->Texture
.Unit
[2]._ReallyEnabled
, 4 )
242 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
, 0 )
243 TCL_CHECK( tcl_lighting_add4
, ctx
->Light
.Enabled
, 4 )
244 TCL_CHECK( tcl_eyespace_or_lighting
, ctx
->_NeedEyeCoords
|| ctx
->Light
.Enabled
, 0 )
245 TCL_CHECK( tcl_eyespace_or_lighting_add4
, ctx
->_NeedEyeCoords
|| ctx
->Light
.Enabled
, 4 )
246 TCL_CHECK( tcl_lit0
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[0].Enabled
, 0 )
247 TCL_CHECK( tcl_lit1
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[1].Enabled
, 0 )
248 TCL_CHECK( tcl_lit2
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[2].Enabled
, 0 )
249 TCL_CHECK( tcl_lit3
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[3].Enabled
, 0 )
250 TCL_CHECK( tcl_lit4
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[4].Enabled
, 0 )
251 TCL_CHECK( tcl_lit5
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[5].Enabled
, 0 )
252 TCL_CHECK( tcl_lit6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[6].Enabled
, 0 )
253 TCL_CHECK( tcl_lit7
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[7].Enabled
, 0 )
254 TCL_CHECK( tcl_lit0_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[0].Enabled
, 6 )
255 TCL_CHECK( tcl_lit1_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[1].Enabled
, 6 )
256 TCL_CHECK( tcl_lit2_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[2].Enabled
, 6 )
257 TCL_CHECK( tcl_lit3_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[3].Enabled
, 6 )
258 TCL_CHECK( tcl_lit4_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[4].Enabled
, 6 )
259 TCL_CHECK( tcl_lit5_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[5].Enabled
, 6 )
260 TCL_CHECK( tcl_lit6_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[6].Enabled
, 6 )
261 TCL_CHECK( tcl_lit7_add6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[7].Enabled
, 6 )
262 TCL_CHECK( tcl_ucp0
, (ctx
->Transform
.ClipPlanesEnabled
& 0x1), 0 )
263 TCL_CHECK( tcl_ucp1
, (ctx
->Transform
.ClipPlanesEnabled
& 0x2), 0 )
264 TCL_CHECK( tcl_ucp2
, (ctx
->Transform
.ClipPlanesEnabled
& 0x4), 0 )
265 TCL_CHECK( tcl_ucp3
, (ctx
->Transform
.ClipPlanesEnabled
& 0x8), 0 )
266 TCL_CHECK( tcl_ucp4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x10), 0 )
267 TCL_CHECK( tcl_ucp5
, (ctx
->Transform
.ClipPlanesEnabled
& 0x20), 0 )
268 TCL_CHECK( tcl_ucp0_add4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x1), 4 )
269 TCL_CHECK( tcl_ucp1_add4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x2), 4 )
270 TCL_CHECK( tcl_ucp2_add4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x4), 4 )
271 TCL_CHECK( tcl_ucp3_add4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x8), 4 )
272 TCL_CHECK( tcl_ucp4_add4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x10), 4 )
273 TCL_CHECK( tcl_ucp5_add4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x20), 4 )
274 TCL_CHECK( tcl_eyespace_or_fog
, ctx
->_NeedEyeCoords
|| ctx
->Fog
.Enabled
, 0 )
275 TCL_CHECK( tcl_eyespace_or_fog_add4
, ctx
->_NeedEyeCoords
|| ctx
->Fog
.Enabled
, 4 )
277 CHECK( txr0
, (ctx
->Texture
.Unit
[0]._ReallyEnabled
& TEXTURE_RECT_BIT
), 0 )
278 CHECK( txr1
, (ctx
->Texture
.Unit
[1]._ReallyEnabled
& TEXTURE_RECT_BIT
), 0 )
279 CHECK( txr2
, (ctx
->Texture
.Unit
[2]._ReallyEnabled
& TEXTURE_RECT_BIT
), 0 )
281 #define OUT_VEC(hdr, data) do { \
282 drm_radeon_cmd_header_t h; \
284 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
286 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
287 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
288 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
289 OUT_BATCH_TABLE((data), h.vectors.count); \
292 #define OUT_SCL(hdr, data) do { \
293 drm_radeon_cmd_header_t h; \
295 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
296 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
297 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
298 OUT_BATCH_TABLE((data), h.scalars.count); \
301 static void scl_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
303 r100ContextPtr r100
= R100_CONTEXT(ctx
);
304 BATCH_LOCALS(&r100
->radeon
);
305 uint32_t dwords
= atom
->check(ctx
, atom
);
307 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
308 OUT_SCL(atom
->cmd
[0], atom
->cmd
+1);
313 static void vec_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
315 r100ContextPtr r100
= R100_CONTEXT(ctx
);
316 BATCH_LOCALS(&r100
->radeon
);
317 uint32_t dwords
= atom
->check(ctx
, atom
);
319 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
320 OUT_VEC(atom
->cmd
[0], atom
->cmd
+1);
325 static void lit_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
327 r100ContextPtr r100
= R100_CONTEXT(ctx
);
328 BATCH_LOCALS(&r100
->radeon
);
329 uint32_t dwords
= atom
->check(ctx
, atom
);
331 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
332 OUT_VEC(atom
->cmd
[LIT_CMD_0
], atom
->cmd
+1);
333 OUT_SCL(atom
->cmd
[LIT_CMD_1
], atom
->cmd
+LIT_CMD_1
+1);
337 static void ctx_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
339 r100ContextPtr r100
= R100_CONTEXT(ctx
);
340 BATCH_LOCALS(&r100
->radeon
);
341 struct radeon_renderbuffer
*rrb
;
343 uint32_t zbpitch
, depth_fmt
;
344 uint32_t dwords
= atom
->check(ctx
, atom
);
346 /* output the first 7 bytes of context */
347 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
348 OUT_BATCH_TABLE(atom
->cmd
, 5);
350 rrb
= radeon_get_depthbuffer(&r100
->radeon
);
355 zbpitch
= (rrb
->pitch
/ rrb
->cpp
);
356 if (r100
->using_hyperz
)
357 zbpitch
|= RADEON_DEPTH_HYPERZ
;
359 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
362 depth_fmt
= RADEON_DEPTH_FORMAT_24BIT_INT_Z
;
364 depth_fmt
= RADEON_DEPTH_FORMAT_16BIT_INT_Z
;
365 atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_DEPTH_FORMAT_MASK
;
366 atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
] |= depth_fmt
;
369 OUT_BATCH(atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
]);
370 OUT_BATCH(atom
->cmd
[CTX_CMD_1
]);
371 OUT_BATCH(atom
->cmd
[CTX_PP_CNTL
]);
373 rrb
= radeon_get_colorbuffer(&r100
->radeon
);
374 if (!rrb
|| !rrb
->bo
) {
375 OUT_BATCH(atom
->cmd
[CTX_RB3D_CNTL
]);
376 OUT_BATCH(atom
->cmd
[CTX_RB3D_COLOROFFSET
]);
378 atom
->cmd
[CTX_RB3D_CNTL
] &= ~(0xf << 10);
380 atom
->cmd
[CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB8888
;
382 atom
->cmd
[CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_RGB565
;
384 OUT_BATCH(atom
->cmd
[CTX_RB3D_CNTL
]);
385 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
388 OUT_BATCH(atom
->cmd
[CTX_CMD_2
]);
390 if (!rrb
|| !rrb
->bo
) {
391 OUT_BATCH(atom
->cmd
[CTX_RB3D_COLORPITCH
]);
393 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
394 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
395 cbpitch
|= RADEON_COLOR_TILE_ENABLE
;
402 static int check_always_ctx( GLcontext
*ctx
, struct radeon_state_atom
*atom
)
404 r100ContextPtr r100
= R100_CONTEXT(ctx
);
405 struct radeon_renderbuffer
*rrb
, *drb
;
408 rrb
= radeon_get_colorbuffer(&r100
->radeon
);
409 if (!rrb
|| !rrb
->bo
) {
413 drb
= radeon_get_depthbuffer(&r100
->radeon
);
424 static void ctx_emit_cs(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
426 r100ContextPtr r100
= R100_CONTEXT(ctx
);
427 BATCH_LOCALS(&r100
->radeon
);
428 struct radeon_renderbuffer
*rrb
, *drb
;
429 uint32_t cbpitch
= 0;
430 uint32_t zbpitch
= 0;
431 uint32_t dwords
= atom
->check(ctx
, atom
);
434 rrb
= radeon_get_colorbuffer(&r100
->radeon
);
435 if (!rrb
|| !rrb
->bo
) {
436 fprintf(stderr
, "no rrb\n");
440 atom
->cmd
[CTX_RB3D_CNTL
] &= ~(0xf << 10);
442 atom
->cmd
[CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB8888
;
443 else switch (rrb
->base
.Format
) {
444 case MESA_FORMAT_RGB565
:
445 atom
->cmd
[CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_RGB565
;
447 case MESA_FORMAT_ARGB4444
:
448 atom
->cmd
[CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB4444
;
450 case MESA_FORMAT_ARGB1555
:
451 atom
->cmd
[CTX_RB3D_CNTL
] |= RADEON_COLOR_FORMAT_ARGB1555
;
454 _mesa_problem(ctx
, "unexpected format in ctx_emit_cs()");
457 cbpitch
= (rrb
->pitch
/ rrb
->cpp
);
458 if (rrb
->bo
->flags
& RADEON_BO_FLAGS_MACRO_TILE
)
459 cbpitch
|= R200_COLOR_TILE_ENABLE
;
461 drb
= radeon_get_depthbuffer(&r100
->radeon
);
463 zbpitch
= (drb
->pitch
/ drb
->cpp
);
465 depth_fmt
= RADEON_DEPTH_FORMAT_24BIT_INT_Z
;
467 depth_fmt
= RADEON_DEPTH_FORMAT_16BIT_INT_Z
;
468 atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
] &= ~RADEON_DEPTH_FORMAT_MASK
;
469 atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
] |= depth_fmt
;
473 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
475 /* In the CS case we need to split this up */
476 OUT_BATCH(CP_PACKET0(packet
[0].start
, 3));
477 OUT_BATCH_TABLE((atom
->cmd
+ 1), 4);
480 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET
, 0));
481 OUT_BATCH_RELOC(0, drb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
483 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH
, 0));
487 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL
, 0));
488 OUT_BATCH(atom
->cmd
[CTX_RB3D_ZSTENCILCNTL
]);
489 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL
, 1));
490 OUT_BATCH(atom
->cmd
[CTX_PP_CNTL
]);
491 OUT_BATCH(atom
->cmd
[CTX_RB3D_CNTL
]);
494 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET
, 0));
495 OUT_BATCH_RELOC(0, rrb
->bo
, 0, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
497 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH
, 0));
498 OUT_BATCH_RELOC(cbpitch
, rrb
->bo
, cbpitch
, 0, RADEON_GEM_DOMAIN_VRAM
, 0);
501 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
502 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
506 BEGIN_BATCH_NO_AUTOSTATE(4);
507 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT
, 0));
509 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT
, 0));
511 OUT_BATCH(((rrb
->base
.Width
- 1) << RADEON_RE_WIDTH_SHIFT
) |
512 ((rrb
->base
.Height
- 1) << RADEON_RE_HEIGHT_SHIFT
));
519 static void cube_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
521 r100ContextPtr r100
= R100_CONTEXT(ctx
);
522 BATCH_LOCALS(&r100
->radeon
);
523 uint32_t dwords
= atom
->check(ctx
, atom
);
524 int i
= atom
->idx
, j
;
525 radeonTexObj
*t
= r100
->state
.texture
.unit
[i
].texobj
;
526 radeon_mipmap_level
*lvl
;
528 if (!(ctx
->Texture
.Unit
[i
]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
537 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
538 OUT_BATCH_TABLE(atom
->cmd
, 3);
539 lvl
= &t
->mt
->levels
[0];
540 for (j
= 0; j
< 5; j
++) {
541 OUT_BATCH_RELOC(lvl
->faces
[j
].offset
, t
->mt
->bo
, lvl
->faces
[j
].offset
,
542 RADEON_GEM_DOMAIN_VRAM
, 0, 0);
547 static void cube_emit_cs(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
549 r100ContextPtr r100
= R100_CONTEXT(ctx
);
550 BATCH_LOCALS(&r100
->radeon
);
551 uint32_t dwords
= atom
->check(ctx
, atom
);
552 int i
= atom
->idx
, j
;
553 radeonTexObj
*t
= r100
->state
.texture
.unit
[i
].texobj
;
554 radeon_mipmap_level
*lvl
;
557 if (!(ctx
->Texture
.Unit
[i
]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
567 case 1: base_reg
= RADEON_PP_CUBIC_OFFSET_T1_0
; break;
568 case 2: base_reg
= RADEON_PP_CUBIC_OFFSET_T2_0
; break;
570 case 0: base_reg
= RADEON_PP_CUBIC_OFFSET_T0_0
; break;
572 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
573 OUT_BATCH_TABLE(atom
->cmd
, 2);
574 lvl
= &t
->mt
->levels
[0];
575 for (j
= 0; j
< 5; j
++) {
576 OUT_BATCH(CP_PACKET0(base_reg
+ (4 * j
), 0));
577 OUT_BATCH_RELOC(lvl
->faces
[j
].offset
, t
->mt
->bo
, lvl
->faces
[j
].offset
,
578 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
583 static void tex_emit(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
585 r100ContextPtr r100
= R100_CONTEXT(ctx
);
586 BATCH_LOCALS(&r100
->radeon
);
587 uint32_t dwords
= atom
->cmd_size
;
589 radeonTexObj
*t
= r100
->state
.texture
.unit
[i
].texobj
;
590 radeon_mipmap_level
*lvl
;
592 if (t
&& t
->mt
&& !t
->image_override
)
594 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
596 OUT_BATCH_TABLE(atom
->cmd
, 3);
597 if (t
&& t
->mt
&& !t
->image_override
) {
598 if ((ctx
->Texture
.Unit
[i
]._ReallyEnabled
& TEXTURE_CUBE_BIT
)) {
599 lvl
= &t
->mt
->levels
[0];
600 OUT_BATCH_RELOC(lvl
->faces
[5].offset
, t
->mt
->bo
, lvl
->faces
[5].offset
,
601 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
603 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, 0,
604 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
607 /* workaround for old CS mechanism */
608 OUT_BATCH(r100
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
]);
609 // OUT_BATCH(r100->radeon.radeonScreen);
611 OUT_BATCH(t
->override_offset
);
614 OUT_BATCH_TABLE((atom
->cmd
+4), 5);
618 static void tex_emit_cs(GLcontext
*ctx
, struct radeon_state_atom
*atom
)
620 r100ContextPtr r100
= R100_CONTEXT(ctx
);
621 BATCH_LOCALS(&r100
->radeon
);
622 uint32_t dwords
= atom
->cmd_size
;
624 radeonTexObj
*t
= r100
->state
.texture
.unit
[i
].texobj
;
625 radeon_mipmap_level
*lvl
;
631 if (!t
->mt
&& !t
->bo
)
639 BEGIN_BATCH_NO_AUTOSTATE(dwords
);
641 OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0
+ (24 * i
), 1));
642 OUT_BATCH_TABLE((atom
->cmd
+ 1), 2);
645 OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0
+ (24 * i
), 0));
646 if (t
->mt
&& !t
->image_override
) {
647 if ((ctx
->Texture
.Unit
[i
]._ReallyEnabled
& TEXTURE_CUBE_BIT
)) {
648 lvl
= &t
->mt
->levels
[t
->minLod
];
649 OUT_BATCH_RELOC(lvl
->faces
[5].offset
, t
->mt
->bo
, lvl
->faces
[5].offset
,
650 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
652 OUT_BATCH_RELOC(t
->tile_bits
, t
->mt
->bo
, get_base_teximage_offset(t
),
653 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
657 OUT_BATCH_RELOC(t
->tile_bits
, t
->bo
, 0,
658 RADEON_GEM_DOMAIN_GTT
|RADEON_GEM_DOMAIN_VRAM
, 0, 0);
662 OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0
+ (i
* 24), 1));
663 OUT_BATCH_TABLE((atom
->cmd
+4), 2);
664 OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0
+ (i
* 4), 0));
665 OUT_BATCH((atom
->cmd
[TEX_PP_BORDER_COLOR
]));
669 /* Initialize the context's hardware state.
671 void radeonInitState( r100ContextPtr rmesa
)
673 GLcontext
*ctx
= rmesa
->radeon
.glCtx
;
676 rmesa
->radeon
.state
.color
.clear
= 0x00000000;
678 switch ( ctx
->Visual
.depthBits
) {
680 rmesa
->radeon
.state
.depth
.clear
= 0x0000ffff;
681 rmesa
->radeon
.state
.stencil
.clear
= 0x00000000;
684 rmesa
->radeon
.state
.depth
.clear
= 0x00ffffff;
685 rmesa
->radeon
.state
.stencil
.clear
= 0xffff0000;
691 rmesa
->radeon
.Fallback
= 0;
694 rmesa
->radeon
.hw
.max_state_size
= 0;
696 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
698 rmesa->hw.ATOM.cmd_size = SZ; \
699 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
700 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
701 rmesa->hw.ATOM.name = NM; \
702 rmesa->hw.ATOM.is_tcl = FLAG; \
703 rmesa->hw.ATOM.check = check_##CHK; \
704 rmesa->hw.ATOM.dirty = GL_TRUE; \
705 rmesa->hw.ATOM.idx = IDX; \
706 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
709 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
710 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
712 /* Allocate state buffers:
714 ALLOC_STATE( ctx
, always_add4
, CTX_STATE_SIZE
, "CTX/context", 0 );
715 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
716 rmesa
->hw
.ctx
.emit
= ctx_emit_cs
;
717 rmesa
->hw
.ctx
.check
= check_always_ctx
;
719 rmesa
->hw
.ctx
.emit
= ctx_emit
;
720 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
721 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
722 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
723 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
724 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
725 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
726 ALLOC_STATE( tcl
, always
, TCL_STATE_SIZE
, "TCL/tcl", 1 );
727 ALLOC_STATE( mtl
, tcl_lighting
, MTL_STATE_SIZE
, "MTL/material", 1 );
728 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
729 ALLOC_STATE( grd
, always_add2
, GRD_STATE_SIZE
, "GRD/guard-band", 1 );
730 ALLOC_STATE( fog
, fog_add4
, FOG_STATE_SIZE
, "FOG/fog", 1 );
731 ALLOC_STATE( glt
, tcl_lighting_add4
, GLT_STATE_SIZE
, "GLT/light-global", 1 );
732 ALLOC_STATE( eye
, tcl_lighting_add4
, EYE_STATE_SIZE
, "EYE/eye-vector", 1 );
733 ALLOC_STATE_IDX( tex
[0], tex0_mm
, TEX_STATE_SIZE
, "TEX/tex-0", 0, 0);
734 ALLOC_STATE_IDX( tex
[1], tex1_mm
, TEX_STATE_SIZE
, "TEX/tex-1", 0, 1);
735 ALLOC_STATE_IDX( tex
[2], tex2_mm
, TEX_STATE_SIZE
, "TEX/tex-2", 0, 2);
736 ALLOC_STATE( mat
[0], tcl_add4
, MAT_STATE_SIZE
, "MAT/modelproject", 1 );
737 ALLOC_STATE( mat
[1], tcl_eyespace_or_fog_add4
, MAT_STATE_SIZE
, "MAT/modelview", 1 );
738 ALLOC_STATE( mat
[2], tcl_eyespace_or_lighting_add4
, MAT_STATE_SIZE
, "MAT/it-modelview", 1 );
739 ALLOC_STATE( mat
[3], tcl_tex0_add4
, MAT_STATE_SIZE
, "MAT/texmat0", 1 );
740 ALLOC_STATE( mat
[4], tcl_tex1_add4
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
741 ALLOC_STATE( mat
[5], tcl_tex2_add4
, MAT_STATE_SIZE
, "MAT/texmat2", 1 );
742 ALLOC_STATE( lit
[0], tcl_lit0_add6
, LIT_STATE_SIZE
, "LIT/light-0", 1 );
743 ALLOC_STATE( lit
[1], tcl_lit1_add6
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
744 ALLOC_STATE( lit
[2], tcl_lit2_add6
, LIT_STATE_SIZE
, "LIT/light-2", 1 );
745 ALLOC_STATE( lit
[3], tcl_lit3_add6
, LIT_STATE_SIZE
, "LIT/light-3", 1 );
746 ALLOC_STATE( lit
[4], tcl_lit4_add6
, LIT_STATE_SIZE
, "LIT/light-4", 1 );
747 ALLOC_STATE( lit
[5], tcl_lit5_add6
, LIT_STATE_SIZE
, "LIT/light-5", 1 );
748 ALLOC_STATE( lit
[6], tcl_lit6_add6
, LIT_STATE_SIZE
, "LIT/light-6", 1 );
749 ALLOC_STATE( lit
[7], tcl_lit7_add6
, LIT_STATE_SIZE
, "LIT/light-7", 1 );
750 ALLOC_STATE( ucp
[0], tcl_ucp0_add4
, UCP_STATE_SIZE
, "UCP/userclip-0", 1 );
751 ALLOC_STATE( ucp
[1], tcl_ucp1_add4
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
752 ALLOC_STATE( ucp
[2], tcl_ucp2_add4
, UCP_STATE_SIZE
, "UCP/userclip-2", 1 );
753 ALLOC_STATE( ucp
[3], tcl_ucp3_add4
, UCP_STATE_SIZE
, "UCP/userclip-3", 1 );
754 ALLOC_STATE( ucp
[4], tcl_ucp4_add4
, UCP_STATE_SIZE
, "UCP/userclip-4", 1 );
755 ALLOC_STATE( ucp
[5], tcl_ucp5_add4
, UCP_STATE_SIZE
, "UCP/userclip-5", 1 );
757 ALLOC_STATE( grd
, always
, GRD_STATE_SIZE
, "GRD/guard-band", 1 );
758 ALLOC_STATE( fog
, fog
, FOG_STATE_SIZE
, "FOG/fog", 1 );
759 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 1 );
760 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 1 );
761 ALLOC_STATE_IDX( tex
[0], tex0
, TEX_STATE_SIZE
, "TEX/tex-0", 0, 0);
762 ALLOC_STATE_IDX( tex
[1], tex1
, TEX_STATE_SIZE
, "TEX/tex-1", 0, 1);
763 ALLOC_STATE_IDX( tex
[2], tex2
, TEX_STATE_SIZE
, "TEX/tex-2", 0, 2);
764 ALLOC_STATE( mat
[0], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 1 );
765 ALLOC_STATE( mat
[1], tcl_eyespace_or_fog
, MAT_STATE_SIZE
, "MAT/modelview", 1 );
766 ALLOC_STATE( mat
[2], tcl_eyespace_or_lighting
, MAT_STATE_SIZE
, "MAT/it-modelview", 1 );
767 ALLOC_STATE( mat
[3], tcl_tex0
, MAT_STATE_SIZE
, "MAT/texmat0", 1 );
768 ALLOC_STATE( mat
[4], tcl_tex1
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
769 ALLOC_STATE( mat
[5], tcl_tex2
, MAT_STATE_SIZE
, "MAT/texmat2", 1 );
770 ALLOC_STATE( lit
[0], tcl_lit0
, LIT_STATE_SIZE
, "LIT/light-0", 1 );
771 ALLOC_STATE( lit
[1], tcl_lit1
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
772 ALLOC_STATE( lit
[2], tcl_lit2
, LIT_STATE_SIZE
, "LIT/light-2", 1 );
773 ALLOC_STATE( lit
[3], tcl_lit3
, LIT_STATE_SIZE
, "LIT/light-3", 1 );
774 ALLOC_STATE( lit
[4], tcl_lit4
, LIT_STATE_SIZE
, "LIT/light-4", 1 );
775 ALLOC_STATE( lit
[5], tcl_lit5
, LIT_STATE_SIZE
, "LIT/light-5", 1 );
776 ALLOC_STATE( lit
[6], tcl_lit6
, LIT_STATE_SIZE
, "LIT/light-6", 1 );
777 ALLOC_STATE( lit
[7], tcl_lit7
, LIT_STATE_SIZE
, "LIT/light-7", 1 );
778 ALLOC_STATE( ucp
[0], tcl_ucp0
, UCP_STATE_SIZE
, "UCP/userclip-0", 1 );
779 ALLOC_STATE( ucp
[1], tcl_ucp1
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
780 ALLOC_STATE( ucp
[2], tcl_ucp2
, UCP_STATE_SIZE
, "UCP/userclip-2", 1 );
781 ALLOC_STATE( ucp
[3], tcl_ucp3
, UCP_STATE_SIZE
, "UCP/userclip-3", 1 );
782 ALLOC_STATE( ucp
[4], tcl_ucp4
, UCP_STATE_SIZE
, "UCP/userclip-4", 1 );
783 ALLOC_STATE( ucp
[5], tcl_ucp5
, UCP_STATE_SIZE
, "UCP/userclip-5", 1 );
786 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
787 ALLOC_STATE( stp
, always
, STP_STATE_SIZE
, "STP/stp", 0 );
790 for (i
= 0; i
< 3; i
++) {
791 if (rmesa
->radeon
.radeonScreen
->kernel_mm
)
792 rmesa
->hw
.tex
[i
].emit
= tex_emit_cs
;
794 rmesa
->hw
.tex
[i
].emit
= tex_emit
;
796 if (rmesa
->radeon
.radeonScreen
->drmSupportsCubeMapsR100
)
798 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
799 ALLOC_STATE_IDX( cube
[0], cube0_mm
, CUBE_STATE_SIZE
, "CUBE/cube-0", 0, 0 );
800 ALLOC_STATE_IDX( cube
[1], cube1_mm
, CUBE_STATE_SIZE
, "CUBE/cube-1", 0, 1 );
801 ALLOC_STATE_IDX( cube
[2], cube2_mm
, CUBE_STATE_SIZE
, "CUBE/cube-2", 0, 2 );
802 for (i
= 0; i
< 3; i
++)
803 rmesa
->hw
.cube
[i
].emit
= cube_emit_cs
;
805 ALLOC_STATE_IDX( cube
[0], cube0
, CUBE_STATE_SIZE
, "CUBE/cube-0", 0, 0 );
806 ALLOC_STATE_IDX( cube
[1], cube1
, CUBE_STATE_SIZE
, "CUBE/cube-1", 0, 1 );
807 ALLOC_STATE_IDX( cube
[2], cube2
, CUBE_STATE_SIZE
, "CUBE/cube-2", 0, 2 );
808 for (i
= 0; i
< 3; i
++)
809 rmesa
->hw
.cube
[i
].emit
= cube_emit
;
814 ALLOC_STATE_IDX( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/cube-0", 0, 0 );
815 ALLOC_STATE_IDX( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/cube-1", 0, 1 );
816 ALLOC_STATE_IDX( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/cube-2", 0, 2 );
818 ALLOC_STATE_IDX( txr
[0], txr0
, TXR_STATE_SIZE
, "TXR/txr-0", 0, 0 );
819 ALLOC_STATE_IDX( txr
[1], txr1
, TXR_STATE_SIZE
, "TXR/txr-1", 0, 1 );
820 ALLOC_STATE_IDX( txr
[2], txr2
, TXR_STATE_SIZE
, "TXR/txr-2", 0, 2 );
822 radeonSetUpAtomList( rmesa
);
824 /* Fill in the packet headers:
826 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_MISC
);
827 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CNTL
);
828 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(rmesa
, RADEON_EMIT_RB3D_COLORPITCH
);
829 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_RE_LINE_PATTERN
);
830 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_SE_LINE_WIDTH
);
831 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_RB3D_STENCILREFMASK
);
832 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_VPORT_XSCALE
);
833 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_CNTL
);
834 rmesa
->hw
.set
.cmd
[SET_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_SE_CNTL_STATUS
);
835 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_RE_MISC
);
836 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TXFILTER_0
);
837 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_BORDER_COLOR_0
);
838 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TXFILTER_1
);
839 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_BORDER_COLOR_1
);
840 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TXFILTER_2
);
841 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_BORDER_COLOR_2
);
842 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_FACES_0
);
843 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_OFFSETS_T0
);
844 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_FACES_1
);
845 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_OFFSETS_T1
);
846 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_FACES_2
);
847 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(rmesa
, RADEON_EMIT_PP_CUBIC_OFFSETS_T2
);
848 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_ZBIAS_FACTOR
);
849 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT
);
850 rmesa
->hw
.mtl
.cmd
[MTL_CMD_0
] =
851 cmdpkt(rmesa
, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED
);
852 rmesa
->hw
.txr
[0].cmd
[TXR_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TEX_SIZE_0
);
853 rmesa
->hw
.txr
[1].cmd
[TXR_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TEX_SIZE_1
);
854 rmesa
->hw
.txr
[2].cmd
[TXR_CMD_0
] = cmdpkt(rmesa
, RADEON_EMIT_PP_TEX_SIZE_2
);
855 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
856 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
857 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
858 cmdvec( RADEON_VS_FOG_PARAM_ADDR
, 1, 4 );
859 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
860 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
861 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
862 cmdvec( RADEON_VS_EYE_VECTOR_ADDR
, 1, 4 );
864 for (i
= 0 ; i
< 6; i
++) {
865 rmesa
->hw
.mat
[i
].cmd
[MAT_CMD_0
] =
866 cmdvec( RADEON_VS_MATRIX_0_ADDR
+ i
*4, 1, 16);
869 for (i
= 0 ; i
< 8; i
++) {
870 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
871 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
872 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
873 cmdscl( RADEON_SS_LIGHT_DCD_ADDR
+ i
, 8, 6 );
876 for (i
= 0 ; i
< 6; i
++) {
877 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
878 cmdvec( RADEON_VS_UCP_ADDR
+ i
, 1, 4 );
881 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
882 rmesa
->hw
.stp
.cmd
[STP_CMD_0
] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR
, 0);
883 rmesa
->hw
.stp
.cmd
[STP_DATA_0
] = 0;
884 rmesa
->hw
.stp
.cmd
[STP_CMD_1
] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA
, 31);
886 rmesa
->hw
.grd
.emit
= scl_emit
;
887 rmesa
->hw
.fog
.emit
= vec_emit
;
888 rmesa
->hw
.glt
.emit
= vec_emit
;
889 rmesa
->hw
.eye
.emit
= vec_emit
;
891 for (i
= 0; i
< 6; i
++)
892 rmesa
->hw
.mat
[i
].emit
= vec_emit
;
894 for (i
= 0; i
< 8; i
++)
895 rmesa
->hw
.lit
[i
].emit
= lit_emit
;
897 for (i
= 0; i
< 6; i
++)
898 rmesa
->hw
.ucp
[i
].emit
= vec_emit
;
901 rmesa
->last_ReallyEnabled
= -1;
903 /* Initial Harware state:
905 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (RADEON_ALPHA_TEST_PASS
|
906 RADEON_CHROMA_FUNC_FAIL
|
907 RADEON_CHROMA_KEY_NEAREST
|
908 RADEON_SHADOW_FUNC_EQUAL
|
909 RADEON_SHADOW_PASS_1
/*|
910 RADEON_RIGHT_HAND_CUBE_OGL */);
912 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (RADEON_FOG_VERTEX
|
913 /* this bit unused for vertex fog */
914 RADEON_FOG_USE_DEPTH
);
916 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
918 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (RADEON_COMB_FCN_ADD_CLAMP
|
919 RADEON_SRC_BLEND_GL_ONE
|
920 RADEON_DST_BLEND_GL_ZERO
);
922 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (RADEON_Z_TEST_LESS
|
923 RADEON_STENCIL_TEST_ALWAYS
|
924 RADEON_STENCIL_FAIL_KEEP
|
925 RADEON_STENCIL_ZPASS_KEEP
|
926 RADEON_STENCIL_ZFAIL_KEEP
|
927 RADEON_Z_WRITE_ENABLE
);
929 if (rmesa
->using_hyperz
) {
930 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_COMPRESSION_ENABLE
|
931 RADEON_Z_DECOMPRESSION_ENABLE
;
932 if (rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
933 /* works for q3, but slight rendering errors with glxgears ? */
934 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
935 /* need this otherwise get lots of lockups with q3 ??? */
936 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_FORCE_Z_DIRTY
;
940 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (RADEON_SCISSOR_ENABLE
|
941 RADEON_ANTI_ALIAS_NONE
);
943 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = (RADEON_PLANE_MASK_ENABLE
|
946 switch ( driQueryOptioni( &rmesa
->radeon
.optionCache
, "dither_mode" ) ) {
947 case DRI_CONF_DITHER_XERRORDIFFRESET
:
948 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_INIT
;
950 case DRI_CONF_DITHER_ORDERED
:
951 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_SCALE_DITHER_ENABLE
;
954 if ( driQueryOptioni( &rmesa
->radeon
.optionCache
, "round_mode" ) ==
955 DRI_CONF_ROUND_ROUND
)
956 rmesa
->radeon
.state
.color
.roundEnable
= RADEON_ROUND_ENABLE
;
958 rmesa
->radeon
.state
.color
.roundEnable
= 0;
959 if ( driQueryOptioni (&rmesa
->radeon
.optionCache
, "color_reduction" ) ==
960 DRI_CONF_COLOR_REDUCTION_DITHER
)
961 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
;
963 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->radeon
.state
.color
.roundEnable
;
966 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (RADEON_FFACE_CULL_CCW
|
969 /* RADEON_BADVTX_CULL_DISABLE | */
970 RADEON_FLAT_SHADE_VTX_LAST
|
971 RADEON_DIFFUSE_SHADE_GOURAUD
|
972 RADEON_ALPHA_SHADE_GOURAUD
|
973 RADEON_SPECULAR_SHADE_GOURAUD
|
974 RADEON_FOG_SHADE_GOURAUD
|
975 RADEON_VPORT_XY_XFORM_ENABLE
|
976 RADEON_VPORT_Z_XFORM_ENABLE
|
977 RADEON_VTX_PIX_CENTER_OGL
|
978 RADEON_ROUND_MODE_TRUNC
|
979 RADEON_ROUND_PREC_8TH_PIX
);
981 rmesa
->hw
.set
.cmd
[SET_SE_CNTL_STATUS
] =
982 #ifdef MESA_BIG_ENDIAN
983 RADEON_VC_32BIT_SWAP
;
988 if (!(rmesa
->radeon
.radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
989 rmesa
->hw
.set
.cmd
[SET_SE_CNTL_STATUS
] |= RADEON_TCL_BYPASS
;
992 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = (
993 RADEON_VTX_W0_IS_NOT_1_OVER_W0
|
994 RADEON_TEX1_W_ROUTING_USE_Q1
);
997 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
999 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
1000 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT
) |
1001 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT
));
1003 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
1005 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
1006 ((0x00 << RADEON_STENCIL_REF_SHIFT
) |
1007 (0xff << RADEON_STENCIL_MASK_SHIFT
) |
1008 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT
));
1010 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = RADEON_ROP_COPY
;
1011 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
1013 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
1014 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT
) |
1015 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT
) |
1016 RADEON_STIPPLE_BIG_BIT_ORDER
);
1018 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
1019 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
1020 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
1021 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
1022 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
1023 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
1025 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
1026 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = RADEON_BORDER_MODE_OGL
;
1027 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
1028 (RADEON_TXFORMAT_ENDIAN_NO_SWAP
|
1029 RADEON_TXFORMAT_PERSPECTIVE_ENABLE
|
1030 (i
<< 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
1031 (2 << RADEON_TXFORMAT_WIDTH_SHIFT
) |
1032 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT
));
1034 /* Initialize the texture offset to the start of the card texture heap */
1035 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
1036 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1038 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
1039 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXCBLEND
] =
1040 (RADEON_COLOR_ARG_A_ZERO
|
1041 RADEON_COLOR_ARG_B_ZERO
|
1042 RADEON_COLOR_ARG_C_CURRENT_COLOR
|
1043 RADEON_BLEND_CTL_ADD
|
1046 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXABLEND
] =
1047 (RADEON_ALPHA_ARG_A_ZERO
|
1048 RADEON_ALPHA_ARG_B_ZERO
|
1049 RADEON_ALPHA_ARG_C_CURRENT_ALPHA
|
1050 RADEON_BLEND_CTL_ADD
|
1053 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TFACTOR
] = 0;
1055 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
1056 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_0
] =
1057 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
1058 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_1
] =
1059 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
1060 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_2
] =
1061 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
1062 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_3
] =
1063 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
1064 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_4
] =
1065 rmesa
->radeon
.radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
1068 /* Can only add ST1 at the time of doing some multitex but can keep
1069 * it after that. Errors if DIFFUSE is missing.
1071 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] =
1072 (RADEON_TCL_VTX_Z0
|
1074 RADEON_TCL_VTX_PK_DIFFUSE
1075 ); /* need to keep this uptodate */
1077 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] =
1078 ( RADEON_TCL_COMPUTE_XYZW
|
1079 (RADEON_TCL_TEX_INPUT_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
) |
1080 (RADEON_TCL_TEX_INPUT_TEX_1
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
) |
1081 (RADEON_TCL_TEX_INPUT_TEX_2
<< RADEON_TCL_TEX_2_OUTPUT_SHIFT
));
1085 rmesa
->hw
.tcl
.cmd
[TCL_MATRIX_SELECT_0
] =
1086 ((MODEL
<< RADEON_MODELVIEW_0_SHIFT
) |
1087 (MODEL_IT
<< RADEON_IT_MODELVIEW_0_SHIFT
));
1089 rmesa
->hw
.tcl
.cmd
[TCL_MATRIX_SELECT_1
] =
1090 ((MODEL_PROJ
<< RADEON_MODELPROJECT_0_SHIFT
) |
1091 (TEXMAT_0
<< RADEON_TEXMAT_0_SHIFT
) |
1092 (TEXMAT_1
<< RADEON_TEXMAT_1_SHIFT
) |
1093 (TEXMAT_2
<< RADEON_TEXMAT_2_SHIFT
));
1095 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
1096 (RADEON_UCP_IN_CLIP_SPACE
|
1097 RADEON_CULL_FRONT_IS_CCW
);
1099 rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] = 0;
1101 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] =
1102 (RADEON_SPECULAR_LIGHTS
|
1103 RADEON_DIFFUSE_SPECULAR_COMBINE
|
1104 RADEON_LOCAL_LIGHT_VEC_GL
|
1105 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_EMISSIVE_SOURCE_SHIFT
) |
1106 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_AMBIENT_SOURCE_SHIFT
) |
1107 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_DIFFUSE_SOURCE_SHIFT
) |
1108 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_SPECULAR_SOURCE_SHIFT
));
1110 for (i
= 0 ; i
< 8; i
++) {
1111 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
1112 GLenum p
= GL_LIGHT0
+ i
;
1113 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
1115 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
1116 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
1117 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
1118 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, NULL
);
1119 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, NULL
);
1120 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
1121 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
1122 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
1123 &l
->ConstantAttenuation
);
1124 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
1125 &l
->LinearAttenuation
);
1126 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
1127 &l
->QuadraticAttenuation
);
1128 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
1131 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
1132 ctx
->Light
.Model
.Ambient
);
1134 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
1136 for (i
= 0 ; i
< 6; i
++) {
1137 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
1140 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, NULL
);
1141 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
1142 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
1143 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
1144 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
1145 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, NULL
);
1147 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
1148 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
1149 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
1150 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
1152 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
1153 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
1154 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
1155 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
1157 if (rmesa
->radeon
.radeonScreen
->kernel_mm
) {
1158 radeon_init_query_stateobj(&rmesa
->radeon
, R100_QUERYOBJ_CMDSIZE
);
1159 rmesa
->radeon
.query
.queryobj
.cmd
[R100_QUERYOBJ_CMD_0
] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA
, 0);
1160 rmesa
->radeon
.query
.queryobj
.cmd
[R100_QUERYOBJ_DATA_0
] = 0;
1163 rmesa
->radeon
.hw
.all_dirty
= GL_TRUE
;
1165 rcommonInitCmdBuf(&rmesa
->radeon
);