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radeon/r300: Code clean up and logic fix.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c
1 /*
2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
28 */
29
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
33
34 #include "swrast/swrast.h"
35 #include "vbo/vbo.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
39
40 #include "radeon_context.h"
41 #include "radeon_mipmap_tree.h"
42 #include "radeon_ioctl.h"
43 #include "radeon_state.h"
44 #include "radeon_tcl.h"
45 #include "radeon_tex.h"
46 #include "radeon_swtcl.h"
47
48 #include "../r200/r200_reg.h"
49
50 #include "xmlpool.h"
51
52 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
53 * 1.3 cmdbuffers allow all previous state to be updated as well as
54 * the tcl scalar and vector areas.
55 */
56 static struct {
57 int start;
58 int len;
59 const char *name;
60 } packet[RADEON_MAX_STATE_PACKETS] = {
61 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
62 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
63 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
64 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
65 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
66 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
67 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
68 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
69 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
70 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
71 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
72 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
73 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
74 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
75 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
76 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
77 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
78 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
79 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
80 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
81 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
82 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
83 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
84 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
85 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
86 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
87 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
88 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
89 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
90 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
91 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
92 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
93 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
94 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
95 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
96 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
97 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
98 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
99 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
100 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
101 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
102 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
103 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
104 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
105 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
106 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
107 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
108 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
109 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
110 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
111 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
112 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
113 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
114 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
115 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
116 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
117 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
118 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
119 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
120 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
121 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
122 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
123 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
124 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
125 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
126 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
127 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
128 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
129 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
130 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
131 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
132 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
133 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
134 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
135 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
136 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
137 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
138 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
139 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
140 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
141 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
142 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
143 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
144 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
145 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
146 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
147 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
148 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
149 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
150 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
151 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
152 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
153 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
154 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
155 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
156 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
157 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
158 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
159 };
160
161 /* =============================================================
162 * State initialization
163 */
164 static int cmdpkt( r100ContextPtr rmesa, int id )
165 {
166 drm_radeon_cmd_header_t h;
167
168 if (rmesa->radeon.radeonScreen->kernel_mm) {
169 return CP_PACKET0(packet[id].start, packet[id].len - 1);
170 } else {
171 h.i = 0;
172 h.packet.cmd_type = RADEON_CMD_PACKET;
173 h.packet.packet_id = id;
174 }
175 return h.i;
176 }
177
178 static int cmdvec( int offset, int stride, int count )
179 {
180 drm_radeon_cmd_header_t h;
181 h.i = 0;
182 h.vectors.cmd_type = RADEON_CMD_VECTORS;
183 h.vectors.offset = offset;
184 h.vectors.stride = stride;
185 h.vectors.count = count;
186 return h.i;
187 }
188
189 static int cmdscl( int offset, int stride, int count )
190 {
191 drm_radeon_cmd_header_t h;
192 h.i = 0;
193 h.scalars.cmd_type = RADEON_CMD_SCALARS;
194 h.scalars.offset = offset;
195 h.scalars.stride = stride;
196 h.scalars.count = count;
197 return h.i;
198 }
199
200 #define CHECK( NM, FLAG, ADD ) \
201 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
202 { \
203 return FLAG ? atom->cmd_size + (ADD) : 0; \
204 }
205
206 #define TCL_CHECK( NM, FLAG, ADD ) \
207 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
208 { \
209 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
210 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
211 }
212
213
214 CHECK( always, GL_TRUE, 0 )
215 CHECK( always_add2, GL_TRUE, 2 )
216 CHECK( never, GL_FALSE, 0 )
217 CHECK( tex0_mm, ctx->Texture.Unit[0]._ReallyEnabled, 3 )
218 CHECK( tex1_mm, ctx->Texture.Unit[1]._ReallyEnabled, 3 )
219 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
220 CHECK( tex2_mm, ctx->Texture._EnabledUnits, 3 )
221 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled, 2 )
222 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled, 2 )
223 CHECK( tex2, ctx->Texture._EnabledUnits, 2 )
224 CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE )
225 CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE )
226 CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE )
227 CHECK( cube0_mm, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
228 CHECK( cube1_mm, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
229 CHECK( cube2_mm, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
230 CHECK( fog, ctx->Fog.Enabled, 0 )
231 CHECK( fog_add4, ctx->Fog.Enabled, 4 )
232 TCL_CHECK( tcl, GL_TRUE, 0 )
233 TCL_CHECK( tcl_add4, GL_TRUE, 4 )
234 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled, 0 )
235 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled, 0 )
236 TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled, 0 )
237 TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._ReallyEnabled, 4 )
238 TCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._ReallyEnabled, 4 )
239 TCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._ReallyEnabled, 4 )
240 TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 )
241 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
242 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled, 0 )
243 TCL_CHECK( tcl_eyespace_or_lighting_add4, ctx->_NeedEyeCoords || ctx->Light.Enabled, 4 )
244 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 0 )
245 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 0 )
246 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 0 )
247 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 0 )
248 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 0 )
249 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 0 )
250 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 0 )
251 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 0 )
252 TCL_CHECK( tcl_lit0_add6, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 6 )
253 TCL_CHECK( tcl_lit1_add6, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 6 )
254 TCL_CHECK( tcl_lit2_add6, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 6 )
255 TCL_CHECK( tcl_lit3_add6, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 6 )
256 TCL_CHECK( tcl_lit4_add6, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 6 )
257 TCL_CHECK( tcl_lit5_add6, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 6 )
258 TCL_CHECK( tcl_lit6_add6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 6 )
259 TCL_CHECK( tcl_lit7_add6, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 6 )
260 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1), 0 )
261 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2), 0 )
262 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4), 0 )
263 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8), 0 )
264 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10), 0 )
265 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20), 0 )
266 TCL_CHECK( tcl_ucp0_add4, (ctx->Transform.ClipPlanesEnabled & 0x1), 4 )
267 TCL_CHECK( tcl_ucp1_add4, (ctx->Transform.ClipPlanesEnabled & 0x2), 4 )
268 TCL_CHECK( tcl_ucp2_add4, (ctx->Transform.ClipPlanesEnabled & 0x4), 4 )
269 TCL_CHECK( tcl_ucp3_add4, (ctx->Transform.ClipPlanesEnabled & 0x8), 4 )
270 TCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 )
271 TCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 )
272 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 0 )
273 TCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 )
274
275 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
276 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
277 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
278
279 #define OUT_VEC(hdr, data) do { \
280 drm_radeon_cmd_header_t h; \
281 h.i = hdr; \
282 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
283 OUT_BATCH(0); \
284 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
285 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
286 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
287 OUT_BATCH_TABLE((data), h.vectors.count); \
288 } while(0)
289
290 #define OUT_SCL(hdr, data) do { \
291 drm_radeon_cmd_header_t h; \
292 h.i = hdr; \
293 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
294 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
295 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
296 OUT_BATCH_TABLE((data), h.scalars.count); \
297 } while(0)
298
299 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
300 {
301 r100ContextPtr r100 = R100_CONTEXT(ctx);
302 BATCH_LOCALS(&r100->radeon);
303 uint32_t dwords = atom->check(ctx, atom);
304
305 BEGIN_BATCH_NO_AUTOSTATE(dwords);
306 OUT_SCL(atom->cmd[0], atom->cmd+1);
307 END_BATCH();
308 }
309
310
311 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
312 {
313 r100ContextPtr r100 = R100_CONTEXT(ctx);
314 BATCH_LOCALS(&r100->radeon);
315 uint32_t dwords = atom->check(ctx, atom);
316
317 BEGIN_BATCH_NO_AUTOSTATE(dwords);
318 OUT_VEC(atom->cmd[0], atom->cmd+1);
319 END_BATCH();
320 }
321
322
323 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
324 {
325 r100ContextPtr r100 = R100_CONTEXT(ctx);
326 BATCH_LOCALS(&r100->radeon);
327 uint32_t dwords = atom->check(ctx, atom);
328
329 BEGIN_BATCH_NO_AUTOSTATE(dwords);
330 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
331 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
332 END_BATCH();
333 }
334
335 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
336 {
337 r100ContextPtr r100 = R100_CONTEXT(ctx);
338 BATCH_LOCALS(&r100->radeon);
339 struct radeon_renderbuffer *rrb;
340 uint32_t cbpitch;
341 uint32_t zbpitch, depth_fmt;
342 uint32_t dwords = atom->check(ctx, atom);
343
344 /* output the first 7 bytes of context */
345 BEGIN_BATCH_NO_AUTOSTATE(dwords);
346 OUT_BATCH_TABLE(atom->cmd, 5);
347
348 rrb = radeon_get_depthbuffer(&r100->radeon);
349 if (!rrb) {
350 OUT_BATCH(0);
351 OUT_BATCH(0);
352 } else {
353 zbpitch = (rrb->pitch / rrb->cpp);
354 if (r100->using_hyperz)
355 zbpitch |= RADEON_DEPTH_HYPERZ;
356
357 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
358 OUT_BATCH(zbpitch);
359 if (rrb->cpp == 4)
360 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
361 else
362 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
363 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
364 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
365 }
366
367 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
368 OUT_BATCH(atom->cmd[CTX_CMD_1]);
369 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
370
371 rrb = radeon_get_colorbuffer(&r100->radeon);
372 if (!rrb || !rrb->bo) {
373 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
374 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
375 } else {
376 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
377 if (rrb->cpp == 4)
378 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
379 else
380 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
381
382 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
383 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
384 }
385
386 OUT_BATCH(atom->cmd[CTX_CMD_2]);
387
388 if (!rrb || !rrb->bo) {
389 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
390 } else {
391 cbpitch = (rrb->pitch / rrb->cpp);
392 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
393 cbpitch |= RADEON_COLOR_TILE_ENABLE;
394 OUT_BATCH(cbpitch);
395 }
396
397 END_BATCH();
398 }
399
400 static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
401 {
402 r100ContextPtr r100 = R100_CONTEXT(ctx);
403 struct radeon_renderbuffer *rrb, *drb;
404 uint32_t dwords;
405
406 rrb = radeon_get_colorbuffer(&r100->radeon);
407 if (!rrb || !rrb->bo) {
408 return 0;
409 }
410
411 drb = radeon_get_depthbuffer(&r100->radeon);
412
413 dwords = 10;
414 if (drb)
415 dwords += 6;
416 if (rrb)
417 dwords += 8;
418
419 return dwords;
420 }
421
422 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
423 {
424 r100ContextPtr r100 = R100_CONTEXT(ctx);
425 BATCH_LOCALS(&r100->radeon);
426 struct radeon_renderbuffer *rrb, *drb;
427 uint32_t cbpitch = 0;
428 uint32_t zbpitch = 0;
429 uint32_t dwords = atom->check(ctx, atom);
430 uint32_t depth_fmt;
431
432 rrb = radeon_get_colorbuffer(&r100->radeon);
433 if (!rrb || !rrb->bo) {
434 fprintf(stderr, "no rrb\n");
435 return;
436 }
437
438 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
439 if (rrb->cpp == 4)
440 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
441 else switch (rrb->base._ActualFormat) {
442 case GL_RGB5:
443 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
444 break;
445 case GL_RGBA4:
446 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
447 break;
448 case GL_RGB5_A1:
449 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
450 break;
451 }
452
453 cbpitch = (rrb->pitch / rrb->cpp);
454 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
455 cbpitch |= R200_COLOR_TILE_ENABLE;
456
457 drb = radeon_get_depthbuffer(&r100->radeon);
458 if (drb) {
459 zbpitch = (drb->pitch / drb->cpp);
460 if (drb->cpp == 4)
461 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
462 else
463 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
464 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
465 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
466
467 }
468
469 BEGIN_BATCH_NO_AUTOSTATE(dwords);
470
471 /* In the CS case we need to split this up */
472 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
473 OUT_BATCH_TABLE((atom->cmd + 1), 4);
474
475 if (drb) {
476 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
477 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
478
479 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
480 OUT_BATCH(zbpitch);
481 }
482
483 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
484 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
485 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
486 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
487 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
488
489 if (rrb) {
490 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
491 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
492
493 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
494 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
495 }
496
497 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
498 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
499 // }
500
501 END_BATCH();
502 BEGIN_BATCH_NO_AUTOSTATE(4);
503 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
504 OUT_BATCH(0);
505 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
506 if (rrb) {
507 OUT_BATCH(((rrb->base.Width - 1) << RADEON_RE_WIDTH_SHIFT) |
508 ((rrb->base.Height - 1) << RADEON_RE_HEIGHT_SHIFT));
509 } else {
510 OUT_BATCH(0);
511 }
512 END_BATCH();
513 }
514
515 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
516 {
517 r100ContextPtr r100 = R100_CONTEXT(ctx);
518 BATCH_LOCALS(&r100->radeon);
519 uint32_t dwords = atom->check(ctx, atom);
520 int i = atom->idx, j;
521 radeonTexObj *t = r100->state.texture.unit[i].texobj;
522 radeon_mipmap_level *lvl;
523
524 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
525 return;
526
527 if (!t)
528 return;
529
530 if (!t->mt)
531 return;
532
533 BEGIN_BATCH_NO_AUTOSTATE(dwords);
534 OUT_BATCH_TABLE(atom->cmd, 3);
535 lvl = &t->mt->levels[0];
536 for (j = 0; j < 5; j++) {
537 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
538 RADEON_GEM_DOMAIN_VRAM, 0, 0);
539 }
540 END_BATCH();
541 }
542
543 static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
544 {
545 r100ContextPtr r100 = R100_CONTEXT(ctx);
546 BATCH_LOCALS(&r100->radeon);
547 uint32_t dwords = atom->check(ctx, atom);
548 int i = atom->idx, j;
549 radeonTexObj *t = r100->state.texture.unit[i].texobj;
550 radeon_mipmap_level *lvl;
551 uint32_t base_reg;
552
553 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
554 return;
555
556 if (!t)
557 return;
558
559 if (!t->mt)
560 return;
561
562 switch(i) {
563 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
564 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
565 default:
566 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
567 };
568 BEGIN_BATCH_NO_AUTOSTATE(dwords);
569 OUT_BATCH_TABLE(atom->cmd, 2);
570 lvl = &t->mt->levels[0];
571 for (j = 0; j < 5; j++) {
572 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
573 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
574 RADEON_GEM_DOMAIN_VRAM, 0, 0);
575 }
576 END_BATCH();
577 }
578
579 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
580 {
581 r100ContextPtr r100 = R100_CONTEXT(ctx);
582 BATCH_LOCALS(&r100->radeon);
583 uint32_t dwords = atom->cmd_size;
584 int i = atom->idx;
585 radeonTexObj *t = r100->state.texture.unit[i].texobj;
586 radeon_mipmap_level *lvl;
587
588 if (t && t->mt && !t->image_override)
589 dwords += 2;
590 BEGIN_BATCH_NO_AUTOSTATE(dwords);
591
592 OUT_BATCH_TABLE(atom->cmd, 3);
593 if (t && t->mt && !t->image_override) {
594 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
595 lvl = &t->mt->levels[0];
596 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
597 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
598 } else {
599 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
600 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
601 }
602 } else if (!t) {
603 /* workaround for old CS mechanism */
604 OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
605 // OUT_BATCH(r100->radeon.radeonScreen);
606 } else {
607 OUT_BATCH(t->override_offset);
608 }
609
610 OUT_BATCH_TABLE((atom->cmd+4), 5);
611 END_BATCH();
612 }
613
614 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
615 {
616 r100ContextPtr r100 = R100_CONTEXT(ctx);
617 BATCH_LOCALS(&r100->radeon);
618 uint32_t dwords = atom->cmd_size;
619 int i = atom->idx;
620 radeonTexObj *t = r100->state.texture.unit[i].texobj;
621 radeon_mipmap_level *lvl;
622 int hastexture = 1;
623
624 if (!t)
625 hastexture = 0;
626 else {
627 if (!t->mt && !t->bo)
628 hastexture = 0;
629 }
630 dwords += 1;
631 if (hastexture)
632 dwords += 2;
633 else
634 dwords -= 2;
635 BEGIN_BATCH_NO_AUTOSTATE(dwords);
636
637 OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1));
638 OUT_BATCH_TABLE((atom->cmd + 1), 2);
639
640 if (hastexture) {
641 OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
642 if (t->mt && !t->image_override) {
643 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
644 lvl = &t->mt->levels[0];
645 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
646 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
647 } else {
648 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
649 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
650 }
651 } else {
652 if (t->bo)
653 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
654 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
655 }
656 }
657
658 OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1));
659 OUT_BATCH_TABLE((atom->cmd+4), 2);
660 OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0));
661 OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR]));
662 END_BATCH();
663 }
664
665 /* Initialize the context's hardware state.
666 */
667 void radeonInitState( r100ContextPtr rmesa )
668 {
669 GLcontext *ctx = rmesa->radeon.glCtx;
670 GLuint i;
671
672 rmesa->radeon.state.color.clear = 0x00000000;
673
674 switch ( ctx->Visual.depthBits ) {
675 case 16:
676 rmesa->radeon.state.depth.clear = 0x0000ffff;
677 rmesa->radeon.state.stencil.clear = 0x00000000;
678 break;
679 case 24:
680 rmesa->radeon.state.depth.clear = 0x00ffffff;
681 rmesa->radeon.state.stencil.clear = 0xffff0000;
682 break;
683 default:
684 break;
685 }
686
687 rmesa->radeon.Fallback = 0;
688
689
690 rmesa->radeon.hw.max_state_size = 0;
691
692 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
693 do { \
694 rmesa->hw.ATOM.cmd_size = SZ; \
695 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
696 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
697 rmesa->hw.ATOM.name = NM; \
698 rmesa->hw.ATOM.is_tcl = FLAG; \
699 rmesa->hw.ATOM.check = check_##CHK; \
700 rmesa->hw.ATOM.dirty = GL_TRUE; \
701 rmesa->hw.ATOM.idx = IDX; \
702 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
703 } while (0)
704
705 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
706 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
707
708 /* Allocate state buffers:
709 */
710 ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
711 if (rmesa->radeon.radeonScreen->kernel_mm) {
712 rmesa->hw.ctx.emit = ctx_emit_cs;
713 rmesa->hw.ctx.check = check_always_ctx;
714 } else
715 rmesa->hw.ctx.emit = ctx_emit;
716 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
717 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
718 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
719 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
720 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
721 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
722 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
723 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
724 if (rmesa->radeon.radeonScreen->kernel_mm) {
725 ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 );
726 ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 );
727 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 );
728 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
729 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
730 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
731 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2);
732 ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 );
733 ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 );
734 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
735 ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 );
736 ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
737 ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 );
738 ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 );
739 ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 );
740 ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 );
741 ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 );
742 ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 );
743 ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 );
744 ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 );
745 ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 );
746 ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
747 ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
748 ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
749 ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
750 ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
751 ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
752 } else {
753 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
754 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
755 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
756 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
757 ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
758 ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
759 ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2);
760 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
761 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
762 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
763 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
764 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
765 ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
766 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
767 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
768 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
769 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
770 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
771 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
772 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
773 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
774 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
775 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
776 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
777 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
778 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
779 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
780 }
781
782 for (i = 0; i < 3; i++) {
783 if (rmesa->radeon.radeonScreen->kernel_mm)
784 rmesa->hw.tex[i].emit = tex_emit_cs;
785 else
786 rmesa->hw.tex[i].emit = tex_emit;
787 }
788 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
789 {
790 if (rmesa->radeon.radeonScreen->kernel_mm) {
791 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
792 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
793 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
794 for (i = 0; i < 3; i++)
795 rmesa->hw.cube[i].emit = cube_emit_cs;
796 } else {
797 ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
798 ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
799 ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
800 for (i = 0; i < 3; i++)
801 rmesa->hw.cube[i].emit = cube_emit;
802 }
803 }
804 else
805 {
806 ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
807 ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
808 ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
809 }
810 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
811 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
812 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );
813
814 radeonSetUpAtomList( rmesa );
815
816 /* Fill in the packet headers:
817 */
818 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
819 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
820 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
821 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
822 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
823 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
824 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
825 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
826 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
827 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
828 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
829 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
830 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
831 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
832 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
833 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
834 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
835 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
836 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
837 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
838 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
839 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
840 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
841 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
842 rmesa->hw.mtl.cmd[MTL_CMD_0] =
843 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
844 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
845 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
846 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
847 rmesa->hw.grd.cmd[GRD_CMD_0] =
848 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
849 rmesa->hw.fog.cmd[FOG_CMD_0] =
850 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
851 rmesa->hw.glt.cmd[GLT_CMD_0] =
852 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
853 rmesa->hw.eye.cmd[EYE_CMD_0] =
854 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
855
856 for (i = 0 ; i < 6; i++) {
857 rmesa->hw.mat[i].cmd[MAT_CMD_0] =
858 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
859 }
860
861 for (i = 0 ; i < 8; i++) {
862 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
863 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
864 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
865 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
866 }
867
868 for (i = 0 ; i < 6; i++) {
869 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
870 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
871 }
872
873 if (rmesa->radeon.radeonScreen->kernel_mm) {
874 rmesa->hw.grd.emit = scl_emit;
875 rmesa->hw.fog.emit = vec_emit;
876 rmesa->hw.glt.emit = vec_emit;
877 rmesa->hw.eye.emit = vec_emit;
878
879 for (i = 0; i <= 6; i++)
880 rmesa->hw.mat[i].emit = vec_emit;
881
882 for (i = 0; i < 8; i++)
883 rmesa->hw.lit[i].emit = lit_emit;
884
885 for (i = 0; i < 6; i++)
886 rmesa->hw.ucp[i].emit = vec_emit;
887 }
888
889 rmesa->last_ReallyEnabled = -1;
890
891 /* Initial Harware state:
892 */
893 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
894 RADEON_CHROMA_FUNC_FAIL |
895 RADEON_CHROMA_KEY_NEAREST |
896 RADEON_SHADOW_FUNC_EQUAL |
897 RADEON_SHADOW_PASS_1 /*|
898 RADEON_RIGHT_HAND_CUBE_OGL */);
899
900 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
901 /* this bit unused for vertex fog */
902 RADEON_FOG_USE_DEPTH);
903
904 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
905
906 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
907 RADEON_SRC_BLEND_GL_ONE |
908 RADEON_DST_BLEND_GL_ZERO );
909
910 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
911 RADEON_STENCIL_TEST_ALWAYS |
912 RADEON_STENCIL_FAIL_KEEP |
913 RADEON_STENCIL_ZPASS_KEEP |
914 RADEON_STENCIL_ZFAIL_KEEP |
915 RADEON_Z_WRITE_ENABLE);
916
917 if (rmesa->using_hyperz) {
918 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
919 RADEON_Z_DECOMPRESSION_ENABLE;
920 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
921 /* works for q3, but slight rendering errors with glxgears ? */
922 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
923 /* need this otherwise get lots of lockups with q3 ??? */
924 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
925 }
926 }
927
928 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
929 RADEON_ANTI_ALIAS_NONE);
930
931 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
932 RADEON_ZBLOCK16);
933
934 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
935 case DRI_CONF_DITHER_XERRORDIFFRESET:
936 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
937 break;
938 case DRI_CONF_DITHER_ORDERED:
939 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
940 break;
941 }
942 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
943 DRI_CONF_ROUND_ROUND )
944 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
945 else
946 rmesa->radeon.state.color.roundEnable = 0;
947 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
948 DRI_CONF_COLOR_REDUCTION_DITHER )
949 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
950 else
951 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
952
953
954 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
955 RADEON_BFACE_SOLID |
956 RADEON_FFACE_SOLID |
957 /* RADEON_BADVTX_CULL_DISABLE | */
958 RADEON_FLAT_SHADE_VTX_LAST |
959 RADEON_DIFFUSE_SHADE_GOURAUD |
960 RADEON_ALPHA_SHADE_GOURAUD |
961 RADEON_SPECULAR_SHADE_GOURAUD |
962 RADEON_FOG_SHADE_GOURAUD |
963 RADEON_VPORT_XY_XFORM_ENABLE |
964 RADEON_VPORT_Z_XFORM_ENABLE |
965 RADEON_VTX_PIX_CENTER_OGL |
966 RADEON_ROUND_MODE_TRUNC |
967 RADEON_ROUND_PREC_8TH_PIX);
968
969 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
970 #ifdef MESA_BIG_ENDIAN
971 RADEON_VC_32BIT_SWAP;
972 #else
973 RADEON_VC_NO_SWAP;
974 #endif
975
976 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
977 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
978 }
979
980 rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
981 RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
982 RADEON_TEX1_W_ROUTING_USE_Q1);
983
984
985 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
986
987 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
988 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
989 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
990
991 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
992
993 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
994 ((0x00 << RADEON_STENCIL_REF_SHIFT) |
995 (0xff << RADEON_STENCIL_MASK_SHIFT) |
996 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
997
998 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
999 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1000
1001 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1002 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
1003 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
1004 RADEON_STIPPLE_BIG_BIT_ORDER);
1005
1006 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1007 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1008 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1009 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1010 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1011 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1012
1013 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1014 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
1015 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1016 (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
1017 RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
1018 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
1019 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
1020 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
1021
1022 /* Initialize the texture offset to the start of the card texture heap */
1023 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
1024 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1025
1026 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1027 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
1028 (RADEON_COLOR_ARG_A_ZERO |
1029 RADEON_COLOR_ARG_B_ZERO |
1030 RADEON_COLOR_ARG_C_CURRENT_COLOR |
1031 RADEON_BLEND_CTL_ADD |
1032 RADEON_SCALE_1X |
1033 RADEON_CLAMP_TX);
1034 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
1035 (RADEON_ALPHA_ARG_A_ZERO |
1036 RADEON_ALPHA_ARG_B_ZERO |
1037 RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
1038 RADEON_BLEND_CTL_ADD |
1039 RADEON_SCALE_1X |
1040 RADEON_CLAMP_TX);
1041 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
1042
1043 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1044 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
1045 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1046 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
1047 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1048 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
1049 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1050 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
1051 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1052 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
1053 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1054 }
1055
1056 /* Can only add ST1 at the time of doing some multitex but can keep
1057 * it after that. Errors if DIFFUSE is missing.
1058 */
1059 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
1060 (RADEON_TCL_VTX_Z0 |
1061 RADEON_TCL_VTX_W0 |
1062 RADEON_TCL_VTX_PK_DIFFUSE
1063 ); /* need to keep this uptodate */
1064
1065 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
1066 ( RADEON_TCL_COMPUTE_XYZW |
1067 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
1068 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
1069 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
1070
1071
1072 /* XXX */
1073 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
1074 ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
1075 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
1076
1077 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
1078 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
1079 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
1080 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
1081 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
1082
1083 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1084 (RADEON_UCP_IN_CLIP_SPACE |
1085 RADEON_CULL_FRONT_IS_CCW);
1086
1087 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
1088
1089 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
1090 (RADEON_SPECULAR_LIGHTS |
1091 RADEON_DIFFUSE_SPECULAR_COMBINE |
1092 RADEON_LOCAL_LIGHT_VEC_GL |
1093 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
1094 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
1095 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
1096 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
1097
1098 for (i = 0 ; i < 8; i++) {
1099 struct gl_light *l = &ctx->Light.Light[i];
1100 GLenum p = GL_LIGHT0 + i;
1101 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1102
1103 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1104 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1105 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1106 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1107 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1108 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1109 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1110 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1111 &l->ConstantAttenuation );
1112 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1113 &l->LinearAttenuation );
1114 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1115 &l->QuadraticAttenuation );
1116 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1117 }
1118
1119 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1120 ctx->Light.Model.Ambient );
1121
1122 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1123
1124 for (i = 0 ; i < 6; i++) {
1125 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1126 }
1127
1128 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1129 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1130 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1131 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1132 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1133 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1134
1135 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1136 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1137 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1138 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1139
1140 rmesa->hw.eye.cmd[EYE_X] = 0;
1141 rmesa->hw.eye.cmd[EYE_Y] = 0;
1142 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1143 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1144
1145 rmesa->radeon.hw.all_dirty = GL_TRUE;
1146
1147 rcommonInitCmdBuf(&rmesa->radeon);
1148 }