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Merge branch 'master' of ssh://git.freedesktop.org/git/mesa/mesa
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c
1 /*
2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
28 */
29
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
33
34 #include "swrast/swrast.h"
35 #include "vbo/vbo.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
39
40 #include "radeon_context.h"
41 #include "radeon_mipmap_tree.h"
42 #include "radeon_ioctl.h"
43 #include "radeon_state.h"
44 #include "radeon_tcl.h"
45 #include "radeon_tex.h"
46 #include "radeon_swtcl.h"
47 #include "radeon_queryobj.h"
48
49 #include "../r200/r200_reg.h"
50
51 #include "xmlpool.h"
52
53 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
54 * 1.3 cmdbuffers allow all previous state to be updated as well as
55 * the tcl scalar and vector areas.
56 */
57 static struct {
58 int start;
59 int len;
60 const char *name;
61 } packet[RADEON_MAX_STATE_PACKETS] = {
62 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
63 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
64 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
65 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
66 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
67 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
68 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
69 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
70 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
71 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
72 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
73 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
74 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
75 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
76 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
77 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
78 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
79 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
80 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
81 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
82 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
83 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
84 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
85 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
86 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
87 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
88 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
89 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
90 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
91 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
92 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
93 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
94 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
95 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
96 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
97 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
98 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
99 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
100 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
101 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
102 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
103 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
104 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
105 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
106 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
107 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
108 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
109 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
110 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
111 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
112 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
113 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
114 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
115 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
116 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
117 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
118 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
119 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
120 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
121 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
122 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
123 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
124 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
125 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
126 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
127 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
128 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
129 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
130 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
131 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
132 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
133 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
134 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
135 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
136 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
137 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
138 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
139 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
140 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
141 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
142 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
143 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
144 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
145 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
146 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
147 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
148 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
149 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
150 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
151 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
152 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
153 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
154 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
155 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
156 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
157 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
158 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
159 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
160 };
161
162 /* =============================================================
163 * State initialization
164 */
165 static int cmdpkt( r100ContextPtr rmesa, int id )
166 {
167 drm_radeon_cmd_header_t h;
168
169 if (rmesa->radeon.radeonScreen->kernel_mm) {
170 return CP_PACKET0(packet[id].start, packet[id].len - 1);
171 } else {
172 h.i = 0;
173 h.packet.cmd_type = RADEON_CMD_PACKET;
174 h.packet.packet_id = id;
175 }
176 return h.i;
177 }
178
179 static int cmdvec( int offset, int stride, int count )
180 {
181 drm_radeon_cmd_header_t h;
182 h.i = 0;
183 h.vectors.cmd_type = RADEON_CMD_VECTORS;
184 h.vectors.offset = offset;
185 h.vectors.stride = stride;
186 h.vectors.count = count;
187 return h.i;
188 }
189
190 static int cmdscl( int offset, int stride, int count )
191 {
192 drm_radeon_cmd_header_t h;
193 h.i = 0;
194 h.scalars.cmd_type = RADEON_CMD_SCALARS;
195 h.scalars.offset = offset;
196 h.scalars.stride = stride;
197 h.scalars.count = count;
198 return h.i;
199 }
200
201 #define CHECK( NM, FLAG, ADD ) \
202 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
203 { \
204 return FLAG ? atom->cmd_size + (ADD) : 0; \
205 }
206
207 #define TCL_CHECK( NM, FLAG, ADD ) \
208 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
209 { \
210 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
211 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size + (ADD) : 0; \
212 }
213
214
215 CHECK( always, GL_TRUE, 0 )
216 CHECK( always_add2, GL_TRUE, 2 )
217 CHECK( always_add4, GL_TRUE, 4 )
218 CHECK( never, GL_FALSE, 0 )
219 CHECK( tex0_mm, ctx->Texture.Unit[0]._ReallyEnabled, 3 )
220 CHECK( tex1_mm, ctx->Texture.Unit[1]._ReallyEnabled, 3 )
221 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
222 CHECK( tex2_mm, ctx->Texture._EnabledUnits, 3 )
223 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled, 2 )
224 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled, 2 )
225 CHECK( tex2, ctx->Texture._EnabledUnits, 2 )
226 CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE )
227 CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE )
228 CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 3 + 3*5 - CUBE_STATE_SIZE )
229 CHECK( cube0_mm, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
230 CHECK( cube1_mm, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
231 CHECK( cube2_mm, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT), 2 + 4*5 - CUBE_STATE_SIZE )
232 CHECK( fog, ctx->Fog.Enabled, 0 )
233 CHECK( fog_add4, ctx->Fog.Enabled, 4 )
234 TCL_CHECK( tcl, GL_TRUE, 0 )
235 TCL_CHECK( tcl_add4, GL_TRUE, 4 )
236 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled, 0 )
237 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled, 0 )
238 TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled, 0 )
239 TCL_CHECK( tcl_tex0_add4, ctx->Texture.Unit[0]._ReallyEnabled, 4 )
240 TCL_CHECK( tcl_tex1_add4, ctx->Texture.Unit[1]._ReallyEnabled, 4 )
241 TCL_CHECK( tcl_tex2_add4, ctx->Texture.Unit[2]._ReallyEnabled, 4 )
242 TCL_CHECK( tcl_lighting, ctx->Light.Enabled, 0 )
243 TCL_CHECK( tcl_lighting_add4, ctx->Light.Enabled, 4 )
244 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled, 0 )
245 TCL_CHECK( tcl_eyespace_or_lighting_add4, ctx->_NeedEyeCoords || ctx->Light.Enabled, 4 )
246 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 0 )
247 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 0 )
248 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 0 )
249 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 0 )
250 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 0 )
251 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 0 )
252 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 0 )
253 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 0 )
254 TCL_CHECK( tcl_lit0_add6, ctx->Light.Enabled && ctx->Light.Light[0].Enabled, 6 )
255 TCL_CHECK( tcl_lit1_add6, ctx->Light.Enabled && ctx->Light.Light[1].Enabled, 6 )
256 TCL_CHECK( tcl_lit2_add6, ctx->Light.Enabled && ctx->Light.Light[2].Enabled, 6 )
257 TCL_CHECK( tcl_lit3_add6, ctx->Light.Enabled && ctx->Light.Light[3].Enabled, 6 )
258 TCL_CHECK( tcl_lit4_add6, ctx->Light.Enabled && ctx->Light.Light[4].Enabled, 6 )
259 TCL_CHECK( tcl_lit5_add6, ctx->Light.Enabled && ctx->Light.Light[5].Enabled, 6 )
260 TCL_CHECK( tcl_lit6_add6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled, 6 )
261 TCL_CHECK( tcl_lit7_add6, ctx->Light.Enabled && ctx->Light.Light[7].Enabled, 6 )
262 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1), 0 )
263 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2), 0 )
264 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4), 0 )
265 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8), 0 )
266 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10), 0 )
267 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20), 0 )
268 TCL_CHECK( tcl_ucp0_add4, (ctx->Transform.ClipPlanesEnabled & 0x1), 4 )
269 TCL_CHECK( tcl_ucp1_add4, (ctx->Transform.ClipPlanesEnabled & 0x2), 4 )
270 TCL_CHECK( tcl_ucp2_add4, (ctx->Transform.ClipPlanesEnabled & 0x4), 4 )
271 TCL_CHECK( tcl_ucp3_add4, (ctx->Transform.ClipPlanesEnabled & 0x8), 4 )
272 TCL_CHECK( tcl_ucp4_add4, (ctx->Transform.ClipPlanesEnabled & 0x10), 4 )
273 TCL_CHECK( tcl_ucp5_add4, (ctx->Transform.ClipPlanesEnabled & 0x20), 4 )
274 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 0 )
275 TCL_CHECK( tcl_eyespace_or_fog_add4, ctx->_NeedEyeCoords || ctx->Fog.Enabled, 4 )
276
277 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
278 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
279 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT), 0 )
280
281 #define OUT_VEC(hdr, data) do { \
282 drm_radeon_cmd_header_t h; \
283 h.i = hdr; \
284 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
285 OUT_BATCH(0); \
286 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
287 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
288 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
289 OUT_BATCH_TABLE((data), h.vectors.count); \
290 } while(0)
291
292 #define OUT_SCL(hdr, data) do { \
293 drm_radeon_cmd_header_t h; \
294 h.i = hdr; \
295 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
296 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
297 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
298 OUT_BATCH_TABLE((data), h.scalars.count); \
299 } while(0)
300
301 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
302 {
303 r100ContextPtr r100 = R100_CONTEXT(ctx);
304 BATCH_LOCALS(&r100->radeon);
305 uint32_t dwords = atom->check(ctx, atom);
306
307 BEGIN_BATCH_NO_AUTOSTATE(dwords);
308 OUT_SCL(atom->cmd[0], atom->cmd+1);
309 END_BATCH();
310 }
311
312
313 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
314 {
315 r100ContextPtr r100 = R100_CONTEXT(ctx);
316 BATCH_LOCALS(&r100->radeon);
317 uint32_t dwords = atom->check(ctx, atom);
318
319 BEGIN_BATCH_NO_AUTOSTATE(dwords);
320 OUT_VEC(atom->cmd[0], atom->cmd+1);
321 END_BATCH();
322 }
323
324
325 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
326 {
327 r100ContextPtr r100 = R100_CONTEXT(ctx);
328 BATCH_LOCALS(&r100->radeon);
329 uint32_t dwords = atom->check(ctx, atom);
330
331 BEGIN_BATCH_NO_AUTOSTATE(dwords);
332 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
333 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
334 END_BATCH();
335 }
336
337 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
338 {
339 r100ContextPtr r100 = R100_CONTEXT(ctx);
340 BATCH_LOCALS(&r100->radeon);
341 struct radeon_renderbuffer *rrb;
342 uint32_t cbpitch;
343 uint32_t zbpitch, depth_fmt;
344 uint32_t dwords = atom->check(ctx, atom);
345
346 /* output the first 7 bytes of context */
347 BEGIN_BATCH_NO_AUTOSTATE(dwords);
348 OUT_BATCH_TABLE(atom->cmd, 5);
349
350 rrb = radeon_get_depthbuffer(&r100->radeon);
351 if (!rrb) {
352 OUT_BATCH(0);
353 OUT_BATCH(0);
354 } else {
355 zbpitch = (rrb->pitch / rrb->cpp);
356 if (r100->using_hyperz)
357 zbpitch |= RADEON_DEPTH_HYPERZ;
358
359 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
360 OUT_BATCH(zbpitch);
361 if (rrb->cpp == 4)
362 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
363 else
364 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
365 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
366 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
367 }
368
369 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
370 OUT_BATCH(atom->cmd[CTX_CMD_1]);
371 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
372
373 rrb = radeon_get_colorbuffer(&r100->radeon);
374 if (!rrb || !rrb->bo) {
375 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
376 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
377 } else {
378 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
379 if (rrb->cpp == 4)
380 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
381 else
382 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
383
384 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
385 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
386 }
387
388 OUT_BATCH(atom->cmd[CTX_CMD_2]);
389
390 if (!rrb || !rrb->bo) {
391 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
392 } else {
393 cbpitch = (rrb->pitch / rrb->cpp);
394 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
395 cbpitch |= RADEON_COLOR_TILE_ENABLE;
396 OUT_BATCH(cbpitch);
397 }
398
399 END_BATCH();
400 }
401
402 static int check_always_ctx( GLcontext *ctx, struct radeon_state_atom *atom)
403 {
404 r100ContextPtr r100 = R100_CONTEXT(ctx);
405 struct radeon_renderbuffer *rrb, *drb;
406 uint32_t dwords;
407
408 rrb = radeon_get_colorbuffer(&r100->radeon);
409 if (!rrb || !rrb->bo) {
410 return 0;
411 }
412
413 drb = radeon_get_depthbuffer(&r100->radeon);
414
415 dwords = 10;
416 if (drb)
417 dwords += 6;
418 if (rrb)
419 dwords += 8;
420
421 return dwords;
422 }
423
424 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
425 {
426 r100ContextPtr r100 = R100_CONTEXT(ctx);
427 BATCH_LOCALS(&r100->radeon);
428 struct radeon_renderbuffer *rrb, *drb;
429 uint32_t cbpitch = 0;
430 uint32_t zbpitch = 0;
431 uint32_t dwords = atom->check(ctx, atom);
432 uint32_t depth_fmt;
433
434 rrb = radeon_get_colorbuffer(&r100->radeon);
435 if (!rrb || !rrb->bo) {
436 fprintf(stderr, "no rrb\n");
437 return;
438 }
439
440 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
441 if (rrb->cpp == 4)
442 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
443 else switch (rrb->base._ActualFormat) {
444 case GL_RGB5:
445 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
446 break;
447 case GL_RGBA4:
448 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB4444;
449 break;
450 case GL_RGB5_A1:
451 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB1555;
452 break;
453 }
454
455 cbpitch = (rrb->pitch / rrb->cpp);
456 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
457 cbpitch |= R200_COLOR_TILE_ENABLE;
458
459 drb = radeon_get_depthbuffer(&r100->radeon);
460 if (drb) {
461 zbpitch = (drb->pitch / drb->cpp);
462 if (drb->cpp == 4)
463 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
464 else
465 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
466 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
467 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
468
469 }
470
471 BEGIN_BATCH_NO_AUTOSTATE(dwords);
472
473 /* In the CS case we need to split this up */
474 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
475 OUT_BATCH_TABLE((atom->cmd + 1), 4);
476
477 if (drb) {
478 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
479 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
480
481 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
482 OUT_BATCH(zbpitch);
483 }
484
485 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
486 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
487 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
488 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
489 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
490
491 if (rrb) {
492 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
493 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
494
495 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
496 OUT_BATCH_RELOC(cbpitch, rrb->bo, cbpitch, 0, RADEON_GEM_DOMAIN_VRAM, 0);
497 }
498
499 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
500 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
501 // }
502
503 END_BATCH();
504 BEGIN_BATCH_NO_AUTOSTATE(4);
505 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
506 OUT_BATCH(0);
507 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
508 if (rrb) {
509 OUT_BATCH(((rrb->base.Width - 1) << RADEON_RE_WIDTH_SHIFT) |
510 ((rrb->base.Height - 1) << RADEON_RE_HEIGHT_SHIFT));
511 } else {
512 OUT_BATCH(0);
513 }
514 END_BATCH();
515 }
516
517 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
518 {
519 r100ContextPtr r100 = R100_CONTEXT(ctx);
520 BATCH_LOCALS(&r100->radeon);
521 uint32_t dwords = atom->check(ctx, atom);
522 int i = atom->idx, j;
523 radeonTexObj *t = r100->state.texture.unit[i].texobj;
524 radeon_mipmap_level *lvl;
525
526 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
527 return;
528
529 if (!t)
530 return;
531
532 if (!t->mt)
533 return;
534
535 BEGIN_BATCH_NO_AUTOSTATE(dwords);
536 OUT_BATCH_TABLE(atom->cmd, 3);
537 lvl = &t->mt->levels[0];
538 for (j = 0; j < 5; j++) {
539 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
540 RADEON_GEM_DOMAIN_VRAM, 0, 0);
541 }
542 END_BATCH();
543 }
544
545 static void cube_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
546 {
547 r100ContextPtr r100 = R100_CONTEXT(ctx);
548 BATCH_LOCALS(&r100->radeon);
549 uint32_t dwords = atom->check(ctx, atom);
550 int i = atom->idx, j;
551 radeonTexObj *t = r100->state.texture.unit[i].texobj;
552 radeon_mipmap_level *lvl;
553 uint32_t base_reg;
554
555 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
556 return;
557
558 if (!t)
559 return;
560
561 if (!t->mt)
562 return;
563
564 switch(i) {
565 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
566 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
567 default:
568 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
569 };
570 BEGIN_BATCH_NO_AUTOSTATE(dwords);
571 OUT_BATCH_TABLE(atom->cmd, 2);
572 lvl = &t->mt->levels[0];
573 for (j = 0; j < 5; j++) {
574 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
575 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
576 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
577 }
578 END_BATCH();
579 }
580
581 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
582 {
583 r100ContextPtr r100 = R100_CONTEXT(ctx);
584 BATCH_LOCALS(&r100->radeon);
585 uint32_t dwords = atom->cmd_size;
586 int i = atom->idx;
587 radeonTexObj *t = r100->state.texture.unit[i].texobj;
588 radeon_mipmap_level *lvl;
589
590 if (t && t->mt && !t->image_override)
591 dwords += 2;
592 BEGIN_BATCH_NO_AUTOSTATE(dwords);
593
594 OUT_BATCH_TABLE(atom->cmd, 3);
595 if (t && t->mt && !t->image_override) {
596 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
597 lvl = &t->mt->levels[0];
598 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
599 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
600 } else {
601 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
602 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
603 }
604 } else if (!t) {
605 /* workaround for old CS mechanism */
606 OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
607 // OUT_BATCH(r100->radeon.radeonScreen);
608 } else {
609 OUT_BATCH(t->override_offset);
610 }
611
612 OUT_BATCH_TABLE((atom->cmd+4), 5);
613 END_BATCH();
614 }
615
616 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
617 {
618 r100ContextPtr r100 = R100_CONTEXT(ctx);
619 BATCH_LOCALS(&r100->radeon);
620 uint32_t dwords = atom->cmd_size;
621 int i = atom->idx;
622 radeonTexObj *t = r100->state.texture.unit[i].texobj;
623 radeon_mipmap_level *lvl;
624 int hastexture = 1;
625
626 if (!t)
627 hastexture = 0;
628 else {
629 if (!t->mt && !t->bo)
630 hastexture = 0;
631 }
632 dwords += 1;
633 if (hastexture)
634 dwords += 2;
635 else
636 dwords -= 2;
637 BEGIN_BATCH_NO_AUTOSTATE(dwords);
638
639 OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1));
640 OUT_BATCH_TABLE((atom->cmd + 1), 2);
641
642 if (hastexture) {
643 OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
644 if (t->mt && !t->image_override) {
645 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
646 lvl = &t->mt->levels[0];
647 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
648 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
649 } else {
650 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
651 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
652 }
653 } else {
654 if (t->bo)
655 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
656 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
657 }
658 }
659
660 OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1));
661 OUT_BATCH_TABLE((atom->cmd+4), 2);
662 OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0));
663 OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR]));
664 END_BATCH();
665 }
666
667 /* Initialize the context's hardware state.
668 */
669 void radeonInitState( r100ContextPtr rmesa )
670 {
671 GLcontext *ctx = rmesa->radeon.glCtx;
672 GLuint i;
673
674 rmesa->radeon.state.color.clear = 0x00000000;
675
676 switch ( ctx->Visual.depthBits ) {
677 case 16:
678 rmesa->radeon.state.depth.clear = 0x0000ffff;
679 rmesa->radeon.state.stencil.clear = 0x00000000;
680 break;
681 case 24:
682 rmesa->radeon.state.depth.clear = 0x00ffffff;
683 rmesa->radeon.state.stencil.clear = 0xffff0000;
684 break;
685 default:
686 break;
687 }
688
689 rmesa->radeon.Fallback = 0;
690
691
692 rmesa->radeon.hw.max_state_size = 0;
693
694 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
695 do { \
696 rmesa->hw.ATOM.cmd_size = SZ; \
697 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
698 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
699 rmesa->hw.ATOM.name = NM; \
700 rmesa->hw.ATOM.is_tcl = FLAG; \
701 rmesa->hw.ATOM.check = check_##CHK; \
702 rmesa->hw.ATOM.dirty = GL_TRUE; \
703 rmesa->hw.ATOM.idx = IDX; \
704 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
705 } while (0)
706
707 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
708 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
709
710 /* Allocate state buffers:
711 */
712 ALLOC_STATE( ctx, always_add4, CTX_STATE_SIZE, "CTX/context", 0 );
713 if (rmesa->radeon.radeonScreen->kernel_mm) {
714 rmesa->hw.ctx.emit = ctx_emit_cs;
715 rmesa->hw.ctx.check = check_always_ctx;
716 } else
717 rmesa->hw.ctx.emit = ctx_emit;
718 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
719 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
720 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
721 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
722 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
723 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
724 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
725 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
726 if (rmesa->radeon.radeonScreen->kernel_mm) {
727 ALLOC_STATE( grd, always_add2, GRD_STATE_SIZE, "GRD/guard-band", 1 );
728 ALLOC_STATE( fog, fog_add4, FOG_STATE_SIZE, "FOG/fog", 1 );
729 ALLOC_STATE( glt, tcl_lighting_add4, GLT_STATE_SIZE, "GLT/light-global", 1 );
730 ALLOC_STATE( eye, tcl_lighting_add4, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
731 ALLOC_STATE_IDX( tex[0], tex0_mm, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
732 ALLOC_STATE_IDX( tex[1], tex1_mm, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
733 ALLOC_STATE_IDX( tex[2], tex2_mm, TEX_STATE_SIZE, "TEX/tex-2", 0, 2);
734 ALLOC_STATE( mat[0], tcl_add4, MAT_STATE_SIZE, "MAT/modelproject", 1 );
735 ALLOC_STATE( mat[1], tcl_eyespace_or_fog_add4, MAT_STATE_SIZE, "MAT/modelview", 1 );
736 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting_add4, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
737 ALLOC_STATE( mat[3], tcl_tex0_add4, MAT_STATE_SIZE, "MAT/texmat0", 1 );
738 ALLOC_STATE( mat[4], tcl_tex1_add4, MAT_STATE_SIZE, "MAT/texmat1", 1 );
739 ALLOC_STATE( mat[5], tcl_tex2_add4, MAT_STATE_SIZE, "MAT/texmat2", 1 );
740 ALLOC_STATE( lit[0], tcl_lit0_add6, LIT_STATE_SIZE, "LIT/light-0", 1 );
741 ALLOC_STATE( lit[1], tcl_lit1_add6, LIT_STATE_SIZE, "LIT/light-1", 1 );
742 ALLOC_STATE( lit[2], tcl_lit2_add6, LIT_STATE_SIZE, "LIT/light-2", 1 );
743 ALLOC_STATE( lit[3], tcl_lit3_add6, LIT_STATE_SIZE, "LIT/light-3", 1 );
744 ALLOC_STATE( lit[4], tcl_lit4_add6, LIT_STATE_SIZE, "LIT/light-4", 1 );
745 ALLOC_STATE( lit[5], tcl_lit5_add6, LIT_STATE_SIZE, "LIT/light-5", 1 );
746 ALLOC_STATE( lit[6], tcl_lit6_add6, LIT_STATE_SIZE, "LIT/light-6", 1 );
747 ALLOC_STATE( lit[7], tcl_lit7_add6, LIT_STATE_SIZE, "LIT/light-7", 1 );
748 ALLOC_STATE( ucp[0], tcl_ucp0_add4, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
749 ALLOC_STATE( ucp[1], tcl_ucp1_add4, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
750 ALLOC_STATE( ucp[2], tcl_ucp2_add4, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
751 ALLOC_STATE( ucp[3], tcl_ucp3_add4, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
752 ALLOC_STATE( ucp[4], tcl_ucp4_add4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
753 ALLOC_STATE( ucp[5], tcl_ucp5_add4, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
754 } else {
755 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
756 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
757 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
758 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
759 ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
760 ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
761 ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2);
762 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
763 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
764 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
765 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
766 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
767 ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
768 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
769 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
770 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
771 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
772 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
773 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
774 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
775 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
776 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
777 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
778 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
779 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
780 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
781 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
782 }
783
784 if (rmesa->radeon.radeonScreen->kernel_mm) {
785 ALLOC_STATE( stp, always, STP_STATE_SIZE, "STP/stp", 0 );
786 }
787
788 for (i = 0; i < 3; i++) {
789 if (rmesa->radeon.radeonScreen->kernel_mm)
790 rmesa->hw.tex[i].emit = tex_emit_cs;
791 else
792 rmesa->hw.tex[i].emit = tex_emit;
793 }
794 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
795 {
796 if (rmesa->radeon.radeonScreen->kernel_mm) {
797 ALLOC_STATE_IDX( cube[0], cube0_mm, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
798 ALLOC_STATE_IDX( cube[1], cube1_mm, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
799 ALLOC_STATE_IDX( cube[2], cube2_mm, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
800 for (i = 0; i < 3; i++)
801 rmesa->hw.cube[i].emit = cube_emit_cs;
802 } else {
803 ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
804 ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
805 ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
806 for (i = 0; i < 3; i++)
807 rmesa->hw.cube[i].emit = cube_emit;
808 }
809 }
810 else
811 {
812 ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
813 ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
814 ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
815 }
816 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
817 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
818 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );
819
820 radeonSetUpAtomList( rmesa );
821
822 /* Fill in the packet headers:
823 */
824 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
825 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
826 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
827 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
828 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
829 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
830 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
831 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
832 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
833 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
834 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
835 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
836 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
837 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
838 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
839 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
840 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
841 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
842 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
843 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
844 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
845 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
846 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
847 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
848 rmesa->hw.mtl.cmd[MTL_CMD_0] =
849 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
850 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
851 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
852 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
853 rmesa->hw.grd.cmd[GRD_CMD_0] =
854 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
855 rmesa->hw.fog.cmd[FOG_CMD_0] =
856 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
857 rmesa->hw.glt.cmd[GLT_CMD_0] =
858 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
859 rmesa->hw.eye.cmd[EYE_CMD_0] =
860 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
861
862 for (i = 0 ; i < 6; i++) {
863 rmesa->hw.mat[i].cmd[MAT_CMD_0] =
864 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
865 }
866
867 for (i = 0 ; i < 8; i++) {
868 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
869 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
870 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
871 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
872 }
873
874 for (i = 0 ; i < 6; i++) {
875 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
876 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
877 }
878
879 if (rmesa->radeon.radeonScreen->kernel_mm) {
880 rmesa->hw.stp.cmd[STP_CMD_0] = CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0);
881 rmesa->hw.stp.cmd[STP_DATA_0] = 0;
882 rmesa->hw.stp.cmd[STP_CMD_1] = CP_PACKET0_ONE(RADEON_RE_STIPPLE_DATA, 31);
883
884 rmesa->hw.grd.emit = scl_emit;
885 rmesa->hw.fog.emit = vec_emit;
886 rmesa->hw.glt.emit = vec_emit;
887 rmesa->hw.eye.emit = vec_emit;
888
889 for (i = 0; i < 6; i++)
890 rmesa->hw.mat[i].emit = vec_emit;
891
892 for (i = 0; i < 8; i++)
893 rmesa->hw.lit[i].emit = lit_emit;
894
895 for (i = 0; i < 6; i++)
896 rmesa->hw.ucp[i].emit = vec_emit;
897 }
898
899 rmesa->last_ReallyEnabled = -1;
900
901 /* Initial Harware state:
902 */
903 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
904 RADEON_CHROMA_FUNC_FAIL |
905 RADEON_CHROMA_KEY_NEAREST |
906 RADEON_SHADOW_FUNC_EQUAL |
907 RADEON_SHADOW_PASS_1 /*|
908 RADEON_RIGHT_HAND_CUBE_OGL */);
909
910 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
911 /* this bit unused for vertex fog */
912 RADEON_FOG_USE_DEPTH);
913
914 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
915
916 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
917 RADEON_SRC_BLEND_GL_ONE |
918 RADEON_DST_BLEND_GL_ZERO );
919
920 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
921 RADEON_STENCIL_TEST_ALWAYS |
922 RADEON_STENCIL_FAIL_KEEP |
923 RADEON_STENCIL_ZPASS_KEEP |
924 RADEON_STENCIL_ZFAIL_KEEP |
925 RADEON_Z_WRITE_ENABLE);
926
927 if (rmesa->using_hyperz) {
928 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
929 RADEON_Z_DECOMPRESSION_ENABLE;
930 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
931 /* works for q3, but slight rendering errors with glxgears ? */
932 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
933 /* need this otherwise get lots of lockups with q3 ??? */
934 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
935 }
936 }
937
938 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
939 RADEON_ANTI_ALIAS_NONE);
940
941 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
942 RADEON_ZBLOCK16);
943
944 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
945 case DRI_CONF_DITHER_XERRORDIFFRESET:
946 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
947 break;
948 case DRI_CONF_DITHER_ORDERED:
949 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
950 break;
951 }
952 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
953 DRI_CONF_ROUND_ROUND )
954 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
955 else
956 rmesa->radeon.state.color.roundEnable = 0;
957 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
958 DRI_CONF_COLOR_REDUCTION_DITHER )
959 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
960 else
961 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
962
963
964 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
965 RADEON_BFACE_SOLID |
966 RADEON_FFACE_SOLID |
967 /* RADEON_BADVTX_CULL_DISABLE | */
968 RADEON_FLAT_SHADE_VTX_LAST |
969 RADEON_DIFFUSE_SHADE_GOURAUD |
970 RADEON_ALPHA_SHADE_GOURAUD |
971 RADEON_SPECULAR_SHADE_GOURAUD |
972 RADEON_FOG_SHADE_GOURAUD |
973 RADEON_VPORT_XY_XFORM_ENABLE |
974 RADEON_VPORT_Z_XFORM_ENABLE |
975 RADEON_VTX_PIX_CENTER_OGL |
976 RADEON_ROUND_MODE_TRUNC |
977 RADEON_ROUND_PREC_8TH_PIX);
978
979 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
980 #ifdef MESA_BIG_ENDIAN
981 RADEON_VC_32BIT_SWAP;
982 #else
983 RADEON_VC_NO_SWAP;
984 #endif
985
986 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
987 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
988 }
989
990 rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
991 RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
992 RADEON_TEX1_W_ROUTING_USE_Q1);
993
994
995 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
996
997 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
998 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
999 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
1000
1001 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
1002
1003 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
1004 ((0x00 << RADEON_STENCIL_REF_SHIFT) |
1005 (0xff << RADEON_STENCIL_MASK_SHIFT) |
1006 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
1007
1008 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
1009 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
1010
1011 rmesa->hw.msc.cmd[MSC_RE_MISC] =
1012 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
1013 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
1014 RADEON_STIPPLE_BIG_BIT_ORDER);
1015
1016 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
1017 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
1018 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
1019 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
1020 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
1021 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
1022
1023 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
1024 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
1025 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
1026 (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
1027 RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
1028 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
1029 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
1030 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
1031
1032 /* Initialize the texture offset to the start of the card texture heap */
1033 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
1034 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1035
1036 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
1037 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
1038 (RADEON_COLOR_ARG_A_ZERO |
1039 RADEON_COLOR_ARG_B_ZERO |
1040 RADEON_COLOR_ARG_C_CURRENT_COLOR |
1041 RADEON_BLEND_CTL_ADD |
1042 RADEON_SCALE_1X |
1043 RADEON_CLAMP_TX);
1044 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
1045 (RADEON_ALPHA_ARG_A_ZERO |
1046 RADEON_ALPHA_ARG_B_ZERO |
1047 RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
1048 RADEON_BLEND_CTL_ADD |
1049 RADEON_SCALE_1X |
1050 RADEON_CLAMP_TX);
1051 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
1052
1053 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
1054 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
1055 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1056 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
1057 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1058 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
1059 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1060 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
1061 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1062 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
1063 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
1064 }
1065
1066 /* Can only add ST1 at the time of doing some multitex but can keep
1067 * it after that. Errors if DIFFUSE is missing.
1068 */
1069 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
1070 (RADEON_TCL_VTX_Z0 |
1071 RADEON_TCL_VTX_W0 |
1072 RADEON_TCL_VTX_PK_DIFFUSE
1073 ); /* need to keep this uptodate */
1074
1075 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
1076 ( RADEON_TCL_COMPUTE_XYZW |
1077 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
1078 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
1079 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
1080
1081
1082 /* XXX */
1083 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
1084 ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
1085 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
1086
1087 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
1088 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
1089 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
1090 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
1091 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
1092
1093 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
1094 (RADEON_UCP_IN_CLIP_SPACE |
1095 RADEON_CULL_FRONT_IS_CCW);
1096
1097 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
1098
1099 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
1100 (RADEON_SPECULAR_LIGHTS |
1101 RADEON_DIFFUSE_SPECULAR_COMBINE |
1102 RADEON_LOCAL_LIGHT_VEC_GL |
1103 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
1104 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
1105 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
1106 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
1107
1108 for (i = 0 ; i < 8; i++) {
1109 struct gl_light *l = &ctx->Light.Light[i];
1110 GLenum p = GL_LIGHT0 + i;
1111 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
1112
1113 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
1114 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
1115 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
1116 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
1117 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
1118 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
1119 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
1120 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
1121 &l->ConstantAttenuation );
1122 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
1123 &l->LinearAttenuation );
1124 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
1125 &l->QuadraticAttenuation );
1126 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
1127 }
1128
1129 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1130 ctx->Light.Model.Ambient );
1131
1132 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1133
1134 for (i = 0 ; i < 6; i++) {
1135 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1136 }
1137
1138 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1139 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1140 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1141 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1142 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1143 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1144
1145 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1146 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1147 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1148 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1149
1150 rmesa->hw.eye.cmd[EYE_X] = 0;
1151 rmesa->hw.eye.cmd[EYE_Y] = 0;
1152 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1153 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1154
1155 if (rmesa->radeon.radeonScreen->kernel_mm) {
1156 radeon_init_query_stateobj(&rmesa->radeon, R100_QUERYOBJ_CMDSIZE);
1157 rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_CMD_0] = CP_PACKET0(RADEON_RB3D_ZPASS_DATA, 0);
1158 rmesa->radeon.query.queryobj.cmd[R100_QUERYOBJ_DATA_0] = 0;
1159 }
1160
1161 rmesa->radeon.hw.all_dirty = GL_TRUE;
1162
1163 rcommonInitCmdBuf(&rmesa->radeon);
1164 }