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Merge remote branch 'main/radeon-rewrite'
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c
1 /*
2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
28 */
29
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
33
34 #include "swrast/swrast.h"
35 #include "vbo/vbo.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
39
40 #include "radeon_context.h"
41 #include "radeon_mipmap_tree.h"
42 #include "radeon_ioctl.h"
43 #include "radeon_state.h"
44 #include "radeon_tcl.h"
45 #include "radeon_tex.h"
46 #include "radeon_swtcl.h"
47
48 #include "../r200/r200_reg.h"
49
50 #include "xmlpool.h"
51
52 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
53 * 1.3 cmdbuffers allow all previous state to be updated as well as
54 * the tcl scalar and vector areas.
55 */
56 static struct {
57 int start;
58 int len;
59 const char *name;
60 } packet[RADEON_MAX_STATE_PACKETS] = {
61 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
62 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
63 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
64 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
65 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
66 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
67 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
68 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
69 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
70 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
71 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
72 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
73 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
74 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
75 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
76 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
77 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
78 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
79 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
80 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
81 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
82 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
83 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
84 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
85 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
86 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
87 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
88 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
89 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
90 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
91 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
92 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
93 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
94 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
95 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
96 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
97 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
98 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
99 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
100 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
101 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
102 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
103 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
104 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
105 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
106 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
107 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
108 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
109 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
110 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
111 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
112 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
113 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
114 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
115 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
116 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
117 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
118 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
119 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
120 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
121 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
122 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
123 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
124 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
125 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
126 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
127 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
128 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
129 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
130 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
131 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
132 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
133 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
134 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
135 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
136 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
137 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
138 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
139 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
140 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
141 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
142 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
143 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
144 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
145 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
146 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
147 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
148 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
149 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
150 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
151 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
152 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
153 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
154 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
155 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
156 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
157 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
158 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
159 };
160
161 /* =============================================================
162 * State initialization
163 */
164 static int cmdpkt( r100ContextPtr rmesa, int id )
165 {
166 drm_radeon_cmd_header_t h;
167
168 if (rmesa->radeon.radeonScreen->kernel_mm) {
169 return CP_PACKET0(packet[id].start, packet[id].len - 1);
170 } else {
171 h.i = 0;
172 h.packet.cmd_type = RADEON_CMD_PACKET;
173 h.packet.packet_id = id;
174 }
175 return h.i;
176 }
177
178 static int cmdvec( int offset, int stride, int count )
179 {
180 drm_radeon_cmd_header_t h;
181 h.i = 0;
182 h.vectors.cmd_type = RADEON_CMD_VECTORS;
183 h.vectors.offset = offset;
184 h.vectors.stride = stride;
185 h.vectors.count = count;
186 return h.i;
187 }
188
189 static int cmdscl( int offset, int stride, int count )
190 {
191 drm_radeon_cmd_header_t h;
192 h.i = 0;
193 h.scalars.cmd_type = RADEON_CMD_SCALARS;
194 h.scalars.offset = offset;
195 h.scalars.stride = stride;
196 h.scalars.count = count;
197 return h.i;
198 }
199
200 #define CHECK( NM, FLAG ) \
201 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
202 { \
203 return FLAG ? atom->cmd_size : 0; \
204 }
205
206 #define TCL_CHECK( NM, FLAG ) \
207 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
208 { \
209 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
210 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
211 }
212
213
214 CHECK( always, GL_TRUE )
215 CHECK( never, GL_FALSE )
216 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
217 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
218 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
219 CHECK( tex2, ctx->Texture._EnabledUnits )
220 CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT))
221 CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT))
222 CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT))
223 CHECK( fog, ctx->Fog.Enabled )
224 TCL_CHECK( tcl, GL_TRUE )
225 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
226 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
227 TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled )
228 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
229 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
230 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
231 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
232 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
233 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
234 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
235 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
236 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
237 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
238 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
239 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
240 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
241 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
242 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
243 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
244 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
245
246 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
247 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
248 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT))
249
250 #define OUT_VEC(hdr, data) do { \
251 drm_radeon_cmd_header_t h; \
252 h.i = hdr; \
253 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
254 OUT_BATCH(0); \
255 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
256 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
257 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
258 OUT_BATCH_TABLE((data), h.vectors.count); \
259 } while(0)
260
261 #define OUT_SCL(hdr, data) do { \
262 drm_radeon_cmd_header_t h; \
263 h.i = hdr; \
264 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
265 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
266 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
267 OUT_BATCH_TABLE((data), h.scalars.count); \
268 } while(0)
269
270 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
271 {
272 r100ContextPtr r100 = R100_CONTEXT(ctx);
273 BATCH_LOCALS(&r100->radeon);
274 uint32_t dwords = atom->cmd_size;
275
276 dwords += 2;
277 BEGIN_BATCH_NO_AUTOSTATE(dwords);
278 OUT_SCL(atom->cmd[0], atom->cmd+1);
279 END_BATCH();
280 }
281
282
283 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
284 {
285 r100ContextPtr r100 = R100_CONTEXT(ctx);
286 BATCH_LOCALS(&r100->radeon);
287 uint32_t dwords = atom->cmd_size;
288
289 dwords += 4;
290 BEGIN_BATCH_NO_AUTOSTATE(dwords);
291 OUT_VEC(atom->cmd[0], atom->cmd+1);
292 END_BATCH();
293 }
294
295
296 static void lit_emit(GLcontext *ctx, struct radeon_state_atom *atom)
297 {
298 r100ContextPtr r100 = R100_CONTEXT(ctx);
299 BATCH_LOCALS(&r100->radeon);
300 uint32_t dwords = atom->cmd_size;
301
302 dwords += 6;
303 BEGIN_BATCH_NO_AUTOSTATE(dwords);
304 OUT_VEC(atom->cmd[LIT_CMD_0], atom->cmd+1);
305 OUT_SCL(atom->cmd[LIT_CMD_1], atom->cmd+LIT_CMD_1+1);
306 END_BATCH();
307 }
308
309 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
310 {
311 r100ContextPtr r100 = R100_CONTEXT(ctx);
312 BATCH_LOCALS(&r100->radeon);
313 struct radeon_renderbuffer *rrb;
314 uint32_t cbpitch;
315 uint32_t zbpitch, depth_fmt;
316 uint32_t dwords = atom->cmd_size;
317
318 /* output the first 7 bytes of context */
319 BEGIN_BATCH_NO_AUTOSTATE(dwords + 4);
320 OUT_BATCH_TABLE(atom->cmd, 5);
321
322 rrb = radeon_get_depthbuffer(&r100->radeon);
323 if (!rrb) {
324 OUT_BATCH(0);
325 OUT_BATCH(0);
326 } else {
327 zbpitch = (rrb->pitch / rrb->cpp);
328 if (r100->using_hyperz)
329 zbpitch |= RADEON_DEPTH_HYPERZ;
330
331 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
332 OUT_BATCH(zbpitch);
333 if (rrb->cpp == 4)
334 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
335 else
336 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
337 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
338 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
339 }
340
341 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
342 OUT_BATCH(atom->cmd[CTX_CMD_1]);
343 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
344
345 rrb = radeon_get_colorbuffer(&r100->radeon);
346 if (!rrb || !rrb->bo) {
347 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
348 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
349 } else {
350 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
351 if (rrb->cpp == 4)
352 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
353 else
354 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
355
356 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
357 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
358 }
359
360 OUT_BATCH(atom->cmd[CTX_CMD_2]);
361
362 if (!rrb || !rrb->bo) {
363 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
364 } else {
365 cbpitch = (rrb->pitch / rrb->cpp);
366 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
367 cbpitch |= RADEON_COLOR_TILE_ENABLE;
368 OUT_BATCH(cbpitch);
369 }
370
371 END_BATCH();
372 }
373
374 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
375 {
376 r100ContextPtr r100 = R100_CONTEXT(ctx);
377 BATCH_LOCALS(&r100->radeon);
378 struct radeon_renderbuffer *rrb, *drb;
379 uint32_t cbpitch = 0;
380 uint32_t zbpitch = 0;
381 uint32_t dwords = atom->cmd_size;
382 uint32_t depth_fmt;
383
384 rrb = radeon_get_colorbuffer(&r100->radeon);
385 if (!rrb || !rrb->bo) {
386 fprintf(stderr, "no rrb\n");
387 return;
388 }
389
390 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
391 if (rrb->cpp == 4)
392 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
393 else
394 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
395
396 cbpitch = (rrb->pitch / rrb->cpp);
397 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
398 cbpitch |= R200_COLOR_TILE_ENABLE;
399
400 drb = radeon_get_depthbuffer(&r100->radeon);
401 if (drb) {
402 zbpitch = (drb->pitch / drb->cpp);
403 if (drb->cpp == 4)
404 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
405 else
406 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
407 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
408 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
409
410 }
411
412 /* output the first 7 bytes of context */
413 dwords = 10;
414 if (drb)
415 dwords += 6;
416 if (rrb)
417 dwords += 6;
418 BEGIN_BATCH_NO_AUTOSTATE(dwords);
419
420 /* In the CS case we need to split this up */
421 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
422 OUT_BATCH_TABLE((atom->cmd + 1), 4);
423
424 if (drb) {
425 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
426 OUT_BATCH_RELOC(0, drb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
427
428 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
429 OUT_BATCH(zbpitch);
430 }
431
432 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
433 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
434 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
435 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
436 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
437
438 if (rrb) {
439 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
440 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
441
442 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
443 OUT_BATCH(cbpitch);
444 }
445
446 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
447 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
448 // }
449
450 END_BATCH();
451 BEGIN_BATCH_NO_AUTOSTATE(4);
452 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
453 OUT_BATCH(0);
454 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
455 if (rrb) {
456 OUT_BATCH(((rrb->width - 1) << RADEON_RE_WIDTH_SHIFT) |
457 ((rrb->height - 1) << RADEON_RE_HEIGHT_SHIFT));
458 } else {
459 OUT_BATCH(0);
460 }
461 END_BATCH();
462 }
463
464 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
465 {
466 r100ContextPtr r100 = R100_CONTEXT(ctx);
467 BATCH_LOCALS(&r100->radeon);
468 uint32_t dwords = 2;
469 int i = atom->idx, j;
470 radeonTexObj *t = r100->state.texture.unit[i].texobj;
471 radeon_mipmap_level *lvl;
472 uint32_t base_reg;
473
474 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
475 return;
476
477 if (!t)
478 return;
479
480 if (!t->mt)
481 return;
482
483 switch(i) {
484 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
485 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
486 default:
487 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
488 };
489 BEGIN_BATCH_NO_AUTOSTATE(dwords + (5 * 4));
490 OUT_BATCH_TABLE(atom->cmd, 2);
491 lvl = &t->mt->levels[0];
492 for (j = 0; j < 5; j++) {
493 OUT_BATCH(CP_PACKET0(base_reg + (4 * (j-1)), 0));
494 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
495 RADEON_GEM_DOMAIN_VRAM, 0, 0);
496 }
497 END_BATCH();
498 }
499
500 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
501 {
502 r100ContextPtr r100 = R100_CONTEXT(ctx);
503 BATCH_LOCALS(&r100->radeon);
504 uint32_t dwords = atom->cmd_size;
505 int i = atom->idx;
506 radeonTexObj *t = r100->state.texture.unit[i].texobj;
507 radeon_mipmap_level *lvl;
508
509 if (t && t->mt && !t->image_override)
510 dwords += 2;
511 BEGIN_BATCH_NO_AUTOSTATE(dwords);
512
513 OUT_BATCH_TABLE(atom->cmd, 3);
514 if (t && t->mt && !t->image_override) {
515 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
516 lvl = &t->mt->levels[0];
517 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
518 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
519 } else {
520 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
521 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
522 }
523 } else if (!t) {
524 /* workaround for old CS mechanism */
525 OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
526 // OUT_BATCH(r100->radeon.radeonScreen);
527 } else {
528 OUT_BATCH(t->override_offset);
529 }
530
531 OUT_BATCH_TABLE((atom->cmd+4), 5);
532 END_BATCH();
533 }
534
535 static void tex_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
536 {
537 r100ContextPtr r100 = R100_CONTEXT(ctx);
538 BATCH_LOCALS(&r100->radeon);
539 uint32_t dwords = atom->cmd_size;
540 int i = atom->idx;
541 radeonTexObj *t = r100->state.texture.unit[i].texobj;
542 radeon_mipmap_level *lvl;
543 int hastexture = 1;
544
545 if (!t)
546 hastexture = 0;
547 else {
548 if (!t->mt && !t->bo)
549 hastexture = 0;
550 }
551 dwords += 1;
552 if (hastexture)
553 dwords += 2;
554 else
555 dwords -= 2;
556 BEGIN_BATCH_NO_AUTOSTATE(dwords);
557
558 OUT_BATCH(CP_PACKET0(RADEON_PP_TXFILTER_0 + (24 * i), 1));
559 OUT_BATCH_TABLE((atom->cmd + 1), 2);
560
561 if (hastexture) {
562 OUT_BATCH(CP_PACKET0(RADEON_PP_TXOFFSET_0 + (24 * i), 0));
563 if (t->mt && !t->image_override) {
564 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
565 lvl = &t->mt->levels[0];
566 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
567 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
568 } else {
569 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
570 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
571 }
572 } else {
573 if (t->bo)
574 OUT_BATCH_RELOC(t->tile_bits, t->bo, 0,
575 RADEON_GEM_DOMAIN_GTT|RADEON_GEM_DOMAIN_VRAM, 0, 0);
576 }
577 }
578
579 OUT_BATCH(CP_PACKET0(RADEON_PP_TXCBLEND_0 + (i * 24), 1));
580 OUT_BATCH_TABLE((atom->cmd+4), 2);
581 OUT_BATCH(CP_PACKET0(RADEON_PP_BORDER_COLOR_0 + (i * 4), 0));
582 OUT_BATCH((atom->cmd[TEX_PP_BORDER_COLOR]));
583 END_BATCH();
584 }
585
586 /* Initialize the context's hardware state.
587 */
588 void radeonInitState( r100ContextPtr rmesa )
589 {
590 GLcontext *ctx = rmesa->radeon.glCtx;
591 GLuint i;
592
593 rmesa->radeon.state.color.clear = 0x00000000;
594
595 switch ( ctx->Visual.depthBits ) {
596 case 16:
597 rmesa->radeon.state.depth.clear = 0x0000ffff;
598 rmesa->radeon.state.stencil.clear = 0x00000000;
599 break;
600 case 24:
601 rmesa->radeon.state.depth.clear = 0x00ffffff;
602 rmesa->radeon.state.stencil.clear = 0xffff0000;
603 break;
604 default:
605 break;
606 }
607
608 rmesa->radeon.Fallback = 0;
609
610
611 rmesa->radeon.hw.max_state_size = 0;
612
613 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
614 do { \
615 rmesa->hw.ATOM.cmd_size = SZ; \
616 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
617 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
618 rmesa->hw.ATOM.name = NM; \
619 rmesa->hw.ATOM.is_tcl = FLAG; \
620 rmesa->hw.ATOM.check = check_##CHK; \
621 rmesa->hw.ATOM.dirty = GL_TRUE; \
622 rmesa->hw.ATOM.idx = IDX; \
623 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
624 } while (0)
625
626 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
627 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
628
629 /* Allocate state buffers:
630 */
631 ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
632 if (rmesa->radeon.radeonScreen->kernel_mm)
633 rmesa->hw.ctx.emit = ctx_emit_cs;
634 else
635 rmesa->hw.ctx.emit = ctx_emit;
636 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
637 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
638 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
639 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
640 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
641 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
642 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
643 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
644 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
645 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
646 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
647 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
648 ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
649 ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
650 ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2);
651
652 for (i = 0; i < 3; i++) {
653 if (rmesa->radeon.radeonScreen->kernel_mm)
654 rmesa->hw.tex[i].emit = tex_emit_cs;
655 else
656 rmesa->hw.tex[i].emit = tex_emit;
657 }
658 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
659 {
660 ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
661 ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
662 ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
663 for (i = 0; i < 3; i++)
664 rmesa->hw.cube[i].emit = cube_emit;
665 }
666 else
667 {
668 ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
669 ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
670 ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
671 }
672 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
673 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
674 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
675 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
676 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
677 ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
678 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
679 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
680 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
681 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
682 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
683 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
684 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
685 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
686 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
687 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
688 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
689 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
690 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
691 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
692 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
693 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
694 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );
695
696 radeonSetUpAtomList( rmesa );
697
698 /* Fill in the packet headers:
699 */
700 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
701 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
702 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
703 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
704 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
705 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
706 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
707 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
708 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
709 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
710 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
711 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
712 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
713 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
714 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
715 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
716 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
717 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
718 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
719 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
720 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
721 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
722 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
723 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
724 rmesa->hw.mtl.cmd[MTL_CMD_0] =
725 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
726 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
727 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
728 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
729 rmesa->hw.grd.cmd[GRD_CMD_0] =
730 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
731 rmesa->hw.fog.cmd[FOG_CMD_0] =
732 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
733 rmesa->hw.glt.cmd[GLT_CMD_0] =
734 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
735 rmesa->hw.eye.cmd[EYE_CMD_0] =
736 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
737
738 for (i = 0 ; i < 6; i++) {
739 rmesa->hw.mat[i].cmd[MAT_CMD_0] =
740 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
741 }
742
743 for (i = 0 ; i < 8; i++) {
744 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
745 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
746 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
747 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
748 }
749
750 for (i = 0 ; i < 6; i++) {
751 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
752 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
753 }
754
755 if (rmesa->radeon.radeonScreen->kernel_mm) {
756 rmesa->hw.grd.emit = scl_emit;
757 rmesa->hw.fog.emit = vec_emit;
758 rmesa->hw.glt.emit = vec_emit;
759 rmesa->hw.eye.emit = vec_emit;
760
761 for (i = 0; i <= 6; i++)
762 rmesa->hw.mat[i].emit = vec_emit;
763
764 for (i = 0; i < 8; i++)
765 rmesa->hw.lit[i].emit = lit_emit;
766
767 for (i = 0; i < 6; i++)
768 rmesa->hw.ucp[i].emit = vec_emit;
769 }
770
771 rmesa->last_ReallyEnabled = -1;
772
773 /* Initial Harware state:
774 */
775 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
776 RADEON_CHROMA_FUNC_FAIL |
777 RADEON_CHROMA_KEY_NEAREST |
778 RADEON_SHADOW_FUNC_EQUAL |
779 RADEON_SHADOW_PASS_1 /*|
780 RADEON_RIGHT_HAND_CUBE_OGL */);
781
782 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
783 /* this bit unused for vertex fog */
784 RADEON_FOG_USE_DEPTH);
785
786 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
787
788 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
789 RADEON_SRC_BLEND_GL_ONE |
790 RADEON_DST_BLEND_GL_ZERO );
791
792 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
793 RADEON_STENCIL_TEST_ALWAYS |
794 RADEON_STENCIL_FAIL_KEEP |
795 RADEON_STENCIL_ZPASS_KEEP |
796 RADEON_STENCIL_ZFAIL_KEEP |
797 RADEON_Z_WRITE_ENABLE);
798
799 if (rmesa->using_hyperz) {
800 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
801 RADEON_Z_DECOMPRESSION_ENABLE;
802 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
803 /* works for q3, but slight rendering errors with glxgears ? */
804 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
805 /* need this otherwise get lots of lockups with q3 ??? */
806 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
807 }
808 }
809
810 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
811 RADEON_ANTI_ALIAS_NONE);
812
813 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
814 RADEON_ZBLOCK16);
815
816 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
817 case DRI_CONF_DITHER_XERRORDIFFRESET:
818 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
819 break;
820 case DRI_CONF_DITHER_ORDERED:
821 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
822 break;
823 }
824 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
825 DRI_CONF_ROUND_ROUND )
826 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
827 else
828 rmesa->radeon.state.color.roundEnable = 0;
829 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
830 DRI_CONF_COLOR_REDUCTION_DITHER )
831 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
832 else
833 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
834
835
836 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
837 RADEON_BFACE_SOLID |
838 RADEON_FFACE_SOLID |
839 /* RADEON_BADVTX_CULL_DISABLE | */
840 RADEON_FLAT_SHADE_VTX_LAST |
841 RADEON_DIFFUSE_SHADE_GOURAUD |
842 RADEON_ALPHA_SHADE_GOURAUD |
843 RADEON_SPECULAR_SHADE_GOURAUD |
844 RADEON_FOG_SHADE_GOURAUD |
845 RADEON_VPORT_XY_XFORM_ENABLE |
846 RADEON_VPORT_Z_XFORM_ENABLE |
847 RADEON_VTX_PIX_CENTER_OGL |
848 RADEON_ROUND_MODE_TRUNC |
849 RADEON_ROUND_PREC_8TH_PIX);
850
851 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
852 #ifdef MESA_BIG_ENDIAN
853 RADEON_VC_32BIT_SWAP;
854 #else
855 RADEON_VC_NO_SWAP;
856 #endif
857
858 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
859 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
860 }
861
862 rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
863 RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
864 RADEON_TEX1_W_ROUTING_USE_Q1);
865
866
867 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
868
869 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
870 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
871 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
872
873 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
874
875 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
876 ((0x00 << RADEON_STENCIL_REF_SHIFT) |
877 (0xff << RADEON_STENCIL_MASK_SHIFT) |
878 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
879
880 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
881 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
882
883 rmesa->hw.msc.cmd[MSC_RE_MISC] =
884 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
885 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
886 RADEON_STIPPLE_BIG_BIT_ORDER);
887
888 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
889 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
890 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
891 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
892 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
893 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
894
895 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
896 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
897 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
898 (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
899 RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
900 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
901 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
902 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
903
904 /* Initialize the texture offset to the start of the card texture heap */
905 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
906 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
907
908 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
909 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
910 (RADEON_COLOR_ARG_A_ZERO |
911 RADEON_COLOR_ARG_B_ZERO |
912 RADEON_COLOR_ARG_C_CURRENT_COLOR |
913 RADEON_BLEND_CTL_ADD |
914 RADEON_SCALE_1X |
915 RADEON_CLAMP_TX);
916 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
917 (RADEON_ALPHA_ARG_A_ZERO |
918 RADEON_ALPHA_ARG_B_ZERO |
919 RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
920 RADEON_BLEND_CTL_ADD |
921 RADEON_SCALE_1X |
922 RADEON_CLAMP_TX);
923 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
924
925 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
926 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
927 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
928 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
929 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
930 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
931 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
932 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
933 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
934 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
935 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
936 }
937
938 /* Can only add ST1 at the time of doing some multitex but can keep
939 * it after that. Errors if DIFFUSE is missing.
940 */
941 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
942 (RADEON_TCL_VTX_Z0 |
943 RADEON_TCL_VTX_W0 |
944 RADEON_TCL_VTX_PK_DIFFUSE
945 ); /* need to keep this uptodate */
946
947 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
948 ( RADEON_TCL_COMPUTE_XYZW |
949 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
950 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
951 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
952
953
954 /* XXX */
955 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
956 ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
957 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
958
959 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
960 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
961 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
962 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
963 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
964
965 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
966 (RADEON_UCP_IN_CLIP_SPACE |
967 RADEON_CULL_FRONT_IS_CCW);
968
969 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
970
971 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
972 (RADEON_SPECULAR_LIGHTS |
973 RADEON_DIFFUSE_SPECULAR_COMBINE |
974 RADEON_LOCAL_LIGHT_VEC_GL |
975 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
976 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
977 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
978 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
979
980 for (i = 0 ; i < 8; i++) {
981 struct gl_light *l = &ctx->Light.Light[i];
982 GLenum p = GL_LIGHT0 + i;
983 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
984
985 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
986 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
987 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
988 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
989 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
990 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
991 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
992 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
993 &l->ConstantAttenuation );
994 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
995 &l->LinearAttenuation );
996 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
997 &l->QuadraticAttenuation );
998 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
999 }
1000
1001 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
1002 ctx->Light.Model.Ambient );
1003
1004 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
1005
1006 for (i = 0 ; i < 6; i++) {
1007 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
1008 }
1009
1010 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
1011 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
1012 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
1013 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
1014 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
1015 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
1016
1017 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
1018 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
1019 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
1020 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
1021
1022 rmesa->hw.eye.cmd[EYE_X] = 0;
1023 rmesa->hw.eye.cmd[EYE_Y] = 0;
1024 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
1025 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
1026
1027 rmesa->radeon.hw.all_dirty = GL_TRUE;
1028
1029 rcommonInitCmdBuf(&rmesa->radeon);
1030 }