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radeon/r200/r300: another big merge upheavel.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c
1 /*
2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
28 */
29
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
33
34 #include "swrast/swrast.h"
35 #include "vbo/vbo.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
39
40 #include "radeon_context.h"
41 #include "common_cmdbuf.h"
42 #include "radeon_cs.h"
43 #include "radeon_mipmap_tree.h"
44 #include "radeon_ioctl.h"
45 #include "radeon_state.h"
46 #include "radeon_tcl.h"
47 #include "radeon_tex.h"
48 #include "radeon_swtcl.h"
49
50 #include "../r200/r200_reg.h"
51
52 #include "xmlpool.h"
53
54 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
55 * 1.3 cmdbuffers allow all previous state to be updated as well as
56 * the tcl scalar and vector areas.
57 */
58 static struct {
59 int start;
60 int len;
61 const char *name;
62 } packet[RADEON_MAX_STATE_PACKETS] = {
63 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
64 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
65 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
66 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
67 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
68 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
69 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
70 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
71 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
72 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
73 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
74 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
75 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
76 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
77 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
78 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
79 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
80 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
81 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
82 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
83 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
84 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
85 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
86 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
87 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
88 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
89 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
90 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
91 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
92 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
93 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
94 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
95 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
96 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
97 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
98 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
99 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
100 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
101 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
102 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
103 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
104 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
105 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
106 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
107 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
108 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
109 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
110 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
111 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
112 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
113 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
114 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
115 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
116 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
117 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
118 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
119 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
120 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
121 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
122 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
123 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
124 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
125 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
126 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
127 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
128 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
129 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
130 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
131 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
132 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
133 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
134 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
135 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
136 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
137 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
138 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
139 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
140 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
141 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
142 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
143 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
144 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
145 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
146 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
147 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
148 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
149 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
150 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
151 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
152 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
153 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
154 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
155 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
156 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
157 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
158 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
159 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
160 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
161 };
162
163 /* =============================================================
164 * State initialization
165 */
166
167 void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
168 {
169 struct radeon_state_atom *l;
170
171 fprintf(stderr, msg);
172 fprintf(stderr, ": ");
173
174 foreach(l, &rmesa->radeon.hw.atomlist) {
175 if (l->dirty || rmesa->radeon.hw.all_dirty)
176 fprintf(stderr, "%s, ", l->name);
177 }
178
179 fprintf(stderr, "\n");
180 }
181
182 static int cmdpkt( r100ContextPtr rmesa, int id )
183 {
184 drm_radeon_cmd_header_t h;
185
186 if (rmesa->radeon.radeonScreen->kernel_mm) {
187 return CP_PACKET0(packet[id].start, packet[id].len - 1);
188 } else {
189 h.i = 0;
190 h.packet.cmd_type = RADEON_CMD_PACKET;
191 h.packet.packet_id = id;
192 }
193 return h.i;
194 }
195
196 static int cmdvec( int offset, int stride, int count )
197 {
198 drm_radeon_cmd_header_t h;
199 h.i = 0;
200 h.vectors.cmd_type = RADEON_CMD_VECTORS;
201 h.vectors.offset = offset;
202 h.vectors.stride = stride;
203 h.vectors.count = count;
204 return h.i;
205 }
206
207 static int cmdscl( int offset, int stride, int count )
208 {
209 drm_radeon_cmd_header_t h;
210 h.i = 0;
211 h.scalars.cmd_type = RADEON_CMD_SCALARS;
212 h.scalars.offset = offset;
213 h.scalars.stride = stride;
214 h.scalars.count = count;
215 return h.i;
216 }
217
218 #define CHECK( NM, FLAG ) \
219 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
220 { \
221 return FLAG ? atom->cmd_size : 0; \
222 }
223
224 #define TCL_CHECK( NM, FLAG ) \
225 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
226 { \
227 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
228 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
229 }
230
231
232 CHECK( always, GL_TRUE )
233 CHECK( never, GL_FALSE )
234 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
235 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
236 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
237 CHECK( tex2, ctx->Texture._EnabledUnits )
238 CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT))
239 CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT))
240 CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT))
241 CHECK( fog, ctx->Fog.Enabled )
242 TCL_CHECK( tcl, GL_TRUE )
243 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
244 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
245 TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled )
246 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
247 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
248 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
249 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
250 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
251 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
252 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
253 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
254 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
255 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
256 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
257 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
258 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
259 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
260 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
261 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
262 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
263
264 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
265 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
266 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT))
267
268 #define OUT_VEC(hdr, data) do { \
269 drm_radeon_cmd_header_t h; \
270 h.i = hdr; \
271 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
272 OUT_BATCH(0); \
273 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
274 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
275 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
276 OUT_BATCH_TABLE((data), h.vectors.count); \
277 } while(0)
278
279 #define OUT_SCL(hdr, data) do { \
280 drm_radeon_cmd_header_t h; \
281 h.i = hdr; \
282 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
283 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
284 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
285 OUT_BATCH_TABLE((data), h.scalars.count); \
286 } while(0)
287
288 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
289 {
290 r100ContextPtr r100 = R100_CONTEXT(ctx);
291 BATCH_LOCALS(&r100->radeon);
292 uint32_t dwords = atom->cmd_size;
293
294 BEGIN_BATCH_NO_AUTOSTATE(dwords);
295 OUT_SCL(atom->cmd[0], atom->cmd+1);
296 END_BATCH();
297 }
298
299
300 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
301 {
302 r100ContextPtr r100 = R100_CONTEXT(ctx);
303 BATCH_LOCALS(&r100->radeon);
304 uint32_t dwords = atom->cmd_size;
305
306 BEGIN_BATCH_NO_AUTOSTATE(dwords);
307 OUT_VEC(atom->cmd[0], atom->cmd+1);
308 END_BATCH();
309 }
310
311 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
312 {
313 r100ContextPtr r100 = R100_CONTEXT(ctx);
314 BATCH_LOCALS(&r100->radeon);
315 struct radeon_renderbuffer *rrb;
316 uint32_t cbpitch;
317 uint32_t zbpitch;
318 uint32_t dwords = atom->cmd_size;
319 GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate;
320
321 /* output the first 7 bytes of context */
322 BEGIN_BATCH_NO_AUTOSTATE(dwords + 4);
323 OUT_BATCH_TABLE(atom->cmd, 5);
324
325 rrb = r100->radeon.state.depth.rrb;
326 if (!rrb) {
327 OUT_BATCH(0);
328 OUT_BATCH(0);
329 } else {
330 zbpitch = (rrb->pitch / rrb->cpp);
331 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
332 OUT_BATCH(zbpitch);
333 }
334
335 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
336 OUT_BATCH(atom->cmd[CTX_CMD_1]);
337 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
338 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
339
340 rrb = r100->radeon.state.color.rrb;
341 if (r100->radeon.radeonScreen->driScreen->dri2.enabled) {
342 rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
343 }
344 if (!rrb || !rrb->bo) {
345 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
346 } else {
347 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
348 }
349
350 OUT_BATCH(atom->cmd[CTX_CMD_2]);
351
352 if (!rrb || !rrb->bo) {
353 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
354 } else {
355 cbpitch = (rrb->pitch / rrb->cpp);
356 if (rrb->cpp == 4)
357 ;
358 else
359 ;
360 if (r100->radeon.sarea->tiling_enabled)
361 cbpitch |= R200_COLOR_TILE_ENABLE;
362 OUT_BATCH(cbpitch);
363 }
364
365 END_BATCH();
366 }
367 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
368 {
369 r100ContextPtr r100 = R100_CONTEXT(ctx);
370 BATCH_LOCALS(&r100->radeon);
371 struct radeon_renderbuffer *rrb, *drb;
372 uint32_t cbpitch = 0;
373 uint32_t zbpitch = 0;
374 uint32_t dwords = atom->cmd_size;
375 GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate;
376
377 rrb = r100->radeon.state.color.rrb;
378 if (r100->radeon.radeonScreen->driScreen->dri2.enabled) {
379 rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
380 }
381 if (rrb) {
382 assert(rrb->bo != NULL);
383 cbpitch = (rrb->pitch / rrb->cpp);
384 if (r100->radeon.sarea->tiling_enabled)
385 cbpitch |= R200_COLOR_TILE_ENABLE;
386 }
387
388 drb = r100->radeon.state.depth.rrb;
389 if (drb)
390 zbpitch = (drb->pitch / drb->cpp);
391
392 /* output the first 7 bytes of context */
393 BEGIN_BATCH_NO_AUTOSTATE(dwords);
394
395 /* In the CS case we need to split this up */
396 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
397 OUT_BATCH_TABLE((atom->cmd + 1), 4);
398
399 if (drb) {
400 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
401 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
402
403 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
404 OUT_BATCH(zbpitch);
405 }
406
407 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
408 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
409 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
410 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
411 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
412
413
414 if (rrb) {
415 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
416 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
417 }
418
419 if (rrb) {
420 if (rrb->cpp == 4)
421 ;
422 else
423 ;
424 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
425 OUT_BATCH(cbpitch);
426 }
427
428 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
429 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
430 // }
431
432 END_BATCH();
433 }
434
435 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
436 {
437 r100ContextPtr r100 = R100_CONTEXT(ctx);
438 BATCH_LOCALS(&r100->radeon);
439 uint32_t dwords = atom->cmd_size;
440 int i = atom->idx;
441 radeonTexObj *t = r100->state.texture.unit[i].texobj;
442
443 if (t && t->mt && !t->image_override)
444 dwords += 2;
445 BEGIN_BATCH_NO_AUTOSTATE(dwords);
446 OUT_BATCH_TABLE(atom->cmd, 3);
447 if (t && t->mt && !t->image_override) {
448 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
449 RADEON_GEM_DOMAIN_VRAM, 0, 0);
450 } else {
451 /* workaround for old CS mechanism */
452 OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
453 // OUT_BATCH(r100->radeon.radeonScreen);
454 }
455
456 OUT_BATCH_TABLE((atom->cmd+4), 5);
457 END_BATCH();
458 }
459
460 /* Initialize the context's hardware state.
461 */
462 void radeonInitState( r100ContextPtr rmesa )
463 {
464 GLcontext *ctx = rmesa->radeon.glCtx;
465 GLuint color_fmt, depth_fmt, i;
466 GLint drawPitch, drawOffset;
467
468 switch ( rmesa->radeon.radeonScreen->cpp ) {
469 case 2:
470 color_fmt = RADEON_COLOR_FORMAT_RGB565;
471 break;
472 case 4:
473 color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
474 break;
475 default:
476 fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
477 exit( -1 );
478 }
479
480 rmesa->radeon.state.color.clear = 0x00000000;
481
482 switch ( ctx->Visual.depthBits ) {
483 case 16:
484 rmesa->radeon.state.depth.clear = 0x0000ffff;
485 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
486 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
487 rmesa->radeon.state.stencil.clear = 0x00000000;
488 break;
489 case 24:
490 rmesa->radeon.state.depth.clear = 0x00ffffff;
491 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
492 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
493 rmesa->radeon.state.stencil.clear = 0xffff0000;
494 break;
495 default:
496 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
497 ctx->Visual.depthBits );
498 exit( -1 );
499 }
500
501 /* Only have hw stencil when depth buffer is 24 bits deep */
502 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
503 ctx->Visual.depthBits == 24 );
504
505 rmesa->radeon.Fallback = 0;
506
507 if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
508 drawOffset = rmesa->radeon.radeonScreen->backOffset;
509 drawPitch = rmesa->radeon.radeonScreen->backPitch;
510 } else {
511 drawOffset = rmesa->radeon.radeonScreen->frontOffset;
512 drawPitch = rmesa->radeon.radeonScreen->frontPitch;
513 }
514
515 rmesa->radeon.hw.max_state_size = 0;
516
517 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
518 do { \
519 rmesa->hw.ATOM.cmd_size = SZ; \
520 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
521 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
522 rmesa->hw.ATOM.name = NM; \
523 rmesa->hw.ATOM.is_tcl = FLAG; \
524 rmesa->hw.ATOM.check = check_##CHK; \
525 rmesa->hw.ATOM.dirty = GL_TRUE; \
526 rmesa->hw.ATOM.idx = IDX; \
527 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
528 } while (0)
529
530 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
531 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
532
533 /* Allocate state buffers:
534 */
535 ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
536 if (rmesa->radeon.radeonScreen->kernel_mm)
537 rmesa->hw.ctx.emit = ctx_emit_cs;
538 else
539 rmesa->hw.ctx.emit = ctx_emit;
540 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
541 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
542 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
543 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
544 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
545 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
546 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
547 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
548 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
549 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
550 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
551 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
552 ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
553 ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
554 ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2 );
555
556 for (i = 0; i < 3; i++)
557 rmesa->hw.tex[i].emit = tex_emit;
558 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
559 {
560 ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
561 ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
562 ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
563 }
564 else
565 {
566 ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
567 ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
568 ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
569 }
570 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
571 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
572 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
573 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
574 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
575 ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
576 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
577 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
578 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
579 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
580 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
581 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
582 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
583 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
584 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
585 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
586 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
587 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
588 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
589 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
590 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
591 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
592 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );
593
594 radeonSetUpAtomList( rmesa );
595
596 /* Fill in the packet headers:
597 */
598 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
599 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
600 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
601 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
602 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
603 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
604 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
605 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
606 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
607 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
608 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
609 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
610 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
611 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
612 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
613 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
614 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
615 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
616 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
617 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
618 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
619 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
620 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
621 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
622 rmesa->hw.mtl.cmd[MTL_CMD_0] =
623 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
624 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
625 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
626 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
627 rmesa->hw.grd.cmd[GRD_CMD_0] =
628 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
629 rmesa->hw.fog.cmd[FOG_CMD_0] =
630 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
631 rmesa->hw.glt.cmd[GLT_CMD_0] =
632 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
633 rmesa->hw.eye.cmd[EYE_CMD_0] =
634 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
635
636 for (i = 0 ; i < 6; i++) {
637 rmesa->hw.mat[i].cmd[MAT_CMD_0] =
638 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
639 }
640
641 for (i = 0 ; i < 8; i++) {
642 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
643 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
644 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
645 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
646 }
647
648 for (i = 0 ; i < 6; i++) {
649 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
650 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
651 }
652
653 rmesa->last_ReallyEnabled = -1;
654
655 /* Initial Harware state:
656 */
657 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
658 RADEON_CHROMA_FUNC_FAIL |
659 RADEON_CHROMA_KEY_NEAREST |
660 RADEON_SHADOW_FUNC_EQUAL |
661 RADEON_SHADOW_PASS_1 /*|
662 RADEON_RIGHT_HAND_CUBE_OGL */);
663
664 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
665 /* this bit unused for vertex fog */
666 RADEON_FOG_USE_DEPTH);
667
668 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
669
670 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
671 RADEON_SRC_BLEND_GL_ONE |
672 RADEON_DST_BLEND_GL_ZERO );
673
674 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
675 rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
676
677 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
678 ((rmesa->radeon.radeonScreen->depthPitch &
679 RADEON_DEPTHPITCH_MASK) |
680 RADEON_DEPTH_ENDIAN_NO_SWAP);
681
682 if (rmesa->using_hyperz)
683 rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
684
685 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
686 RADEON_Z_TEST_LESS |
687 RADEON_STENCIL_TEST_ALWAYS |
688 RADEON_STENCIL_FAIL_KEEP |
689 RADEON_STENCIL_ZPASS_KEEP |
690 RADEON_STENCIL_ZFAIL_KEEP |
691 RADEON_Z_WRITE_ENABLE);
692
693 if (rmesa->using_hyperz) {
694 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
695 RADEON_Z_DECOMPRESSION_ENABLE;
696 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
697 /* works for q3, but slight rendering errors with glxgears ? */
698 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
699 /* need this otherwise get lots of lockups with q3 ??? */
700 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
701 }
702 }
703
704 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
705 RADEON_ANTI_ALIAS_NONE);
706
707 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
708 color_fmt |
709 RADEON_ZBLOCK16);
710
711 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
712 case DRI_CONF_DITHER_XERRORDIFFRESET:
713 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
714 break;
715 case DRI_CONF_DITHER_ORDERED:
716 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
717 break;
718 }
719 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
720 DRI_CONF_ROUND_ROUND )
721 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
722 else
723 rmesa->radeon.state.color.roundEnable = 0;
724 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
725 DRI_CONF_COLOR_REDUCTION_DITHER )
726 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
727 else
728 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
729
730 rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
731 rmesa->radeon.radeonScreen->fbLocation)
732 & RADEON_COLOROFFSET_MASK);
733
734 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
735 RADEON_COLORPITCH_MASK) |
736 RADEON_COLOR_ENDIAN_NO_SWAP);
737
738
739 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
740 if (rmesa->radeon.sarea->tiling_enabled) {
741 rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
742 }
743
744 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
745 RADEON_BFACE_SOLID |
746 RADEON_FFACE_SOLID |
747 /* RADEON_BADVTX_CULL_DISABLE | */
748 RADEON_FLAT_SHADE_VTX_LAST |
749 RADEON_DIFFUSE_SHADE_GOURAUD |
750 RADEON_ALPHA_SHADE_GOURAUD |
751 RADEON_SPECULAR_SHADE_GOURAUD |
752 RADEON_FOG_SHADE_GOURAUD |
753 RADEON_VPORT_XY_XFORM_ENABLE |
754 RADEON_VPORT_Z_XFORM_ENABLE |
755 RADEON_VTX_PIX_CENTER_OGL |
756 RADEON_ROUND_MODE_TRUNC |
757 RADEON_ROUND_PREC_8TH_PIX);
758
759 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
760 #ifdef MESA_BIG_ENDIAN
761 RADEON_VC_32BIT_SWAP;
762 #else
763 RADEON_VC_NO_SWAP;
764 #endif
765
766 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
767 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
768 }
769
770 rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
771 RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
772 RADEON_TEX1_W_ROUTING_USE_Q1);
773
774
775 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
776
777 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
778 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
779 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
780
781 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
782
783 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
784 ((0x00 << RADEON_STENCIL_REF_SHIFT) |
785 (0xff << RADEON_STENCIL_MASK_SHIFT) |
786 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
787
788 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
789 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
790
791 rmesa->hw.msc.cmd[MSC_RE_MISC] =
792 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
793 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
794 RADEON_STIPPLE_BIG_BIT_ORDER);
795
796 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
797 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
798 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
799 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
800 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
801 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
802
803 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
804 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
805 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
806 (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
807 RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
808 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
809 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
810 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
811
812 /* Initialize the texture offset to the start of the card texture heap */
813 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
814 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
815
816 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
817 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
818 (RADEON_COLOR_ARG_A_ZERO |
819 RADEON_COLOR_ARG_B_ZERO |
820 RADEON_COLOR_ARG_C_CURRENT_COLOR |
821 RADEON_BLEND_CTL_ADD |
822 RADEON_SCALE_1X |
823 RADEON_CLAMP_TX);
824 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
825 (RADEON_ALPHA_ARG_A_ZERO |
826 RADEON_ALPHA_ARG_B_ZERO |
827 RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
828 RADEON_BLEND_CTL_ADD |
829 RADEON_SCALE_1X |
830 RADEON_CLAMP_TX);
831 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
832
833 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
834 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
835 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
836 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
837 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
838 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
839 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
840 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
841 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
842 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
843 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
844 }
845
846 /* Can only add ST1 at the time of doing some multitex but can keep
847 * it after that. Errors if DIFFUSE is missing.
848 */
849 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
850 (RADEON_TCL_VTX_Z0 |
851 RADEON_TCL_VTX_W0 |
852 RADEON_TCL_VTX_PK_DIFFUSE
853 ); /* need to keep this uptodate */
854
855 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
856 ( RADEON_TCL_COMPUTE_XYZW |
857 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
858 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
859 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
860
861
862 /* XXX */
863 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
864 ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
865 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
866
867 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
868 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
869 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
870 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
871 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
872
873 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
874 (RADEON_UCP_IN_CLIP_SPACE |
875 RADEON_CULL_FRONT_IS_CCW);
876
877 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
878
879 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
880 (RADEON_SPECULAR_LIGHTS |
881 RADEON_DIFFUSE_SPECULAR_COMBINE |
882 RADEON_LOCAL_LIGHT_VEC_GL |
883 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
884 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
885 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
886 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
887
888 for (i = 0 ; i < 8; i++) {
889 struct gl_light *l = &ctx->Light.Light[i];
890 GLenum p = GL_LIGHT0 + i;
891 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
892
893 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
894 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
895 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
896 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
897 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
898 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
899 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
900 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
901 &l->ConstantAttenuation );
902 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
903 &l->LinearAttenuation );
904 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
905 &l->QuadraticAttenuation );
906 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
907 }
908
909 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
910 ctx->Light.Model.Ambient );
911
912 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
913
914 for (i = 0 ; i < 6; i++) {
915 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
916 }
917
918 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
919 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
920 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
921 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
922 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
923 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
924
925 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
926 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
927 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
928 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
929
930 rmesa->hw.eye.cmd[EYE_X] = 0;
931 rmesa->hw.eye.cmd[EYE_Y] = 0;
932 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
933 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
934
935 rmesa->radeon.hw.all_dirty = GL_TRUE;
936
937 rcommonInitCmdBuf(&rmesa->radeon);
938 }