2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
34 #include "swrast/swrast.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
40 #include "radeon_context.h"
41 #include "radeon_ioctl.h"
42 #include "radeon_state.h"
43 #include "radeon_tcl.h"
44 #include "radeon_tex.h"
45 #include "radeon_swtcl.h"
49 /* =============================================================
50 * State initialization
53 void radeonPrintDirty( radeonContextPtr rmesa
, const char *msg
)
55 struct radeon_state_atom
*l
;
58 fprintf(stderr
, ": ");
60 foreach(l
, &rmesa
->hw
.atomlist
) {
61 if (l
->dirty
|| rmesa
->hw
.all_dirty
)
62 fprintf(stderr
, "%s, ", l
->name
);
65 fprintf(stderr
, "\n");
68 static int cmdpkt( int id
)
70 drm_radeon_cmd_header_t h
;
72 h
.packet
.cmd_type
= RADEON_CMD_PACKET
;
73 h
.packet
.packet_id
= id
;
77 static int cmdvec( int offset
, int stride
, int count
)
79 drm_radeon_cmd_header_t h
;
81 h
.vectors
.cmd_type
= RADEON_CMD_VECTORS
;
82 h
.vectors
.offset
= offset
;
83 h
.vectors
.stride
= stride
;
84 h
.vectors
.count
= count
;
88 static int cmdscl( int offset
, int stride
, int count
)
90 drm_radeon_cmd_header_t h
;
92 h
.scalars
.cmd_type
= RADEON_CMD_SCALARS
;
93 h
.scalars
.offset
= offset
;
94 h
.scalars
.stride
= stride
;
95 h
.scalars
.count
= count
;
99 #define CHECK( NM, FLAG ) \
100 static GLboolean check_##NM( GLcontext *ctx ) \
105 #define TCL_CHECK( NM, FLAG ) \
106 static GLboolean check_##NM( GLcontext *ctx ) \
108 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
109 return !rmesa->TclFallback && (FLAG); \
113 CHECK( always
, GL_TRUE
)
114 CHECK( never
, GL_FALSE
)
115 CHECK( tex0
, ctx
->Texture
.Unit
[0]._ReallyEnabled
)
116 CHECK( tex1
, ctx
->Texture
.Unit
[1]._ReallyEnabled
)
117 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
118 CHECK( tex2
, ctx
->Texture
._EnabledUnits
)
119 CHECK( cube0
, (ctx
->Texture
.Unit
[0]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
120 CHECK( cube1
, (ctx
->Texture
.Unit
[1]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
121 CHECK( cube2
, (ctx
->Texture
.Unit
[2]._ReallyEnabled
& TEXTURE_CUBE_BIT
))
122 CHECK( fog
, ctx
->Fog
.Enabled
)
123 TCL_CHECK( tcl
, GL_TRUE
)
124 TCL_CHECK( tcl_tex0
, ctx
->Texture
.Unit
[0]._ReallyEnabled
)
125 TCL_CHECK( tcl_tex1
, ctx
->Texture
.Unit
[1]._ReallyEnabled
)
126 TCL_CHECK( tcl_tex2
, ctx
->Texture
.Unit
[2]._ReallyEnabled
)
127 TCL_CHECK( tcl_lighting
, ctx
->Light
.Enabled
)
128 TCL_CHECK( tcl_eyespace_or_lighting
, ctx
->_NeedEyeCoords
|| ctx
->Light
.Enabled
)
129 TCL_CHECK( tcl_lit0
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[0].Enabled
)
130 TCL_CHECK( tcl_lit1
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[1].Enabled
)
131 TCL_CHECK( tcl_lit2
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[2].Enabled
)
132 TCL_CHECK( tcl_lit3
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[3].Enabled
)
133 TCL_CHECK( tcl_lit4
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[4].Enabled
)
134 TCL_CHECK( tcl_lit5
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[5].Enabled
)
135 TCL_CHECK( tcl_lit6
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[6].Enabled
)
136 TCL_CHECK( tcl_lit7
, ctx
->Light
.Enabled
&& ctx
->Light
.Light
[7].Enabled
)
137 TCL_CHECK( tcl_ucp0
, (ctx
->Transform
.ClipPlanesEnabled
& 0x1) )
138 TCL_CHECK( tcl_ucp1
, (ctx
->Transform
.ClipPlanesEnabled
& 0x2) )
139 TCL_CHECK( tcl_ucp2
, (ctx
->Transform
.ClipPlanesEnabled
& 0x4) )
140 TCL_CHECK( tcl_ucp3
, (ctx
->Transform
.ClipPlanesEnabled
& 0x8) )
141 TCL_CHECK( tcl_ucp4
, (ctx
->Transform
.ClipPlanesEnabled
& 0x10) )
142 TCL_CHECK( tcl_ucp5
, (ctx
->Transform
.ClipPlanesEnabled
& 0x20) )
143 TCL_CHECK( tcl_eyespace_or_fog
, ctx
->_NeedEyeCoords
|| ctx
->Fog
.Enabled
)
145 CHECK( txr0
, (ctx
->Texture
.Unit
[0]._ReallyEnabled
& TEXTURE_RECT_BIT
))
146 CHECK( txr1
, (ctx
->Texture
.Unit
[1]._ReallyEnabled
& TEXTURE_RECT_BIT
))
147 CHECK( txr2
, (ctx
->Texture
.Unit
[2]._ReallyEnabled
& TEXTURE_RECT_BIT
))
151 /* Initialize the context's hardware state.
153 void radeonInitState( radeonContextPtr rmesa
)
155 GLcontext
*ctx
= rmesa
->glCtx
;
156 GLuint color_fmt
, depth_fmt
, i
;
157 GLint drawPitch
, drawOffset
;
159 switch ( rmesa
->radeonScreen
->cpp
) {
161 color_fmt
= RADEON_COLOR_FORMAT_RGB565
;
164 color_fmt
= RADEON_COLOR_FORMAT_ARGB8888
;
167 fprintf( stderr
, "Error: Unsupported pixel depth... exiting\n" );
171 rmesa
->state
.color
.clear
= 0x00000000;
173 switch ( ctx
->Visual
.depthBits
) {
175 rmesa
->state
.depth
.clear
= 0x0000ffff;
176 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffff;
177 depth_fmt
= RADEON_DEPTH_FORMAT_16BIT_INT_Z
;
178 rmesa
->state
.stencil
.clear
= 0x00000000;
181 rmesa
->state
.depth
.clear
= 0x00ffffff;
182 rmesa
->state
.depth
.scale
= 1.0 / (GLfloat
)0xffffff;
183 depth_fmt
= RADEON_DEPTH_FORMAT_24BIT_INT_Z
;
184 rmesa
->state
.stencil
.clear
= 0xffff0000;
187 fprintf( stderr
, "Error: Unsupported depth %d... exiting\n",
188 ctx
->Visual
.depthBits
);
192 /* Only have hw stencil when depth buffer is 24 bits deep */
193 rmesa
->state
.stencil
.hwBuffer
= ( ctx
->Visual
.stencilBits
> 0 &&
194 ctx
->Visual
.depthBits
== 24 );
198 if ( ctx
->Visual
.doubleBufferMode
&& rmesa
->sarea
->pfCurrentPage
== 0 ) {
199 drawOffset
= rmesa
->radeonScreen
->backOffset
;
200 drawPitch
= rmesa
->radeonScreen
->backPitch
;
202 drawOffset
= rmesa
->radeonScreen
->frontOffset
;
203 drawPitch
= rmesa
->radeonScreen
->frontPitch
;
206 rmesa
->hw
.max_state_size
= 0;
208 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
210 rmesa->hw.ATOM.cmd_size = SZ; \
211 rmesa->hw.ATOM.cmd = (int *)CALLOC(SZ * sizeof(int)); \
212 rmesa->hw.ATOM.lastcmd = (int *)CALLOC(SZ * sizeof(int)); \
213 rmesa->hw.ATOM.name = NM; \
214 rmesa->hw.ATOM.is_tcl = FLAG; \
215 rmesa->hw.ATOM.check = check_##CHK; \
216 rmesa->hw.ATOM.dirty = GL_TRUE; \
217 rmesa->hw.max_state_size += SZ * sizeof(int); \
221 /* Allocate state buffers:
223 ALLOC_STATE( ctx
, always
, CTX_STATE_SIZE
, "CTX/context", 0 );
224 ALLOC_STATE( lin
, always
, LIN_STATE_SIZE
, "LIN/line", 0 );
225 ALLOC_STATE( msk
, always
, MSK_STATE_SIZE
, "MSK/mask", 0 );
226 ALLOC_STATE( vpt
, always
, VPT_STATE_SIZE
, "VPT/viewport", 0 );
227 ALLOC_STATE( set
, always
, SET_STATE_SIZE
, "SET/setup", 0 );
228 ALLOC_STATE( msc
, always
, MSC_STATE_SIZE
, "MSC/misc", 0 );
229 ALLOC_STATE( zbs
, always
, ZBS_STATE_SIZE
, "ZBS/zbias", 0 );
230 ALLOC_STATE( tcl
, always
, TCL_STATE_SIZE
, "TCL/tcl", 1 );
231 ALLOC_STATE( mtl
, tcl_lighting
, MTL_STATE_SIZE
, "MTL/material", 1 );
232 ALLOC_STATE( grd
, always
, GRD_STATE_SIZE
, "GRD/guard-band", 1 );
233 ALLOC_STATE( fog
, fog
, FOG_STATE_SIZE
, "FOG/fog", 1 );
234 ALLOC_STATE( glt
, tcl_lighting
, GLT_STATE_SIZE
, "GLT/light-global", 1 );
235 ALLOC_STATE( eye
, tcl_lighting
, EYE_STATE_SIZE
, "EYE/eye-vector", 1 );
236 ALLOC_STATE( tex
[0], tex0
, TEX_STATE_SIZE
, "TEX/tex-0", 0 );
237 ALLOC_STATE( tex
[1], tex1
, TEX_STATE_SIZE
, "TEX/tex-1", 0 );
238 ALLOC_STATE( tex
[2], tex2
, TEX_STATE_SIZE
, "TEX/tex-2", 0 );
239 if (rmesa
->radeonScreen
->drmSupportsCubeMapsR100
)
241 ALLOC_STATE( cube
[0], cube0
, CUBE_STATE_SIZE
, "CUBE/cube-0", 0 );
242 ALLOC_STATE( cube
[1], cube1
, CUBE_STATE_SIZE
, "CUBE/cube-1", 0 );
243 ALLOC_STATE( cube
[2], cube2
, CUBE_STATE_SIZE
, "CUBE/cube-2", 0 );
247 ALLOC_STATE( cube
[0], never
, CUBE_STATE_SIZE
, "CUBE/cube-0", 0 );
248 ALLOC_STATE( cube
[1], never
, CUBE_STATE_SIZE
, "CUBE/cube-1", 0 );
249 ALLOC_STATE( cube
[2], never
, CUBE_STATE_SIZE
, "CUBE/cube-2", 0 );
251 ALLOC_STATE( mat
[0], tcl
, MAT_STATE_SIZE
, "MAT/modelproject", 1 );
252 ALLOC_STATE( mat
[1], tcl_eyespace_or_fog
, MAT_STATE_SIZE
, "MAT/modelview", 1 );
253 ALLOC_STATE( mat
[2], tcl_eyespace_or_lighting
, MAT_STATE_SIZE
, "MAT/it-modelview", 1 );
254 ALLOC_STATE( mat
[3], tcl_tex0
, MAT_STATE_SIZE
, "MAT/texmat0", 1 );
255 ALLOC_STATE( mat
[4], tcl_tex1
, MAT_STATE_SIZE
, "MAT/texmat1", 1 );
256 ALLOC_STATE( mat
[5], tcl_tex2
, MAT_STATE_SIZE
, "MAT/texmat2", 1 );
257 ALLOC_STATE( ucp
[0], tcl_ucp0
, UCP_STATE_SIZE
, "UCP/userclip-0", 1 );
258 ALLOC_STATE( ucp
[1], tcl_ucp1
, UCP_STATE_SIZE
, "UCP/userclip-1", 1 );
259 ALLOC_STATE( ucp
[2], tcl_ucp2
, UCP_STATE_SIZE
, "UCP/userclip-2", 1 );
260 ALLOC_STATE( ucp
[3], tcl_ucp3
, UCP_STATE_SIZE
, "UCP/userclip-3", 1 );
261 ALLOC_STATE( ucp
[4], tcl_ucp4
, UCP_STATE_SIZE
, "UCP/userclip-4", 1 );
262 ALLOC_STATE( ucp
[5], tcl_ucp5
, UCP_STATE_SIZE
, "UCP/userclip-5", 1 );
263 ALLOC_STATE( lit
[0], tcl_lit0
, LIT_STATE_SIZE
, "LIT/light-0", 1 );
264 ALLOC_STATE( lit
[1], tcl_lit1
, LIT_STATE_SIZE
, "LIT/light-1", 1 );
265 ALLOC_STATE( lit
[2], tcl_lit2
, LIT_STATE_SIZE
, "LIT/light-2", 1 );
266 ALLOC_STATE( lit
[3], tcl_lit3
, LIT_STATE_SIZE
, "LIT/light-3", 1 );
267 ALLOC_STATE( lit
[4], tcl_lit4
, LIT_STATE_SIZE
, "LIT/light-4", 1 );
268 ALLOC_STATE( lit
[5], tcl_lit5
, LIT_STATE_SIZE
, "LIT/light-5", 1 );
269 ALLOC_STATE( lit
[6], tcl_lit6
, LIT_STATE_SIZE
, "LIT/light-6", 1 );
270 ALLOC_STATE( lit
[7], tcl_lit7
, LIT_STATE_SIZE
, "LIT/light-7", 1 );
271 ALLOC_STATE( txr
[0], txr0
, TXR_STATE_SIZE
, "TXR/txr-0", 0 );
272 ALLOC_STATE( txr
[1], txr1
, TXR_STATE_SIZE
, "TXR/txr-1", 0 );
273 ALLOC_STATE( txr
[2], txr2
, TXR_STATE_SIZE
, "TXR/txr-2", 0 );
275 radeonSetUpAtomList( rmesa
);
277 /* Fill in the packet headers:
279 rmesa
->hw
.ctx
.cmd
[CTX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_MISC
);
280 rmesa
->hw
.ctx
.cmd
[CTX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CNTL
);
281 rmesa
->hw
.ctx
.cmd
[CTX_CMD_2
] = cmdpkt(RADEON_EMIT_RB3D_COLORPITCH
);
282 rmesa
->hw
.lin
.cmd
[LIN_CMD_0
] = cmdpkt(RADEON_EMIT_RE_LINE_PATTERN
);
283 rmesa
->hw
.lin
.cmd
[LIN_CMD_1
] = cmdpkt(RADEON_EMIT_SE_LINE_WIDTH
);
284 rmesa
->hw
.msk
.cmd
[MSK_CMD_0
] = cmdpkt(RADEON_EMIT_RB3D_STENCILREFMASK
);
285 rmesa
->hw
.vpt
.cmd
[VPT_CMD_0
] = cmdpkt(RADEON_EMIT_SE_VPORT_XSCALE
);
286 rmesa
->hw
.set
.cmd
[SET_CMD_0
] = cmdpkt(RADEON_EMIT_SE_CNTL
);
287 rmesa
->hw
.set
.cmd
[SET_CMD_1
] = cmdpkt(RADEON_EMIT_SE_CNTL_STATUS
);
288 rmesa
->hw
.msc
.cmd
[MSC_CMD_0
] = cmdpkt(RADEON_EMIT_RE_MISC
);
289 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_TXFILTER_0
);
290 rmesa
->hw
.tex
[0].cmd
[TEX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_0
);
291 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_TXFILTER_1
);
292 rmesa
->hw
.tex
[1].cmd
[TEX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_1
);
293 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_0
] = cmdpkt(RADEON_EMIT_PP_TXFILTER_2
);
294 rmesa
->hw
.tex
[2].cmd
[TEX_CMD_1
] = cmdpkt(RADEON_EMIT_PP_BORDER_COLOR_2
);
295 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_0
] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_0
);
296 rmesa
->hw
.cube
[0].cmd
[CUBE_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T0
);
297 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_0
] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_1
);
298 rmesa
->hw
.cube
[1].cmd
[CUBE_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T1
);
299 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_0
] = cmdpkt(RADEON_EMIT_PP_CUBIC_FACES_2
);
300 rmesa
->hw
.cube
[2].cmd
[CUBE_CMD_1
] = cmdpkt(RADEON_EMIT_PP_CUBIC_OFFSETS_T2
);
301 rmesa
->hw
.zbs
.cmd
[ZBS_CMD_0
] = cmdpkt(RADEON_EMIT_SE_ZBIAS_FACTOR
);
302 rmesa
->hw
.tcl
.cmd
[TCL_CMD_0
] = cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT
);
303 rmesa
->hw
.mtl
.cmd
[MTL_CMD_0
] =
304 cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED
);
305 rmesa
->hw
.txr
[0].cmd
[TXR_CMD_0
] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0
);
306 rmesa
->hw
.txr
[1].cmd
[TXR_CMD_0
] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1
);
307 rmesa
->hw
.txr
[2].cmd
[TXR_CMD_0
] = cmdpkt(RADEON_EMIT_PP_TEX_SIZE_2
);
308 rmesa
->hw
.grd
.cmd
[GRD_CMD_0
] =
309 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR
, 1, 4 );
310 rmesa
->hw
.fog
.cmd
[FOG_CMD_0
] =
311 cmdvec( RADEON_VS_FOG_PARAM_ADDR
, 1, 4 );
312 rmesa
->hw
.glt
.cmd
[GLT_CMD_0
] =
313 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR
, 1, 4 );
314 rmesa
->hw
.eye
.cmd
[EYE_CMD_0
] =
315 cmdvec( RADEON_VS_EYE_VECTOR_ADDR
, 1, 4 );
317 for (i
= 0 ; i
< 6; i
++) {
318 rmesa
->hw
.mat
[i
].cmd
[MAT_CMD_0
] =
319 cmdvec( RADEON_VS_MATRIX_0_ADDR
+ i
*4, 1, 16);
322 for (i
= 0 ; i
< 8; i
++) {
323 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_0
] =
324 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR
+ i
, 8, 24 );
325 rmesa
->hw
.lit
[i
].cmd
[LIT_CMD_1
] =
326 cmdscl( RADEON_SS_LIGHT_DCD_ADDR
+ i
, 8, 6 );
329 for (i
= 0 ; i
< 6; i
++) {
330 rmesa
->hw
.ucp
[i
].cmd
[UCP_CMD_0
] =
331 cmdvec( RADEON_VS_UCP_ADDR
+ i
, 1, 4 );
334 rmesa
->last_ReallyEnabled
= -1;
336 /* Initial Harware state:
338 rmesa
->hw
.ctx
.cmd
[CTX_PP_MISC
] = (RADEON_ALPHA_TEST_PASS
|
339 RADEON_CHROMA_FUNC_FAIL
|
340 RADEON_CHROMA_KEY_NEAREST
|
341 RADEON_SHADOW_FUNC_EQUAL
|
342 RADEON_SHADOW_PASS_1
/*|
343 RADEON_RIGHT_HAND_CUBE_OGL */);
345 rmesa
->hw
.ctx
.cmd
[CTX_PP_FOG_COLOR
] = (RADEON_FOG_VERTEX
|
346 /* this bit unused for vertex fog */
347 RADEON_FOG_USE_DEPTH
);
349 rmesa
->hw
.ctx
.cmd
[CTX_RE_SOLID_COLOR
] = 0x00000000;
351 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_BLENDCNTL
] = (RADEON_COMB_FCN_ADD_CLAMP
|
352 RADEON_SRC_BLEND_GL_ONE
|
353 RADEON_DST_BLEND_GL_ZERO
);
355 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHOFFSET
] =
356 rmesa
->radeonScreen
->depthOffset
+ rmesa
->radeonScreen
->fbLocation
;
358 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] =
359 ((rmesa
->radeonScreen
->depthPitch
&
360 RADEON_DEPTHPITCH_MASK
) |
361 RADEON_DEPTH_ENDIAN_NO_SWAP
);
363 if (rmesa
->using_hyperz
)
364 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_DEPTHPITCH
] |= RADEON_DEPTH_HYPERZ
;
366 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] = (depth_fmt
|
368 RADEON_STENCIL_TEST_ALWAYS
|
369 RADEON_STENCIL_FAIL_KEEP
|
370 RADEON_STENCIL_ZPASS_KEEP
|
371 RADEON_STENCIL_ZFAIL_KEEP
|
372 RADEON_Z_WRITE_ENABLE
);
374 if (rmesa
->using_hyperz
) {
375 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_Z_COMPRESSION_ENABLE
|
376 RADEON_Z_DECOMPRESSION_ENABLE
;
377 if (rmesa
->radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
) {
378 /* works for q3, but slight rendering errors with glxgears ? */
379 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
380 /* need this otherwise get lots of lockups with q3 ??? */
381 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_ZSTENCILCNTL
] |= RADEON_FORCE_Z_DIRTY
;
385 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] = (RADEON_SCISSOR_ENABLE
|
386 RADEON_ANTI_ALIAS_NONE
);
388 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] = (RADEON_PLANE_MASK_ENABLE
|
392 switch ( driQueryOptioni( &rmesa
->optionCache
, "dither_mode" ) ) {
393 case DRI_CONF_DITHER_XERRORDIFFRESET
:
394 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_INIT
;
396 case DRI_CONF_DITHER_ORDERED
:
397 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_SCALE_DITHER_ENABLE
;
400 if ( driQueryOptioni( &rmesa
->optionCache
, "round_mode" ) ==
401 DRI_CONF_ROUND_ROUND
)
402 rmesa
->state
.color
.roundEnable
= RADEON_ROUND_ENABLE
;
404 rmesa
->state
.color
.roundEnable
= 0;
405 if ( driQueryOptioni (&rmesa
->optionCache
, "color_reduction" ) ==
406 DRI_CONF_COLOR_REDUCTION_DITHER
)
407 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= RADEON_DITHER_ENABLE
;
409 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_CNTL
] |= rmesa
->state
.color
.roundEnable
;
411 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLOROFFSET
] = ((drawOffset
+
412 rmesa
->radeonScreen
->fbLocation
)
413 & RADEON_COLOROFFSET_MASK
);
415 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] = ((drawPitch
&
416 RADEON_COLORPITCH_MASK
) |
417 RADEON_COLOR_ENDIAN_NO_SWAP
);
420 /* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
421 if (rmesa
->sarea
->tiling_enabled
) {
422 rmesa
->hw
.ctx
.cmd
[CTX_RB3D_COLORPITCH
] |= RADEON_COLOR_TILE_ENABLE
;
425 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = (RADEON_FFACE_CULL_CCW
|
428 /* RADEON_BADVTX_CULL_DISABLE | */
429 RADEON_FLAT_SHADE_VTX_LAST
|
430 RADEON_DIFFUSE_SHADE_GOURAUD
|
431 RADEON_ALPHA_SHADE_GOURAUD
|
432 RADEON_SPECULAR_SHADE_GOURAUD
|
433 RADEON_FOG_SHADE_GOURAUD
|
434 RADEON_VPORT_XY_XFORM_ENABLE
|
435 RADEON_VPORT_Z_XFORM_ENABLE
|
436 RADEON_VTX_PIX_CENTER_OGL
|
437 RADEON_ROUND_MODE_TRUNC
|
438 RADEON_ROUND_PREC_8TH_PIX
);
440 rmesa
->hw
.set
.cmd
[SET_SE_CNTL_STATUS
] =
441 #ifdef MESA_BIG_ENDIAN
442 RADEON_VC_32BIT_SWAP
;
447 if (!(rmesa
->radeonScreen
->chip_flags
& RADEON_CHIPSET_TCL
)) {
448 rmesa
->hw
.set
.cmd
[SET_SE_CNTL_STATUS
] |= RADEON_TCL_BYPASS
;
451 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = (
452 RADEON_VTX_W0_IS_NOT_1_OVER_W0
|
453 RADEON_TEX1_W_ROUTING_USE_Q1
);
456 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_PATTERN
] = ((1 << 16) | 0xffff);
458 rmesa
->hw
.lin
.cmd
[LIN_RE_LINE_STATE
] =
459 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT
) |
460 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT
));
462 rmesa
->hw
.lin
.cmd
[LIN_SE_LINE_WIDTH
] = (1 << 4);
464 rmesa
->hw
.msk
.cmd
[MSK_RB3D_STENCILREFMASK
] =
465 ((0x00 << RADEON_STENCIL_REF_SHIFT
) |
466 (0xff << RADEON_STENCIL_MASK_SHIFT
) |
467 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT
));
469 rmesa
->hw
.msk
.cmd
[MSK_RB3D_ROPCNTL
] = RADEON_ROP_COPY
;
470 rmesa
->hw
.msk
.cmd
[MSK_RB3D_PLANEMASK
] = 0xffffffff;
472 rmesa
->hw
.msc
.cmd
[MSC_RE_MISC
] =
473 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT
) |
474 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT
) |
475 RADEON_STIPPLE_BIG_BIT_ORDER
);
477 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XSCALE
] = 0x00000000;
478 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_XOFFSET
] = 0x00000000;
479 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YSCALE
] = 0x00000000;
480 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_YOFFSET
] = 0x00000000;
481 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZSCALE
] = 0x00000000;
482 rmesa
->hw
.vpt
.cmd
[VPT_SE_VPORT_ZOFFSET
] = 0x00000000;
484 for ( i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++ ) {
485 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFILTER
] = RADEON_BORDER_MODE_OGL
;
486 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXFORMAT
] =
487 (RADEON_TXFORMAT_ENDIAN_NO_SWAP
|
488 RADEON_TXFORMAT_PERSPECTIVE_ENABLE
|
489 (i
<< 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
490 (2 << RADEON_TXFORMAT_WIDTH_SHIFT
) |
491 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT
));
493 /* Initialize the texture offset to the start of the card texture heap */
494 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXOFFSET
] =
495 rmesa
->radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
497 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_BORDER_COLOR
] = 0;
498 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXCBLEND
] =
499 (RADEON_COLOR_ARG_A_ZERO
|
500 RADEON_COLOR_ARG_B_ZERO
|
501 RADEON_COLOR_ARG_C_CURRENT_COLOR
|
502 RADEON_BLEND_CTL_ADD
|
505 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TXABLEND
] =
506 (RADEON_ALPHA_ARG_A_ZERO
|
507 RADEON_ALPHA_ARG_B_ZERO
|
508 RADEON_ALPHA_ARG_C_CURRENT_ALPHA
|
509 RADEON_BLEND_CTL_ADD
|
512 rmesa
->hw
.tex
[i
].cmd
[TEX_PP_TFACTOR
] = 0;
514 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_FACES
] = 0;
515 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_0
] =
516 rmesa
->radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
517 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_1
] =
518 rmesa
->radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
519 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_2
] =
520 rmesa
->radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
521 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_3
] =
522 rmesa
->radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
523 rmesa
->hw
.cube
[i
].cmd
[CUBE_PP_CUBIC_OFFSET_4
] =
524 rmesa
->radeonScreen
->texOffset
[RADEON_LOCAL_TEX_HEAP
];
527 /* Can only add ST1 at the time of doing some multitex but can keep
528 * it after that. Errors if DIFFUSE is missing.
530 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] =
533 RADEON_TCL_VTX_PK_DIFFUSE
534 ); /* need to keep this uptodate */
536 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXSEL
] =
537 ( RADEON_TCL_COMPUTE_XYZW
|
538 (RADEON_TCL_TEX_INPUT_TEX_0
<< RADEON_TCL_TEX_0_OUTPUT_SHIFT
) |
539 (RADEON_TCL_TEX_INPUT_TEX_1
<< RADEON_TCL_TEX_1_OUTPUT_SHIFT
) |
540 (RADEON_TCL_TEX_INPUT_TEX_2
<< RADEON_TCL_TEX_2_OUTPUT_SHIFT
));
544 rmesa
->hw
.tcl
.cmd
[TCL_MATRIX_SELECT_0
] =
545 ((MODEL
<< RADEON_MODELVIEW_0_SHIFT
) |
546 (MODEL_IT
<< RADEON_IT_MODELVIEW_0_SHIFT
));
548 rmesa
->hw
.tcl
.cmd
[TCL_MATRIX_SELECT_1
] =
549 ((MODEL_PROJ
<< RADEON_MODELPROJECT_0_SHIFT
) |
550 (TEXMAT_0
<< RADEON_TEXMAT_0_SHIFT
) |
551 (TEXMAT_1
<< RADEON_TEXMAT_1_SHIFT
) |
552 (TEXMAT_2
<< RADEON_TEXMAT_2_SHIFT
));
554 rmesa
->hw
.tcl
.cmd
[TCL_UCP_VERT_BLEND_CTL
] =
555 (RADEON_UCP_IN_CLIP_SPACE
|
556 RADEON_CULL_FRONT_IS_CCW
);
558 rmesa
->hw
.tcl
.cmd
[TCL_TEXTURE_PROC_CTL
] = 0;
560 rmesa
->hw
.tcl
.cmd
[TCL_LIGHT_MODEL_CTL
] =
561 (RADEON_SPECULAR_LIGHTS
|
562 RADEON_DIFFUSE_SPECULAR_COMBINE
|
563 RADEON_LOCAL_LIGHT_VEC_GL
|
564 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_EMISSIVE_SOURCE_SHIFT
) |
565 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_AMBIENT_SOURCE_SHIFT
) |
566 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_DIFFUSE_SOURCE_SHIFT
) |
567 (RADEON_LM_SOURCE_STATE_MULT
<< RADEON_SPECULAR_SOURCE_SHIFT
));
569 for (i
= 0 ; i
< 8; i
++) {
570 struct gl_light
*l
= &ctx
->Light
.Light
[i
];
571 GLenum p
= GL_LIGHT0
+ i
;
572 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_RANGE_CUTOFF
]) = FLT_MAX
;
574 ctx
->Driver
.Lightfv( ctx
, p
, GL_AMBIENT
, l
->Ambient
);
575 ctx
->Driver
.Lightfv( ctx
, p
, GL_DIFFUSE
, l
->Diffuse
);
576 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPECULAR
, l
->Specular
);
577 ctx
->Driver
.Lightfv( ctx
, p
, GL_POSITION
, NULL
);
578 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_DIRECTION
, NULL
);
579 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_EXPONENT
, &l
->SpotExponent
);
580 ctx
->Driver
.Lightfv( ctx
, p
, GL_SPOT_CUTOFF
, &l
->SpotCutoff
);
581 ctx
->Driver
.Lightfv( ctx
, p
, GL_CONSTANT_ATTENUATION
,
582 &l
->ConstantAttenuation
);
583 ctx
->Driver
.Lightfv( ctx
, p
, GL_LINEAR_ATTENUATION
,
584 &l
->LinearAttenuation
);
585 ctx
->Driver
.Lightfv( ctx
, p
, GL_QUADRATIC_ATTENUATION
,
586 &l
->QuadraticAttenuation
);
587 *(float *)&(rmesa
->hw
.lit
[i
].cmd
[LIT_ATTEN_XXX
]) = 0.0;
590 ctx
->Driver
.LightModelfv( ctx
, GL_LIGHT_MODEL_AMBIENT
,
591 ctx
->Light
.Model
.Ambient
);
593 TNL_CONTEXT(ctx
)->Driver
.NotifyMaterialChange( ctx
);
595 for (i
= 0 ; i
< 6; i
++) {
596 ctx
->Driver
.ClipPlane( ctx
, GL_CLIP_PLANE0
+ i
, NULL
);
599 ctx
->Driver
.Fogfv( ctx
, GL_FOG_MODE
, NULL
);
600 ctx
->Driver
.Fogfv( ctx
, GL_FOG_DENSITY
, &ctx
->Fog
.Density
);
601 ctx
->Driver
.Fogfv( ctx
, GL_FOG_START
, &ctx
->Fog
.Start
);
602 ctx
->Driver
.Fogfv( ctx
, GL_FOG_END
, &ctx
->Fog
.End
);
603 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COLOR
, ctx
->Fog
.Color
);
604 ctx
->Driver
.Fogfv( ctx
, GL_FOG_COORDINATE_SOURCE_EXT
, NULL
);
606 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_CLIP_ADJ
] = IEEE_ONE
;
607 rmesa
->hw
.grd
.cmd
[GRD_VERT_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
608 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_CLIP_ADJ
] = IEEE_ONE
;
609 rmesa
->hw
.grd
.cmd
[GRD_HORZ_GUARD_DISCARD_ADJ
] = IEEE_ONE
;
611 rmesa
->hw
.eye
.cmd
[EYE_X
] = 0;
612 rmesa
->hw
.eye
.cmd
[EYE_Y
] = 0;
613 rmesa
->hw
.eye
.cmd
[EYE_Z
] = IEEE_ONE
;
614 rmesa
->hw
.eye
.cmd
[EYE_RESCALE_FACTOR
] = IEEE_ONE
;
616 rmesa
->hw
.all_dirty
= GL_TRUE
;