projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeon: move CB/ZB state init into emit code
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_state_init.c
1 /*
2 * Copyright 2000, 2001 VA Linux Systems Inc., Fremont, California.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Keith Whitwell <keith@tungstengraphics.com>
28 */
29
30 #include "main/glheader.h"
31 #include "main/imports.h"
32 #include "main/api_arrayelt.h"
33
34 #include "swrast/swrast.h"
35 #include "vbo/vbo.h"
36 #include "tnl/tnl.h"
37 #include "tnl/t_pipeline.h"
38 #include "swrast_setup/swrast_setup.h"
39
40 #include "radeon_context.h"
41 #include "radeon_mipmap_tree.h"
42 #include "radeon_ioctl.h"
43 #include "radeon_state.h"
44 #include "radeon_tcl.h"
45 #include "radeon_tex.h"
46 #include "radeon_swtcl.h"
47
48 #include "../r200/r200_reg.h"
49
50 #include "xmlpool.h"
51
52 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
53 * 1.3 cmdbuffers allow all previous state to be updated as well as
54 * the tcl scalar and vector areas.
55 */
56 static struct {
57 int start;
58 int len;
59 const char *name;
60 } packet[RADEON_MAX_STATE_PACKETS] = {
61 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
62 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
63 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
64 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
65 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
66 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
67 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
68 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
69 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
70 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
71 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
72 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
73 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
74 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
75 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
76 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
77 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
78 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
79 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
80 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
81 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
82 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
83 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
84 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
85 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
86 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
87 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
88 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
89 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
90 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
91 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
92 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
93 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
94 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
95 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
96 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
97 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
98 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
99 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
100 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
101 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
102 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
103 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
104 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
105 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
106 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
107 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
108 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
109 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
110 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
111 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
112 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
113 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
114 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
115 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
116 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
117 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
118 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
119 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
120 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
121 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
122 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
123 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
124 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
125 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
126 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
127 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
128 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
129 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
130 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
131 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
132 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
133 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
134 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
135 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
136 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
137 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
138 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
139 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
140 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
141 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
142 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
143 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
144 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
145 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
146 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
147 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
148 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
149 {R200_PP_TXCBLEND_8, 32, "R200_PP_AFS_0"}, /* 85 */
150 {R200_PP_TXCBLEND_0, 32, "R200_PP_AFS_1"},
151 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
152 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
153 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
154 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
155 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
156 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
157 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
158 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
159 };
160
161 /* =============================================================
162 * State initialization
163 */
164
165 void radeonPrintDirty( r100ContextPtr rmesa, const char *msg )
166 {
167 struct radeon_state_atom *l;
168
169 fprintf(stderr, msg);
170 fprintf(stderr, ": ");
171
172 foreach(l, &rmesa->radeon.hw.atomlist) {
173 if (l->dirty || rmesa->radeon.hw.all_dirty)
174 fprintf(stderr, "%s, ", l->name);
175 }
176
177 fprintf(stderr, "\n");
178 }
179
180 static int cmdpkt( r100ContextPtr rmesa, int id )
181 {
182 drm_radeon_cmd_header_t h;
183
184 if (rmesa->radeon.radeonScreen->kernel_mm) {
185 return CP_PACKET0(packet[id].start, packet[id].len - 1);
186 } else {
187 h.i = 0;
188 h.packet.cmd_type = RADEON_CMD_PACKET;
189 h.packet.packet_id = id;
190 }
191 return h.i;
192 }
193
194 static int cmdvec( int offset, int stride, int count )
195 {
196 drm_radeon_cmd_header_t h;
197 h.i = 0;
198 h.vectors.cmd_type = RADEON_CMD_VECTORS;
199 h.vectors.offset = offset;
200 h.vectors.stride = stride;
201 h.vectors.count = count;
202 return h.i;
203 }
204
205 static int cmdscl( int offset, int stride, int count )
206 {
207 drm_radeon_cmd_header_t h;
208 h.i = 0;
209 h.scalars.cmd_type = RADEON_CMD_SCALARS;
210 h.scalars.offset = offset;
211 h.scalars.stride = stride;
212 h.scalars.count = count;
213 return h.i;
214 }
215
216 #define CHECK( NM, FLAG ) \
217 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
218 { \
219 return FLAG ? atom->cmd_size : 0; \
220 }
221
222 #define TCL_CHECK( NM, FLAG ) \
223 static int check_##NM( GLcontext *ctx, struct radeon_state_atom *atom ) \
224 { \
225 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
226 return (!rmesa->radeon.TclFallback && (FLAG)) ? atom->cmd_size : 0; \
227 }
228
229
230 CHECK( always, GL_TRUE )
231 CHECK( never, GL_FALSE )
232 CHECK( tex0, ctx->Texture.Unit[0]._ReallyEnabled )
233 CHECK( tex1, ctx->Texture.Unit[1]._ReallyEnabled )
234 /* need this for the cubic_map on disabled unit 2 bug, maybe r100 only? */
235 CHECK( tex2, ctx->Texture._EnabledUnits )
236 CHECK( cube0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_CUBE_BIT))
237 CHECK( cube1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_CUBE_BIT))
238 CHECK( cube2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_CUBE_BIT))
239 CHECK( fog, ctx->Fog.Enabled )
240 TCL_CHECK( tcl, GL_TRUE )
241 TCL_CHECK( tcl_tex0, ctx->Texture.Unit[0]._ReallyEnabled )
242 TCL_CHECK( tcl_tex1, ctx->Texture.Unit[1]._ReallyEnabled )
243 TCL_CHECK( tcl_tex2, ctx->Texture.Unit[2]._ReallyEnabled )
244 TCL_CHECK( tcl_lighting, ctx->Light.Enabled )
245 TCL_CHECK( tcl_eyespace_or_lighting, ctx->_NeedEyeCoords || ctx->Light.Enabled )
246 TCL_CHECK( tcl_lit0, ctx->Light.Enabled && ctx->Light.Light[0].Enabled )
247 TCL_CHECK( tcl_lit1, ctx->Light.Enabled && ctx->Light.Light[1].Enabled )
248 TCL_CHECK( tcl_lit2, ctx->Light.Enabled && ctx->Light.Light[2].Enabled )
249 TCL_CHECK( tcl_lit3, ctx->Light.Enabled && ctx->Light.Light[3].Enabled )
250 TCL_CHECK( tcl_lit4, ctx->Light.Enabled && ctx->Light.Light[4].Enabled )
251 TCL_CHECK( tcl_lit5, ctx->Light.Enabled && ctx->Light.Light[5].Enabled )
252 TCL_CHECK( tcl_lit6, ctx->Light.Enabled && ctx->Light.Light[6].Enabled )
253 TCL_CHECK( tcl_lit7, ctx->Light.Enabled && ctx->Light.Light[7].Enabled )
254 TCL_CHECK( tcl_ucp0, (ctx->Transform.ClipPlanesEnabled & 0x1) )
255 TCL_CHECK( tcl_ucp1, (ctx->Transform.ClipPlanesEnabled & 0x2) )
256 TCL_CHECK( tcl_ucp2, (ctx->Transform.ClipPlanesEnabled & 0x4) )
257 TCL_CHECK( tcl_ucp3, (ctx->Transform.ClipPlanesEnabled & 0x8) )
258 TCL_CHECK( tcl_ucp4, (ctx->Transform.ClipPlanesEnabled & 0x10) )
259 TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) )
260 TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || ctx->Fog.Enabled )
261
262 CHECK( txr0, (ctx->Texture.Unit[0]._ReallyEnabled & TEXTURE_RECT_BIT))
263 CHECK( txr1, (ctx->Texture.Unit[1]._ReallyEnabled & TEXTURE_RECT_BIT))
264 CHECK( txr2, (ctx->Texture.Unit[2]._ReallyEnabled & TEXTURE_RECT_BIT))
265
266 #define OUT_VEC(hdr, data) do { \
267 drm_radeon_cmd_header_t h; \
268 h.i = hdr; \
269 OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \
270 OUT_BATCH(0); \
271 OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \
272 OUT_BATCH(h.vectors.offset | (h.vectors.stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \
273 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, h.vectors.count - 1)); \
274 OUT_BATCH_TABLE((data), h.vectors.count); \
275 } while(0)
276
277 #define OUT_SCL(hdr, data) do { \
278 drm_radeon_cmd_header_t h; \
279 h.i = hdr; \
280 OUT_BATCH(CP_PACKET0(R200_SE_TCL_SCALAR_INDX_REG, 0)); \
281 OUT_BATCH((h.scalars.offset) | (h.scalars.stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT)); \
282 OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_SCALAR_DATA_REG, h.scalars.count - 1)); \
283 OUT_BATCH_TABLE((data), h.scalars.count); \
284 } while(0)
285
286 static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom)
287 {
288 r100ContextPtr r100 = R100_CONTEXT(ctx);
289 BATCH_LOCALS(&r100->radeon);
290 uint32_t dwords = atom->cmd_size;
291
292 BEGIN_BATCH_NO_AUTOSTATE(dwords);
293 OUT_SCL(atom->cmd[0], atom->cmd+1);
294 END_BATCH();
295 }
296
297
298 static void vec_emit(GLcontext *ctx, struct radeon_state_atom *atom)
299 {
300 r100ContextPtr r100 = R100_CONTEXT(ctx);
301 BATCH_LOCALS(&r100->radeon);
302 uint32_t dwords = atom->cmd_size;
303
304 BEGIN_BATCH_NO_AUTOSTATE(dwords);
305 OUT_VEC(atom->cmd[0], atom->cmd+1);
306 END_BATCH();
307 }
308
309 static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
310 {
311 r100ContextPtr r100 = R100_CONTEXT(ctx);
312 BATCH_LOCALS(&r100->radeon);
313 struct radeon_renderbuffer *rrb;
314 uint32_t cbpitch;
315 uint32_t zbpitch, depth_fmt;
316 uint32_t dwords = atom->cmd_size;
317
318 /* output the first 7 bytes of context */
319 BEGIN_BATCH_NO_AUTOSTATE(dwords + 4);
320 OUT_BATCH_TABLE(atom->cmd, 5);
321
322 rrb = radeon_get_depthbuffer(&r100->radeon);
323 if (!rrb) {
324 OUT_BATCH(0);
325 OUT_BATCH(0);
326 } else {
327 zbpitch = (rrb->pitch / rrb->cpp);
328 if (r100->using_hyperz)
329 zbpitch |= RADEON_DEPTH_HYPERZ;
330
331 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
332 OUT_BATCH(zbpitch);
333 if (rrb->cpp == 4)
334 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
335 else
336 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
337 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
338 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
339 }
340
341 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
342 OUT_BATCH(atom->cmd[CTX_CMD_1]);
343 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
344
345 rrb = radeon_get_colorbuffer(&r100->radeon);
346 if (!rrb || !rrb->bo) {
347 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
348 OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
349 } else {
350 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
351 if (rrb->cpp == 4)
352 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
353 else
354 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
355
356 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
357 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
358 }
359
360 OUT_BATCH(atom->cmd[CTX_CMD_2]);
361
362 if (!rrb || !rrb->bo) {
363 OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
364 } else {
365 cbpitch = (rrb->pitch / rrb->cpp);
366 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
367 cbpitch |= RADEON_COLOR_TILE_ENABLE;
368 OUT_BATCH(cbpitch);
369 }
370
371 END_BATCH();
372 }
373
374 static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
375 {
376 r100ContextPtr r100 = R100_CONTEXT(ctx);
377 BATCH_LOCALS(&r100->radeon);
378 struct radeon_renderbuffer *rrb, *drb;
379 uint32_t cbpitch = 0;
380 uint32_t zbpitch = 0;
381 uint32_t dwords = atom->cmd_size;
382 uint32_t depth_fmt;
383
384 rrb = radeon_get_colorbuffer(&r100->radeon);
385 if (!rrb || !rrb->bo) {
386 fprintf(stderr, "no rrb\n");
387 return;
388 }
389
390 atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
391 if (rrb->cpp == 4)
392 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
393 else
394 atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
395
396 cbpitch = (rrb->pitch / rrb->cpp);
397 if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
398 cbpitch |= R200_COLOR_TILE_ENABLE;
399
400 drb = radeon_get_depthbuffer(&r100->radeon);
401 if (drb) {
402 zbpitch = (drb->pitch / drb->cpp);
403 if (drb->cpp == 4)
404 depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
405 else
406 depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
407 atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
408 atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
409
410 }
411 /* output the first 7 bytes of context */
412 BEGIN_BATCH_NO_AUTOSTATE(dwords);
413
414 /* In the CS case we need to split this up */
415 OUT_BATCH(CP_PACKET0(packet[0].start, 3));
416 OUT_BATCH_TABLE((atom->cmd + 1), 4);
417
418 if (drb) {
419 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHOFFSET, 0));
420 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
421
422 OUT_BATCH(CP_PACKET0(RADEON_RB3D_DEPTHPITCH, 0));
423 OUT_BATCH(zbpitch);
424 }
425
426 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZSTENCILCNTL, 0));
427 OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
428 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 1));
429 OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
430 OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
431
432
433 if (rrb) {
434 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLOROFFSET, 0));
435 OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
436 }
437
438 if (rrb) {
439 cbpitch = (rrb->pitch / rrb->cpp);
440 OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
441 OUT_BATCH(cbpitch);
442 }
443
444 // if (atom->cmd_size == CTX_STATE_SIZE_NEWDRM) {
445 // OUT_BATCH_TABLE((atom->cmd + 14), 4);
446 // }
447
448 END_BATCH();
449 }
450
451 static void cube_emit(GLcontext *ctx, struct radeon_state_atom *atom)
452 {
453 r100ContextPtr r100 = R100_CONTEXT(ctx);
454 BATCH_LOCALS(&r100->radeon);
455 uint32_t dwords = atom->cmd_size;
456 int i = atom->idx, j;
457 radeonTexObj *t = r100->state.texture.unit[i].texobj;
458 radeon_mipmap_level *lvl;
459
460 if (!(ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT))
461 return;
462
463 if (!t)
464 return;
465
466 if (!t->mt)
467 return;
468
469 BEGIN_BATCH_NO_AUTOSTATE(dwords + 10);
470 OUT_BATCH_TABLE(atom->cmd, 3);
471 lvl = &t->mt->levels[0];
472 for (j = 0; j < 5; j++) {
473 OUT_BATCH_RELOC(lvl->faces[j].offset, t->mt->bo, lvl->faces[j].offset,
474 RADEON_GEM_DOMAIN_VRAM, 0, 0);
475 }
476 END_BATCH();
477 }
478
479 static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
480 {
481 r100ContextPtr r100 = R100_CONTEXT(ctx);
482 BATCH_LOCALS(&r100->radeon);
483 uint32_t dwords = atom->cmd_size;
484 int i = atom->idx;
485 radeonTexObj *t = r100->state.texture.unit[i].texobj;
486 radeon_mipmap_level *lvl;
487
488 if (t && t->mt && !t->image_override)
489 dwords += 2;
490 BEGIN_BATCH_NO_AUTOSTATE(dwords);
491 OUT_BATCH_TABLE(atom->cmd, 3);
492 if (t && t->mt && !t->image_override) {
493 if ((ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_CUBE_BIT)) {
494 lvl = &t->mt->levels[0];
495 OUT_BATCH_RELOC(lvl->faces[5].offset, t->mt->bo, lvl->faces[5].offset,
496 RADEON_GEM_DOMAIN_VRAM, 0, 0);
497 } else {
498 OUT_BATCH_RELOC(t->tile_bits, t->mt->bo, 0,
499 RADEON_GEM_DOMAIN_VRAM, 0, 0);
500 }
501 } else if (!t) {
502 /* workaround for old CS mechanism */
503 OUT_BATCH(r100->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP]);
504 // OUT_BATCH(r100->radeon.radeonScreen);
505 } else if (t->image_override)
506 OUT_BATCH(t->override_offset);
507
508 OUT_BATCH_TABLE((atom->cmd+4), 5);
509 END_BATCH();
510 }
511
512 /* Initialize the context's hardware state.
513 */
514 void radeonInitState( r100ContextPtr rmesa )
515 {
516 GLcontext *ctx = rmesa->radeon.glCtx;
517 GLuint i;
518
519 rmesa->radeon.state.color.clear = 0x00000000;
520
521 switch ( ctx->Visual.depthBits ) {
522 case 16:
523 rmesa->radeon.state.depth.clear = 0x0000ffff;
524 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
525 rmesa->radeon.state.stencil.clear = 0x00000000;
526 break;
527 case 24:
528 rmesa->radeon.state.depth.clear = 0x00ffffff;
529 rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
530 rmesa->radeon.state.stencil.clear = 0xffff0000;
531 break;
532 default:
533 fprintf( stderr, "Error: Unsupported depth %d... exiting\n",
534 ctx->Visual.depthBits );
535 exit( -1 );
536 }
537
538 /* Only have hw stencil when depth buffer is 24 bits deep */
539 rmesa->radeon.state.stencil.hwBuffer = ( ctx->Visual.stencilBits > 0 &&
540 ctx->Visual.depthBits == 24 );
541
542 rmesa->radeon.Fallback = 0;
543
544
545 rmesa->radeon.hw.max_state_size = 0;
546
547 #define ALLOC_STATE_IDX( ATOM, CHK, SZ, NM, FLAG, IDX ) \
548 do { \
549 rmesa->hw.ATOM.cmd_size = SZ; \
550 rmesa->hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
551 rmesa->hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
552 rmesa->hw.ATOM.name = NM; \
553 rmesa->hw.ATOM.is_tcl = FLAG; \
554 rmesa->hw.ATOM.check = check_##CHK; \
555 rmesa->hw.ATOM.dirty = GL_TRUE; \
556 rmesa->hw.ATOM.idx = IDX; \
557 rmesa->radeon.hw.max_state_size += SZ * sizeof(int); \
558 } while (0)
559
560 #define ALLOC_STATE( ATOM, CHK, SZ, NM, FLAG ) \
561 ALLOC_STATE_IDX(ATOM, CHK, SZ, NM, FLAG, 0)
562
563 /* Allocate state buffers:
564 */
565 ALLOC_STATE( ctx, always, CTX_STATE_SIZE, "CTX/context", 0 );
566 if (rmesa->radeon.radeonScreen->kernel_mm)
567 rmesa->hw.ctx.emit = ctx_emit_cs;
568 else
569 rmesa->hw.ctx.emit = ctx_emit;
570 ALLOC_STATE( lin, always, LIN_STATE_SIZE, "LIN/line", 0 );
571 ALLOC_STATE( msk, always, MSK_STATE_SIZE, "MSK/mask", 0 );
572 ALLOC_STATE( vpt, always, VPT_STATE_SIZE, "VPT/viewport", 0 );
573 ALLOC_STATE( set, always, SET_STATE_SIZE, "SET/setup", 0 );
574 ALLOC_STATE( msc, always, MSC_STATE_SIZE, "MSC/misc", 0 );
575 ALLOC_STATE( zbs, always, ZBS_STATE_SIZE, "ZBS/zbias", 0 );
576 ALLOC_STATE( tcl, always, TCL_STATE_SIZE, "TCL/tcl", 1 );
577 ALLOC_STATE( mtl, tcl_lighting, MTL_STATE_SIZE, "MTL/material", 1 );
578 ALLOC_STATE( grd, always, GRD_STATE_SIZE, "GRD/guard-band", 1 );
579 ALLOC_STATE( fog, fog, FOG_STATE_SIZE, "FOG/fog", 1 );
580 ALLOC_STATE( glt, tcl_lighting, GLT_STATE_SIZE, "GLT/light-global", 1 );
581 ALLOC_STATE( eye, tcl_lighting, EYE_STATE_SIZE, "EYE/eye-vector", 1 );
582 ALLOC_STATE_IDX( tex[0], tex0, TEX_STATE_SIZE, "TEX/tex-0", 0, 0);
583 ALLOC_STATE_IDX( tex[1], tex1, TEX_STATE_SIZE, "TEX/tex-1", 0, 1);
584 ALLOC_STATE_IDX( tex[2], tex2, TEX_STATE_SIZE, "TEX/tex-2", 0, 2 );
585
586 for (i = 0; i < 3; i++)
587 rmesa->hw.tex[i].emit = tex_emit;
588 if (rmesa->radeon.radeonScreen->drmSupportsCubeMapsR100)
589 {
590 ALLOC_STATE_IDX( cube[0], cube0, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
591 ALLOC_STATE_IDX( cube[1], cube1, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
592 ALLOC_STATE_IDX( cube[2], cube2, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
593 for (i = 0; i < 3; i++)
594 rmesa->hw.cube[i].emit = cube_emit;
595 }
596 else
597 {
598 ALLOC_STATE_IDX( cube[0], never, CUBE_STATE_SIZE, "CUBE/cube-0", 0, 0 );
599 ALLOC_STATE_IDX( cube[1], never, CUBE_STATE_SIZE, "CUBE/cube-1", 0, 1 );
600 ALLOC_STATE_IDX( cube[2], never, CUBE_STATE_SIZE, "CUBE/cube-2", 0, 2 );
601 }
602 ALLOC_STATE( mat[0], tcl, MAT_STATE_SIZE, "MAT/modelproject", 1 );
603 ALLOC_STATE( mat[1], tcl_eyespace_or_fog, MAT_STATE_SIZE, "MAT/modelview", 1 );
604 ALLOC_STATE( mat[2], tcl_eyespace_or_lighting, MAT_STATE_SIZE, "MAT/it-modelview", 1 );
605 ALLOC_STATE( mat[3], tcl_tex0, MAT_STATE_SIZE, "MAT/texmat0", 1 );
606 ALLOC_STATE( mat[4], tcl_tex1, MAT_STATE_SIZE, "MAT/texmat1", 1 );
607 ALLOC_STATE( mat[5], tcl_tex2, MAT_STATE_SIZE, "MAT/texmat2", 1 );
608 ALLOC_STATE( ucp[0], tcl_ucp0, UCP_STATE_SIZE, "UCP/userclip-0", 1 );
609 ALLOC_STATE( ucp[1], tcl_ucp1, UCP_STATE_SIZE, "UCP/userclip-1", 1 );
610 ALLOC_STATE( ucp[2], tcl_ucp2, UCP_STATE_SIZE, "UCP/userclip-2", 1 );
611 ALLOC_STATE( ucp[3], tcl_ucp3, UCP_STATE_SIZE, "UCP/userclip-3", 1 );
612 ALLOC_STATE( ucp[4], tcl_ucp4, UCP_STATE_SIZE, "UCP/userclip-4", 1 );
613 ALLOC_STATE( ucp[5], tcl_ucp5, UCP_STATE_SIZE, "UCP/userclip-5", 1 );
614 ALLOC_STATE( lit[0], tcl_lit0, LIT_STATE_SIZE, "LIT/light-0", 1 );
615 ALLOC_STATE( lit[1], tcl_lit1, LIT_STATE_SIZE, "LIT/light-1", 1 );
616 ALLOC_STATE( lit[2], tcl_lit2, LIT_STATE_SIZE, "LIT/light-2", 1 );
617 ALLOC_STATE( lit[3], tcl_lit3, LIT_STATE_SIZE, "LIT/light-3", 1 );
618 ALLOC_STATE( lit[4], tcl_lit4, LIT_STATE_SIZE, "LIT/light-4", 1 );
619 ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 );
620 ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 );
621 ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 );
622 ALLOC_STATE_IDX( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0, 0 );
623 ALLOC_STATE_IDX( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0, 1 );
624 ALLOC_STATE_IDX( txr[2], txr2, TXR_STATE_SIZE, "TXR/txr-2", 0, 2 );
625
626 radeonSetUpAtomList( rmesa );
627
628 /* Fill in the packet headers:
629 */
630 rmesa->hw.ctx.cmd[CTX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_MISC);
631 rmesa->hw.ctx.cmd[CTX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CNTL);
632 rmesa->hw.ctx.cmd[CTX_CMD_2] = cmdpkt(rmesa, RADEON_EMIT_RB3D_COLORPITCH);
633 rmesa->hw.lin.cmd[LIN_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_LINE_PATTERN);
634 rmesa->hw.lin.cmd[LIN_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_LINE_WIDTH);
635 rmesa->hw.msk.cmd[MSK_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RB3D_STENCILREFMASK);
636 rmesa->hw.vpt.cmd[VPT_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_VPORT_XSCALE);
637 rmesa->hw.set.cmd[SET_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL);
638 rmesa->hw.set.cmd[SET_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_SE_CNTL_STATUS);
639 rmesa->hw.msc.cmd[MSC_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_RE_MISC);
640 rmesa->hw.tex[0].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_0);
641 rmesa->hw.tex[0].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_0);
642 rmesa->hw.tex[1].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_1);
643 rmesa->hw.tex[1].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_1);
644 rmesa->hw.tex[2].cmd[TEX_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TXFILTER_2);
645 rmesa->hw.tex[2].cmd[TEX_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_BORDER_COLOR_2);
646 rmesa->hw.cube[0].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_0);
647 rmesa->hw.cube[0].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T0);
648 rmesa->hw.cube[1].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_1);
649 rmesa->hw.cube[1].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T1);
650 rmesa->hw.cube[2].cmd[CUBE_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_FACES_2);
651 rmesa->hw.cube[2].cmd[CUBE_CMD_1] = cmdpkt(rmesa, RADEON_EMIT_PP_CUBIC_OFFSETS_T2);
652 rmesa->hw.zbs.cmd[ZBS_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_ZBIAS_FACTOR);
653 rmesa->hw.tcl.cmd[TCL_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT);
654 rmesa->hw.mtl.cmd[MTL_CMD_0] =
655 cmdpkt(rmesa, RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED);
656 rmesa->hw.txr[0].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_0);
657 rmesa->hw.txr[1].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_1);
658 rmesa->hw.txr[2].cmd[TXR_CMD_0] = cmdpkt(rmesa, RADEON_EMIT_PP_TEX_SIZE_2);
659 rmesa->hw.grd.cmd[GRD_CMD_0] =
660 cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 );
661 rmesa->hw.fog.cmd[FOG_CMD_0] =
662 cmdvec( RADEON_VS_FOG_PARAM_ADDR, 1, 4 );
663 rmesa->hw.glt.cmd[GLT_CMD_0] =
664 cmdvec( RADEON_VS_GLOBAL_AMBIENT_ADDR, 1, 4 );
665 rmesa->hw.eye.cmd[EYE_CMD_0] =
666 cmdvec( RADEON_VS_EYE_VECTOR_ADDR, 1, 4 );
667
668 for (i = 0 ; i < 6; i++) {
669 rmesa->hw.mat[i].cmd[MAT_CMD_0] =
670 cmdvec( RADEON_VS_MATRIX_0_ADDR + i*4, 1, 16);
671 }
672
673 for (i = 0 ; i < 8; i++) {
674 rmesa->hw.lit[i].cmd[LIT_CMD_0] =
675 cmdvec( RADEON_VS_LIGHT_AMBIENT_ADDR + i, 8, 24 );
676 rmesa->hw.lit[i].cmd[LIT_CMD_1] =
677 cmdscl( RADEON_SS_LIGHT_DCD_ADDR + i, 8, 6 );
678 }
679
680 for (i = 0 ; i < 6; i++) {
681 rmesa->hw.ucp[i].cmd[UCP_CMD_0] =
682 cmdvec( RADEON_VS_UCP_ADDR + i, 1, 4 );
683 }
684
685 rmesa->last_ReallyEnabled = -1;
686
687 /* Initial Harware state:
688 */
689 rmesa->hw.ctx.cmd[CTX_PP_MISC] = (RADEON_ALPHA_TEST_PASS |
690 RADEON_CHROMA_FUNC_FAIL |
691 RADEON_CHROMA_KEY_NEAREST |
692 RADEON_SHADOW_FUNC_EQUAL |
693 RADEON_SHADOW_PASS_1 /*|
694 RADEON_RIGHT_HAND_CUBE_OGL */);
695
696 rmesa->hw.ctx.cmd[CTX_PP_FOG_COLOR] = (RADEON_FOG_VERTEX |
697 /* this bit unused for vertex fog */
698 RADEON_FOG_USE_DEPTH);
699
700 rmesa->hw.ctx.cmd[CTX_RE_SOLID_COLOR] = 0x00000000;
701
702 rmesa->hw.ctx.cmd[CTX_RB3D_BLENDCNTL] = (RADEON_COMB_FCN_ADD_CLAMP |
703 RADEON_SRC_BLEND_GL_ONE |
704 RADEON_DST_BLEND_GL_ZERO );
705
706 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
707 RADEON_STENCIL_TEST_ALWAYS |
708 RADEON_STENCIL_FAIL_KEEP |
709 RADEON_STENCIL_ZPASS_KEEP |
710 RADEON_STENCIL_ZFAIL_KEEP |
711 RADEON_Z_WRITE_ENABLE);
712
713 if (rmesa->using_hyperz) {
714 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_COMPRESSION_ENABLE |
715 RADEON_Z_DECOMPRESSION_ENABLE;
716 if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
717 /* works for q3, but slight rendering errors with glxgears ? */
718 /* rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_Z_HIERARCHY_ENABLE;*/
719 /* need this otherwise get lots of lockups with q3 ??? */
720 rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] |= RADEON_FORCE_Z_DIRTY;
721 }
722 }
723
724 rmesa->hw.ctx.cmd[CTX_PP_CNTL] = (RADEON_SCISSOR_ENABLE |
725 RADEON_ANTI_ALIAS_NONE);
726
727 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
728 RADEON_ZBLOCK16);
729
730 switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
731 case DRI_CONF_DITHER_XERRORDIFFRESET:
732 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT;
733 break;
734 case DRI_CONF_DITHER_ORDERED:
735 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE;
736 break;
737 }
738 if ( driQueryOptioni( &rmesa->radeon.optionCache, "round_mode" ) ==
739 DRI_CONF_ROUND_ROUND )
740 rmesa->radeon.state.color.roundEnable = RADEON_ROUND_ENABLE;
741 else
742 rmesa->radeon.state.color.roundEnable = 0;
743 if ( driQueryOptioni (&rmesa->radeon.optionCache, "color_reduction" ) ==
744 DRI_CONF_COLOR_REDUCTION_DITHER )
745 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE;
746 else
747 rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
748
749
750 rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
751 RADEON_BFACE_SOLID |
752 RADEON_FFACE_SOLID |
753 /* RADEON_BADVTX_CULL_DISABLE | */
754 RADEON_FLAT_SHADE_VTX_LAST |
755 RADEON_DIFFUSE_SHADE_GOURAUD |
756 RADEON_ALPHA_SHADE_GOURAUD |
757 RADEON_SPECULAR_SHADE_GOURAUD |
758 RADEON_FOG_SHADE_GOURAUD |
759 RADEON_VPORT_XY_XFORM_ENABLE |
760 RADEON_VPORT_Z_XFORM_ENABLE |
761 RADEON_VTX_PIX_CENTER_OGL |
762 RADEON_ROUND_MODE_TRUNC |
763 RADEON_ROUND_PREC_8TH_PIX);
764
765 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] =
766 #ifdef MESA_BIG_ENDIAN
767 RADEON_VC_32BIT_SWAP;
768 #else
769 RADEON_VC_NO_SWAP;
770 #endif
771
772 if (!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
773 rmesa->hw.set.cmd[SET_SE_CNTL_STATUS] |= RADEON_TCL_BYPASS;
774 }
775
776 rmesa->hw.set.cmd[SET_SE_COORDFMT] = (
777 RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
778 RADEON_TEX1_W_ROUTING_USE_Q1);
779
780
781 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] = ((1 << 16) | 0xffff);
782
783 rmesa->hw.lin.cmd[LIN_RE_LINE_STATE] =
784 ((0 << RADEON_LINE_CURRENT_PTR_SHIFT) |
785 (1 << RADEON_LINE_CURRENT_COUNT_SHIFT));
786
787 rmesa->hw.lin.cmd[LIN_SE_LINE_WIDTH] = (1 << 4);
788
789 rmesa->hw.msk.cmd[MSK_RB3D_STENCILREFMASK] =
790 ((0x00 << RADEON_STENCIL_REF_SHIFT) |
791 (0xff << RADEON_STENCIL_MASK_SHIFT) |
792 (0xff << RADEON_STENCIL_WRITEMASK_SHIFT));
793
794 rmesa->hw.msk.cmd[MSK_RB3D_ROPCNTL] = RADEON_ROP_COPY;
795 rmesa->hw.msk.cmd[MSK_RB3D_PLANEMASK] = 0xffffffff;
796
797 rmesa->hw.msc.cmd[MSC_RE_MISC] =
798 ((0 << RADEON_STIPPLE_X_OFFSET_SHIFT) |
799 (0 << RADEON_STIPPLE_Y_OFFSET_SHIFT) |
800 RADEON_STIPPLE_BIG_BIT_ORDER);
801
802 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XSCALE] = 0x00000000;
803 rmesa->hw.vpt.cmd[VPT_SE_VPORT_XOFFSET] = 0x00000000;
804 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YSCALE] = 0x00000000;
805 rmesa->hw.vpt.cmd[VPT_SE_VPORT_YOFFSET] = 0x00000000;
806 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZSCALE] = 0x00000000;
807 rmesa->hw.vpt.cmd[VPT_SE_VPORT_ZOFFSET] = 0x00000000;
808
809 for ( i = 0 ; i < ctx->Const.MaxTextureUnits ; i++ ) {
810 rmesa->hw.tex[i].cmd[TEX_PP_TXFILTER] = RADEON_BORDER_MODE_OGL;
811 rmesa->hw.tex[i].cmd[TEX_PP_TXFORMAT] =
812 (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
813 RADEON_TXFORMAT_PERSPECTIVE_ENABLE |
814 (i << 24) | /* This is one of RADEON_TXFORMAT_ST_ROUTE_STQ[012] */
815 (2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
816 (2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
817
818 /* Initialize the texture offset to the start of the card texture heap */
819 // rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] =
820 // rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
821
822 rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0;
823 rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] =
824 (RADEON_COLOR_ARG_A_ZERO |
825 RADEON_COLOR_ARG_B_ZERO |
826 RADEON_COLOR_ARG_C_CURRENT_COLOR |
827 RADEON_BLEND_CTL_ADD |
828 RADEON_SCALE_1X |
829 RADEON_CLAMP_TX);
830 rmesa->hw.tex[i].cmd[TEX_PP_TXABLEND] =
831 (RADEON_ALPHA_ARG_A_ZERO |
832 RADEON_ALPHA_ARG_B_ZERO |
833 RADEON_ALPHA_ARG_C_CURRENT_ALPHA |
834 RADEON_BLEND_CTL_ADD |
835 RADEON_SCALE_1X |
836 RADEON_CLAMP_TX);
837 rmesa->hw.tex[i].cmd[TEX_PP_TFACTOR] = 0;
838
839 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_FACES] = 0;
840 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_0] =
841 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
842 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_1] =
843 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
844 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_2] =
845 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
846 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_3] =
847 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
848 rmesa->hw.cube[i].cmd[CUBE_PP_CUBIC_OFFSET_4] =
849 rmesa->radeon.radeonScreen->texOffset[RADEON_LOCAL_TEX_HEAP];
850 }
851
852 /* Can only add ST1 at the time of doing some multitex but can keep
853 * it after that. Errors if DIFFUSE is missing.
854 */
855 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] =
856 (RADEON_TCL_VTX_Z0 |
857 RADEON_TCL_VTX_W0 |
858 RADEON_TCL_VTX_PK_DIFFUSE
859 ); /* need to keep this uptodate */
860
861 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXSEL] =
862 ( RADEON_TCL_COMPUTE_XYZW |
863 (RADEON_TCL_TEX_INPUT_TEX_0 << RADEON_TCL_TEX_0_OUTPUT_SHIFT) |
864 (RADEON_TCL_TEX_INPUT_TEX_1 << RADEON_TCL_TEX_1_OUTPUT_SHIFT) |
865 (RADEON_TCL_TEX_INPUT_TEX_2 << RADEON_TCL_TEX_2_OUTPUT_SHIFT));
866
867
868 /* XXX */
869 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_0] =
870 ((MODEL << RADEON_MODELVIEW_0_SHIFT) |
871 (MODEL_IT << RADEON_IT_MODELVIEW_0_SHIFT));
872
873 rmesa->hw.tcl.cmd[TCL_MATRIX_SELECT_1] =
874 ((MODEL_PROJ << RADEON_MODELPROJECT_0_SHIFT) |
875 (TEXMAT_0 << RADEON_TEXMAT_0_SHIFT) |
876 (TEXMAT_1 << RADEON_TEXMAT_1_SHIFT) |
877 (TEXMAT_2 << RADEON_TEXMAT_2_SHIFT));
878
879 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] =
880 (RADEON_UCP_IN_CLIP_SPACE |
881 RADEON_CULL_FRONT_IS_CCW);
882
883 rmesa->hw.tcl.cmd[TCL_TEXTURE_PROC_CTL] = 0;
884
885 rmesa->hw.tcl.cmd[TCL_LIGHT_MODEL_CTL] =
886 (RADEON_SPECULAR_LIGHTS |
887 RADEON_DIFFUSE_SPECULAR_COMBINE |
888 RADEON_LOCAL_LIGHT_VEC_GL |
889 (RADEON_LM_SOURCE_STATE_MULT << RADEON_EMISSIVE_SOURCE_SHIFT) |
890 (RADEON_LM_SOURCE_STATE_MULT << RADEON_AMBIENT_SOURCE_SHIFT) |
891 (RADEON_LM_SOURCE_STATE_MULT << RADEON_DIFFUSE_SOURCE_SHIFT) |
892 (RADEON_LM_SOURCE_STATE_MULT << RADEON_SPECULAR_SOURCE_SHIFT));
893
894 for (i = 0 ; i < 8; i++) {
895 struct gl_light *l = &ctx->Light.Light[i];
896 GLenum p = GL_LIGHT0 + i;
897 *(float *)&(rmesa->hw.lit[i].cmd[LIT_RANGE_CUTOFF]) = FLT_MAX;
898
899 ctx->Driver.Lightfv( ctx, p, GL_AMBIENT, l->Ambient );
900 ctx->Driver.Lightfv( ctx, p, GL_DIFFUSE, l->Diffuse );
901 ctx->Driver.Lightfv( ctx, p, GL_SPECULAR, l->Specular );
902 ctx->Driver.Lightfv( ctx, p, GL_POSITION, NULL );
903 ctx->Driver.Lightfv( ctx, p, GL_SPOT_DIRECTION, NULL );
904 ctx->Driver.Lightfv( ctx, p, GL_SPOT_EXPONENT, &l->SpotExponent );
905 ctx->Driver.Lightfv( ctx, p, GL_SPOT_CUTOFF, &l->SpotCutoff );
906 ctx->Driver.Lightfv( ctx, p, GL_CONSTANT_ATTENUATION,
907 &l->ConstantAttenuation );
908 ctx->Driver.Lightfv( ctx, p, GL_LINEAR_ATTENUATION,
909 &l->LinearAttenuation );
910 ctx->Driver.Lightfv( ctx, p, GL_QUADRATIC_ATTENUATION,
911 &l->QuadraticAttenuation );
912 *(float *)&(rmesa->hw.lit[i].cmd[LIT_ATTEN_XXX]) = 0.0;
913 }
914
915 ctx->Driver.LightModelfv( ctx, GL_LIGHT_MODEL_AMBIENT,
916 ctx->Light.Model.Ambient );
917
918 TNL_CONTEXT(ctx)->Driver.NotifyMaterialChange( ctx );
919
920 for (i = 0 ; i < 6; i++) {
921 ctx->Driver.ClipPlane( ctx, GL_CLIP_PLANE0 + i, NULL );
922 }
923
924 ctx->Driver.Fogfv( ctx, GL_FOG_MODE, NULL );
925 ctx->Driver.Fogfv( ctx, GL_FOG_DENSITY, &ctx->Fog.Density );
926 ctx->Driver.Fogfv( ctx, GL_FOG_START, &ctx->Fog.Start );
927 ctx->Driver.Fogfv( ctx, GL_FOG_END, &ctx->Fog.End );
928 ctx->Driver.Fogfv( ctx, GL_FOG_COLOR, ctx->Fog.Color );
929 ctx->Driver.Fogfv( ctx, GL_FOG_COORDINATE_SOURCE_EXT, NULL );
930
931 rmesa->hw.grd.cmd[GRD_VERT_GUARD_CLIP_ADJ] = IEEE_ONE;
932 rmesa->hw.grd.cmd[GRD_VERT_GUARD_DISCARD_ADJ] = IEEE_ONE;
933 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_CLIP_ADJ] = IEEE_ONE;
934 rmesa->hw.grd.cmd[GRD_HORZ_GUARD_DISCARD_ADJ] = IEEE_ONE;
935
936 rmesa->hw.eye.cmd[EYE_X] = 0;
937 rmesa->hw.eye.cmd[EYE_Y] = 0;
938 rmesa->hw.eye.cmd[EYE_Z] = IEEE_ONE;
939 rmesa->hw.eye.cmd[EYE_RESCALE_FACTOR] = IEEE_ONE;
940
941 rmesa->radeon.hw.all_dirty = GL_TRUE;
942
943 rcommonInitCmdBuf(&rmesa->radeon);
944 }