src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "math/m_xform.h"
  44
  45 #include "swrast_setup/swrast_setup.h"
  46
  47 #include "tnl/tnl.h"
  48 #include "tnl/t_context.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "radeon_context.h"
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "radeon_swtcl.h"
  55 #include "radeon_tcl.h"
  56 #include "radeon_debug.h"
  57
  58
  59 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  62
  63 /***********************************************************************
  64  *                         Initialization
  65  ***********************************************************************/
  66
  67 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  68 do {                                                                    \
  69    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  70    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  71    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  72    fmt_0 |= F0;                                                         \
  73 } while (0)
  74
  75 #define EMIT_PAD( N )                                                   \
  76 do {                                                                    \
  77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  78    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  79    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  80    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  81 } while (0)
  82
  83 static GLuint radeon_cp_vc_frmts[3][2] =
  84 {
  85    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  86    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  87    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  88 };
  89
  90 static void radeonSetVertexFormat( struct gl_context *ctx )
  91 {
  92    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  93    TNLcontext *tnl = TNL_CONTEXT(ctx);
  94    struct vertex_buffer *VB = &tnl->vb;
  95    GLbitfield64 index_bitset = tnl->render_inputs_bitset;
  96    int fmt_0 = 0;
  97    int offset = 0;
  98
  99    /* Important:
 100     */
 101    if ( VB->NdcPtr != NULL ) {
 102       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 103    }
 104    else {
 105       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 106    }
 107
 108    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 109    rmesa->radeon.swtcl.vertex_attr_count = 0;
 110
 111    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 112     * build up a hardware vertex.
 113     */
 114    if ( !rmesa->swtcl.needproj ||
 115         (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
 116       /* for projtex */
 117       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 118                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 119       offset = 4;
 120    }
 121    else {
 122       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 123                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 124       offset = 3;
 125    }
 126
 127    rmesa->swtcl.coloroffset = offset;
 128 #if MESA_LITTLE_ENDIAN
 129    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 130               RADEON_CP_VC_FRMT_PKCOLOR );
 131 #else
 132    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 133               RADEON_CP_VC_FRMT_PKCOLOR );
 134 #endif
 135    offset += 1;
 136
 137    rmesa->swtcl.specoffset = 0;
 138    if (index_bitset &
 139        (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
 140
 141 #if MESA_LITTLE_ENDIAN
 142       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 143          rmesa->swtcl.specoffset = offset;
 144          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 145                     RADEON_CP_VC_FRMT_PKSPEC );
 146       }
 147       else {
 148          EMIT_PAD( 3 );
 149       }
 150
 151       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 152          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 153                     RADEON_CP_VC_FRMT_PKSPEC );
 154       }
 155       else {
 156          EMIT_PAD( 1 );
 157       }
 158 #else
 159       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 160          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 161                     RADEON_CP_VC_FRMT_PKSPEC );
 162       }
 163       else {
 164          EMIT_PAD( 1 );
 165       }
 166
 167       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 168          rmesa->swtcl.specoffset = offset;
 169          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 170                     RADEON_CP_VC_FRMT_PKSPEC );
 171       }
 172       else {
 173          EMIT_PAD( 3 );
 174       }
 175 #endif
 176    }
 177
 178    if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
 179       int i;
 180
 181       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 182          if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
 183             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 184
 185             switch (sz) {
 186             case 1:
 187             case 2:
 188                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 189                           radeon_cp_vc_frmts[i][0] );
 190                break;
 191             case 3:
 192                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 193                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 194                               radeon_cp_vc_frmts[i][1] );
 195                } else {
 196                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 197                               radeon_cp_vc_frmts[i][0] );
 198                }
 199                break;
 200             case 4:
 201                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 202                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 203                              radeon_cp_vc_frmts[i][1] );
 204                } else {
 205                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 206                              radeon_cp_vc_frmts[i][1] );
 207                }
 208                break;
 209             default:
 210                continue;
 211             };
 212          }
 213       }
 214    }
 215
 216    if (rmesa->radeon.tnl_index_bitset != index_bitset ||
 217        fmt_0 != rmesa->swtcl.vertex_format) {
 218       RADEON_NEWPRIM(rmesa);
 219       rmesa->swtcl.vertex_format = fmt_0;
 220       rmesa->radeon.swtcl.vertex_size =
 221           _tnl_install_attrs( ctx,
 222                               rmesa->radeon.swtcl.vertex_attrs,
 223                               rmesa->radeon.swtcl.vertex_attr_count,
 224                               NULL, 0 );
 225       rmesa->radeon.swtcl.vertex_size /= 4;
 226       rmesa->radeon.tnl_index_bitset = index_bitset;
 227       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 228           "%s: vertex_size= %d floats\n",  __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 229    }
 230 }
 231
 232 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 233 {
 234
 235     if (!rmesa->radeon.swtcl.emit_prediction) {
 236         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 237         const int scissor_size = 8;
 238         const int prims_size = 8;
 239         const int vertex_size = 7;
 240
 241         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 242                     state_size +
 243                     (scissor_size + prims_size + vertex_size),
 244                     __FUNCTION__))
 245             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 246         else
 247             rmesa->radeon.swtcl.emit_prediction = state_size;
 248         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 249             + rmesa->radeon.cmdbuf.cs->cdw;
 250     }
 251 }
 252
 253 static void radeonRenderStart( struct gl_context *ctx )
 254 {
 255     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 256
 257     radeonSetVertexFormat( ctx );
 258
 259     if (rmesa->radeon.dma.flush != 0 &&
 260             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 261         rmesa->radeon.dma.flush( ctx );
 262 }
 263
 264
 265 /**
 266  * Set vertex state for SW TCL.  The primary purpose of this function is to
 267  * determine in advance whether or not the hardware can / should do the
 268  * projection divide or Mesa should do it.
 269  */
 270 void radeonChooseVertexState( struct gl_context *ctx )
 271 {
 272    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 273    TNLcontext *tnl = TNL_CONTEXT(ctx);
 274
 275    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 276    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 277                          ctx->Polygon.BackMode != GL_FILL);
 278    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 279
 280    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 281                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 282                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 283
 284    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 285     * rasterization fallback.  As this function will be called again when we
 286     * leave a rasterization fallback, we can just skip it for now.
 287     */
 288    if (rmesa->radeon.Fallback != 0)
 289       return;
 290
 291    /* HW perspective divide is a win, but tiny vertex formats are a
 292     * bigger one.
 293     */
 294
 295    if ((0 == (tnl->render_inputs_bitset &
 296         (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
 297          | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
 298        || twosided
 299        || unfilled) {
 300       rmesa->swtcl.needproj = GL_TRUE;
 301       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 302                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 303    }
 304    else {
 305       rmesa->swtcl.needproj = GL_FALSE;
 306       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 307    }
 308
 309    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 310
 311    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 312       RADEON_STATECHANGE( rmesa, set );
 313       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 314    }
 315 }
 316
 317 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
 318 {
 319    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 320
 321
 322
 323    radeonEmitState(&rmesa->radeon);
 324    radeonEmitVertexAOS( rmesa,
 325                         rmesa->radeon.swtcl.vertex_size,
 326                         rmesa->radeon.swtcl.bo,
 327                         current_offset);
 328
 329
 330    radeonEmitVbufPrim( rmesa,
 331                        rmesa->swtcl.vertex_format,
 332                        rmesa->radeon.swtcl.hw_primitive,
 333                        rmesa->radeon.swtcl.numverts);
 334    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 335      WARN_ONCE("Rendering was %d commands larger than predicted size."
 336          " We might overflow  command buffer.\n",
 337          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 338
 339
 340    rmesa->radeon.swtcl.emit_prediction = 0;
 341
 342 }
 343
 344 /*
 345  * Render unclipped vertex buffers by emitting vertices directly to
 346  * dma buffers.  Use strip/fan hardware primitives where possible.
 347  * Try to simulate missing primitives with indexed vertices.
 348  */
 349 #define HAVE_POINTS      1
 350 #define HAVE_LINES       1
 351 #define HAVE_LINE_STRIPS 1
 352 #define HAVE_TRIANGLES   1
 353 #define HAVE_TRI_STRIPS  1
 354 #define HAVE_TRI_STRIP_1 0
 355 #define HAVE_TRI_FANS    1
 356 #define HAVE_QUADS       0
 357 #define HAVE_QUAD_STRIPS 0
 358 #define HAVE_POLYGONS    0
 359 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 360 #define HAVE_ELTS        0
 361
 362 static const GLuint hw_prim[GL_POLYGON+1] = {
 363    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 364    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 365    0,
 366    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 367    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 368    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 369    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 370    0,
 371    0,
 372    0
 373 };
 374
 375 static INLINE void
 376 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 377 {
 378    RADEON_NEWPRIM( rmesa );
 379    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 380    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 381 }
 382
 383 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 384 {
 385    void *rv;
 386    do {
 387      radeon_predict_emit_size( rmesa );
 388      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 389    } while (!rv);
 390    return rv;
 391 }
 392
 393 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 394 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 395 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 396 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 397 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 398 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 399   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 400 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 401 #define EMIT_VERTS( ctx, j, nr, buf ) \
 402   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 403
 404 #define TAG(x) radeon_dma_##x
 405 #include "tnl_dd/t_dd_dmatmp.h"
 406
 407
 408 /**********************************************************************/
 409 /*                          Render pipeline stage                     */
 410 /**********************************************************************/
 411
 412
 413 static GLboolean radeon_run_render( struct gl_context *ctx,
 414                                     struct tnl_pipeline_stage *stage )
 415 {
 416    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 417    TNLcontext *tnl = TNL_CONTEXT(ctx);
 418    struct vertex_buffer *VB = &tnl->vb;
 419    tnl_render_func *tab = TAG(render_tab_verts);
 420    GLuint i;
 421
 422    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 423        !radeon_dma_validate_render( ctx, VB ))
 424       return GL_TRUE;
 425
 426    radeon_prepare_render(&rmesa->radeon);
 427    if (rmesa->radeon.NewGLState)
 428       radeonValidateState( ctx );
 429
 430    tnl->Driver.Render.Start( ctx );
 431
 432    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 433    {
 434       GLuint prim = VB->Primitive[i].mode;
 435       GLuint start = VB->Primitive[i].start;
 436       GLuint length = VB->Primitive[i].count;
 437
 438       if (!length)
 439          continue;
 440
 441       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 442           "radeon_render.c: prim %s %d..%d\n",
 443                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 444                  start, start+length);
 445
 446       if (length)
 447          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 448    }
 449
 450    tnl->Driver.Render.Finish( ctx );
 451
 452    return GL_FALSE;             /* finished the pipe */
 453 }
 454
 455
 456
 457 const struct tnl_pipeline_stage _radeon_render_stage =
 458 {
 459    "radeon render",
 460    NULL,
 461    NULL,
 462    NULL,
 463    NULL,
 464    radeon_run_render            /* run */
 465 };
 466
 467
 468 /**************************************************************************/
 469
 470
 471 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 472    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 473    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 474    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 475    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 476    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 477    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 478    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 479    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 480    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 481    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 482 };
 483
 484 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
 485 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
 486 static void radeonResetLineStipple( struct gl_context *ctx );
 487
 488
 489 /***********************************************************************
 490  *                    Emit primitives as inline vertices               *
 491  ***********************************************************************/
 492
 493 #undef LOCAL_VARS
 494 #undef ALLOC_VERTS
 495 #define CTX_ARG r100ContextPtr rmesa
 496 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 497 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 498 #undef LOCAL_VARS
 499 #define LOCAL_VARS                                              \
 500    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 501    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 502 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 503 #define VERTEX radeonVertex
 504 #undef TAG
 505 #define TAG(x) radeon_##x
 506 #include "tnl_dd/t_dd_triemit.h"
 507
 508
 509 /***********************************************************************
 510  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 511  ***********************************************************************/
 512
 513 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 514 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 515 #define LINE( a, b )       radeon_line( rmesa, a, b )
 516 #define POINT( a )         radeon_point( rmesa, a )
 517
 518 /***********************************************************************
 519  *              Build render functions from dd templates               *
 520  ***********************************************************************/
 521
 522 #define RADEON_TWOSIDE_BIT      0x01
 523 #define RADEON_UNFILLED_BIT     0x02
 524 #define RADEON_MAX_TRIFUNC      0x04
 525
 526
 527 static struct {
 528    tnl_points_func              points;
 529    tnl_line_func                line;
 530    tnl_triangle_func    triangle;
 531    tnl_quad_func                quad;
 532 } rast_tab[RADEON_MAX_TRIFUNC];
 533
 534
 535 #define DO_FALLBACK  0
 536 #define DO_OFFSET    0
 537 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 538 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 539 #define DO_FLAT      0
 540 #define DO_TRI       1
 541 #define DO_QUAD      1
 542 #define DO_LINE      1
 543 #define DO_POINTS    1
 544 #define DO_FULL_QUAD 1
 545
 546 #define HAVE_SPEC   1
 547 #define HAVE_BACK_COLORS  0
 548 #define HAVE_HW_FLATSHADE 1
 549 #define TAB rast_tab
 550
 551 #define DEPTH_SCALE 1.0
 552 #define UNFILLED_TRI unfilled_tri
 553 #define UNFILLED_QUAD unfilled_quad
 554 #define VERT_X(_v) _v->v.x
 555 #define VERT_Y(_v) _v->v.y
 556 #define VERT_Z(_v) _v->v.z
 557 #define AREA_IS_CCW( a ) (a < 0)
 558 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 559
 560 #define VERT_SET_RGBA( v, c )                                   \
 561 do {                                                            \
 562    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 563    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 564    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 565    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 566    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 567 } while (0)
 568
 569 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 570
 571 #define VERT_SET_SPEC( v, c )                                   \
 572 do {                                                            \
 573    if (specoffset) {                                            \
 574       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 575       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 576       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 577       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 578    }                                                            \
 579 } while (0)
 580 #define VERT_COPY_SPEC( v0, v1 )                        \
 581 do {                                                    \
 582    if (specoffset) {                                    \
 583       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 584       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 585       spec0->red   = spec1->red;        \
 586       spec0->green = spec1->green;      \
 587       spec0->blue  = spec1->blue;       \
 588    }                                                    \
 589 } while (0)
 590
 591 /* These don't need LE32_TO_CPU() as they used to save and restore
 592  * colors which are already in the correct format.
 593  */
 594 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 595 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 596 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 597 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 598
 599 #undef LOCAL_VARS
 600 #undef TAG
 601 #undef INIT
 602
 603 #define LOCAL_VARS(n)                                                   \
 604    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 605    GLuint color[n] = {0}, spec[n] = {0};                                                \
 606    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 607    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 608    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 609
 610 /***********************************************************************
 611  *                Helpers for rendering unfilled primitives            *
 612  ***********************************************************************/
 613
 614 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 615 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 616 #undef TAG
 617 #define TAG(x) x
 618 #include "tnl_dd/t_dd_unfilled.h"
 619 #undef IND
 620
 621
 622 /***********************************************************************
 623  *                      Generate GL render functions                   *
 624  ***********************************************************************/
 625
 626
 627 #define IND (0)
 628 #define TAG(x) x
 629 #include "tnl_dd/t_dd_tritmp.h"
 630
 631 #define IND (RADEON_TWOSIDE_BIT)
 632 #define TAG(x) x##_twoside
 633 #include "tnl_dd/t_dd_tritmp.h"
 634
 635 #define IND (RADEON_UNFILLED_BIT)
 636 #define TAG(x) x##_unfilled
 637 #include "tnl_dd/t_dd_tritmp.h"
 638
 639 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 640 #define TAG(x) x##_twoside_unfilled
 641 #include "tnl_dd/t_dd_tritmp.h"
 642
 643
 644 static void init_rast_tab( void )
 645 {
 646    init();
 647    init_twoside();
 648    init_unfilled();
 649    init_twoside_unfilled();
 650 }
 651
 652 /**********************************************************************/
 653 /*               Render unclipped begin/end objects                   */
 654 /**********************************************************************/
 655
 656 #define RENDER_POINTS( start, count )           \
 657    for ( ; start < count ; start++)             \
 658       radeon_point( rmesa, VERT(start) )
 659 #define RENDER_LINE( v0, v1 ) \
 660    radeon_line( rmesa, VERT(v0), VERT(v1) )
 661 #define RENDER_TRI( v0, v1, v2 )  \
 662    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 663 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 664    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 665 #undef INIT
 666 #define INIT(x) do {                                    \
 667    radeonRenderPrimitive( ctx, x );                     \
 668 } while (0)
 669 #undef LOCAL_VARS
 670 #define LOCAL_VARS                                              \
 671    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 672    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 673    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 674    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 675    const GLboolean stipple = ctx->Line.StippleFlag;             \
 676    (void) elt; (void) stipple;
 677 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 678 #define RESET_OCCLUSION
 679 #define PRESERVE_VB_DEFS
 680 #define ELT(x) (x)
 681 #define TAG(x) radeon_##x##_verts
 682 #include "tnl/t_vb_rendertmp.h"
 683 #undef ELT
 684 #undef TAG
 685 #define TAG(x) radeon_##x##_elts
 686 #define ELT(x) elt[x]
 687 #include "tnl/t_vb_rendertmp.h"
 688
 689
 690
 691 /**********************************************************************/
 692 /*                    Choose render functions                         */
 693 /**********************************************************************/
 694
 695 void radeonChooseRenderState( struct gl_context *ctx )
 696 {
 697    TNLcontext *tnl = TNL_CONTEXT(ctx);
 698    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 699    GLuint index = 0;
 700    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 701                          ctx->Polygon.BackMode != GL_FILL);
 702    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 703
 704    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 705       return;
 706
 707    if (twosided)
 708       index |= RADEON_TWOSIDE_BIT;
 709    if (unfilled)
 710       index |= RADEON_UNFILLED_BIT;
 711
 712    if (index != rmesa->radeon.swtcl.RenderIndex) {
 713       tnl->Driver.Render.Points = rast_tab[index].points;
 714       tnl->Driver.Render.Line = rast_tab[index].line;
 715       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 716       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 717       tnl->Driver.Render.Quad = rast_tab[index].quad;
 718
 719       if (index == 0) {
 720          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 721          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 722          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 723       } else {
 724          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 725          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 726          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 727       }
 728
 729       rmesa->radeon.swtcl.RenderIndex = index;
 730    }
 731 }
 732
 733
 734 /**********************************************************************/
 735 /*                 High level hooks for t_vb_render.c                 */
 736 /**********************************************************************/
 737
 738
 739 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
 740 {
 741    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 742
 743    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 744       RADEON_NEWPRIM( rmesa );
 745       rmesa->radeon.swtcl.hw_primitive = hwprim;
 746    }
 747 }
 748
 749 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
 750 {
 751    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 752    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 753                          ctx->Polygon.BackMode != GL_FILL);
 754
 755    rmesa->radeon.swtcl.render_primitive = prim;
 756    if (prim < GL_TRIANGLES || !unfilled)
 757       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 758 }
 759
 760 static void radeonRenderFinish( struct gl_context *ctx )
 761 {
 762 }
 763
 764 static void radeonResetLineStipple( struct gl_context *ctx )
 765 {
 766    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 767    RADEON_STATECHANGE( rmesa, lin );
 768 }
 769
 770
 771 /**********************************************************************/
 772 /*           Transition to/from hardware rasterization.               */
 773 /**********************************************************************/
 774
 775 static const char * const fallbackStrings[] = {
 776    "Texture mode",
 777    "glDrawBuffer(GL_FRONT_AND_BACK)",
 778    "glEnable(GL_STENCIL) without hw stencil buffer",
 779    "glRenderMode(selection or feedback)",
 780    "glBlendEquation",
 781    "glBlendFunc",
 782    "RADEON_NO_RAST",
 783    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 784 };
 785
 786
 787 static const char *getFallbackString(GLuint bit)
 788 {
 789    int i = 0;
 790    while (bit > 1) {
 791       i++;
 792       bit >>= 1;
 793    }
 794    return fallbackStrings[i];
 795 }
 796
 797
 798 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
 799 {
 800    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 801    TNLcontext *tnl = TNL_CONTEXT(ctx);
 802    GLuint oldfallback = rmesa->radeon.Fallback;
 803
 804    if (mode) {
 805       rmesa->radeon.Fallback |= bit;
 806       if (oldfallback == 0) {
 807          radeon_firevertices(&rmesa->radeon);
 808          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 809          _swsetup_Wakeup( ctx );
 810          rmesa->radeon.swtcl.RenderIndex = ~0;
 811          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 812             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 813                     bit, getFallbackString(bit));
 814          }
 815       }
 816    }
 817    else {
 818       rmesa->radeon.Fallback &= ~bit;
 819       if (oldfallback == bit) {
 820          _swrast_flush( ctx );
 821          tnl->Driver.Render.Start = radeonRenderStart;
 822          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 823          tnl->Driver.Render.Finish = radeonRenderFinish;
 824
 825          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 826          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 827          tnl->Driver.Render.Interp = _tnl_interp;
 828
 829          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 830          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 831          if (rmesa->radeon.TclFallback) {
 832             /* These are already done if rmesa->radeon.TclFallback goes to
 833              * zero above. But not if it doesn't (RADEON_NO_TCL for
 834              * example?)
 835              */
 836             _tnl_invalidate_vertex_state( ctx, ~0 );
 837             _tnl_invalidate_vertices( ctx, ~0 );
 838             rmesa->radeon.tnl_index_bitset = 0;
 839             radeonChooseVertexState( ctx );
 840             radeonChooseRenderState( ctx );
 841          }
 842          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 843             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 844                     bit, getFallbackString(bit));
 845          }
 846       }
 847    }
 848 }
 849
 850
 851 /**********************************************************************/
 852 /*                            Initialization.                         */
 853 /**********************************************************************/
 854
 855 void radeonInitSwtcl( struct gl_context *ctx )
 856 {
 857    TNLcontext *tnl = TNL_CONTEXT(ctx);
 858    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 859    static int firsttime = 1;
 860
 861    if (firsttime) {
 862       init_rast_tab();
 863       firsttime = 0;
 864    }
 865    rmesa->radeon.swtcl.emit_prediction = 0;
 866
 867    tnl->Driver.Render.Start = radeonRenderStart;
 868    tnl->Driver.Render.Finish = radeonRenderFinish;
 869    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 870    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 871    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 872    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 873    tnl->Driver.Render.Interp = _tnl_interp;
 874
 875    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 876                        RADEON_MAX_TNL_VERTEX_SIZE);
 877
 878    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 879    rmesa->radeon.swtcl.RenderIndex = ~0;
 880    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 881    rmesa->radeon.swtcl.hw_primitive = 0;
 882 }
 883