1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/mtypes.h"
37 #include "main/colormac.h"
38 #include "main/enums.h"
39 #include "main/imports.h"
40 #include "main/macros.h"
42 #include "swrast_setup/swrast_setup.h"
43 #include "math/m_translate.h"
45 #include "tnl/t_context.h"
46 #include "tnl/t_pipeline.h"
48 #include "radeon_context.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_state.h"
51 #include "radeon_swtcl.h"
52 #include "radeon_tcl.h"
55 /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
56 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
57 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */
59 /***********************************************************************
61 ***********************************************************************/
63 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
65 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
66 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
67 rmesa->radeon.swtcl.vertex_attr_count++; \
71 #define EMIT_PAD( N ) \
73 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
74 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
75 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
76 rmesa->radeon.swtcl.vertex_attr_count++; \
79 static GLuint radeon_cp_vc_frmts
[3][2] =
81 { RADEON_CP_VC_FRMT_ST0
, RADEON_CP_VC_FRMT_ST0
| RADEON_CP_VC_FRMT_Q0
},
82 { RADEON_CP_VC_FRMT_ST1
, RADEON_CP_VC_FRMT_ST1
| RADEON_CP_VC_FRMT_Q1
},
83 { RADEON_CP_VC_FRMT_ST2
, RADEON_CP_VC_FRMT_ST2
| RADEON_CP_VC_FRMT_Q2
},
86 static void radeonSetVertexFormat( GLcontext
*ctx
)
88 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
89 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
90 struct vertex_buffer
*VB
= &tnl
->vb
;
91 DECLARE_RENDERINPUTS(index_bitset
);
95 RENDERINPUTS_COPY( index_bitset
, tnl
->render_inputs_bitset
);
99 if ( VB
->NdcPtr
!= NULL
) {
100 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
103 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->ClipPtr
;
106 assert( VB
->AttribPtr
[VERT_ATTRIB_POS
] != NULL
);
107 rmesa
->radeon
.swtcl
.vertex_attr_count
= 0;
109 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
110 * build up a hardware vertex.
112 if ( !rmesa
->swtcl
.needproj
||
113 RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) { /* for projtex */
114 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_4F
,
115 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
| RADEON_CP_VC_FRMT_W0
);
119 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_3F
,
120 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
);
124 rmesa
->swtcl
.coloroffset
= offset
;
125 #if MESA_LITTLE_ENDIAN
126 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_RGBA
,
127 RADEON_CP_VC_FRMT_PKCOLOR
);
129 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_ABGR
,
130 RADEON_CP_VC_FRMT_PKCOLOR
);
134 rmesa
->swtcl
.specoffset
= 0;
135 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
) ||
136 RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
138 #if MESA_LITTLE_ENDIAN
139 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
140 rmesa
->swtcl
.specoffset
= offset
;
141 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_RGB
,
142 RADEON_CP_VC_FRMT_PKSPEC
);
148 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
149 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
150 RADEON_CP_VC_FRMT_PKSPEC
);
156 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
157 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
158 RADEON_CP_VC_FRMT_PKSPEC
);
164 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
165 rmesa
->swtcl
.specoffset
= offset
;
166 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
,
167 RADEON_CP_VC_FRMT_PKSPEC
);
175 if (RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
178 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
179 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_TEX(i
) )) {
180 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
185 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_2F
,
186 radeon_cp_vc_frmts
[i
][0] );
190 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
& (TEXTURE_CUBE_BIT
) ) {
191 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F
,
192 radeon_cp_vc_frmts
[i
][1] );
194 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F_XYW
,
195 radeon_cp_vc_frmts
[i
][1] );
205 if (!RENDERINPUTS_EQUAL( rmesa
->radeon
.tnl_index_bitset
, index_bitset
) ||
206 fmt_0
!= rmesa
->swtcl
.vertex_format
) {
207 RADEON_NEWPRIM(rmesa
);
208 rmesa
->swtcl
.vertex_format
= fmt_0
;
209 rmesa
->radeon
.swtcl
.vertex_size
=
210 _tnl_install_attrs( ctx
,
211 rmesa
->radeon
.swtcl
.vertex_attrs
,
212 rmesa
->radeon
.swtcl
.vertex_attr_count
,
214 rmesa
->radeon
.swtcl
.vertex_size
/= 4;
215 RENDERINPUTS_COPY( rmesa
->radeon
.tnl_index_bitset
, index_bitset
);
216 if (RADEON_DEBUG
& DEBUG_VERTS
)
217 fprintf( stderr
, "%s: vertex_size= %d floats\n",
218 __FUNCTION__
, rmesa
->radeon
.swtcl
.vertex_size
);
223 static void radeonRenderStart( GLcontext
*ctx
)
225 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
227 radeonSetVertexFormat( ctx
);
229 if (rmesa
->radeon
.dma
.flush
!= 0 &&
230 rmesa
->radeon
.dma
.flush
!= rcommon_flush_last_swtcl_prim
)
231 rmesa
->radeon
.dma
.flush( ctx
);
236 * Set vertex state for SW TCL. The primary purpose of this function is to
237 * determine in advance whether or not the hardware can / should do the
238 * projection divide or Mesa should do it.
240 void radeonChooseVertexState( GLcontext
*ctx
)
242 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
243 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
245 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
247 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
248 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
249 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
251 /* We must ensure that we don't do _tnl_need_projected_coords while in a
252 * rasterization fallback. As this function will be called again when we
253 * leave a rasterization fallback, we can just skip it for now.
255 if (rmesa
->radeon
.Fallback
!= 0)
258 /* HW perspective divide is a win, but tiny vertex formats are a
262 if ((!RENDERINPUTS_TEST_RANGE( tnl
->render_inputs_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
) &&
263 !RENDERINPUTS_TEST( tnl
->render_inputs_bitset
, _TNL_ATTRIB_COLOR1
))
264 || (ctx
->_TriangleCaps
& (DD_TRI_LIGHT_TWOSIDE
|DD_TRI_UNFILLED
))) {
265 rmesa
->swtcl
.needproj
= GL_TRUE
;
266 se_coord_fmt
|= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
267 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
);
270 rmesa
->swtcl
.needproj
= GL_FALSE
;
271 se_coord_fmt
|= (RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
274 _tnl_need_projected_coords( ctx
, rmesa
->swtcl
.needproj
);
276 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
277 RADEON_STATECHANGE( rmesa
, set
);
278 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
282 void r100_swtcl_flush(GLcontext
*ctx
, uint32_t current_offset
)
284 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
286 rcommonEnsureCmdBufSpace(&rmesa
->radeon
,
287 rmesa
->hw
.max_state_size
+ (12*sizeof(int)),
291 radeonEmitState(rmesa
);
292 radeonEmitVertexAOS( rmesa
,
293 rmesa
->radeon
.swtcl
.vertex_size
,
294 // rmesa->radeon.dma.current,
298 radeonEmitVbufPrim( rmesa
,
299 rmesa
->swtcl
.vertex_format
,
300 rmesa
->radeon
.swtcl
.hw_primitive
,
301 rmesa
->radeon
.swtcl
.numverts
);
306 * Render unclipped vertex buffers by emitting vertices directly to
307 * dma buffers. Use strip/fan hardware primitives where possible.
308 * Try to simulate missing primitives with indexed vertices.
310 #define HAVE_POINTS 1
312 #define HAVE_LINE_STRIPS 1
313 #define HAVE_TRIANGLES 1
314 #define HAVE_TRI_STRIPS 1
315 #define HAVE_TRI_STRIP_1 0
316 #define HAVE_TRI_FANS 1
318 #define HAVE_QUAD_STRIPS 0
319 #define HAVE_POLYGONS 0
320 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
323 static const GLuint hw_prim
[GL_POLYGON
+1] = {
324 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
325 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
327 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
,
328 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
329 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
,
330 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
,
337 radeonDmaPrimitive( r100ContextPtr rmesa
, GLenum prim
)
339 RADEON_NEWPRIM( rmesa
);
340 rmesa
->radeon
.swtcl
.hw_primitive
= hw_prim
[prim
];
341 // assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
344 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
345 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
346 #define FLUSH() RADEON_NEWPRIM( rmesa )
347 #define GET_CURRENT_VB_MAX_VERTS() 10\
348 // (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
349 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
350 ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
351 #define ALLOC_VERTS( nr ) \
352 rcommonAllocDmaLowVerts( &rmesa->radeon, nr, rmesa->radeon.swtcl.vertex_size * 4 )
353 #define EMIT_VERTS( ctx, j, nr, buf ) \
354 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
356 #define TAG(x) radeon_dma_##x
357 #include "tnl_dd/t_dd_dmatmp.h"
360 /**********************************************************************/
361 /* Render pipeline stage */
362 /**********************************************************************/
365 static GLboolean
radeon_run_render( GLcontext
*ctx
,
366 struct tnl_pipeline_stage
*stage
)
368 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
369 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
370 struct vertex_buffer
*VB
= &tnl
->vb
;
371 tnl_render_func
*tab
= TAG(render_tab_verts
);
374 if (rmesa
->swtcl
.indexed_verts
.buf
)
377 if (rmesa
->radeon
.swtcl
.RenderIndex
!= 0 ||
378 !radeon_dma_validate_render( ctx
, VB
))
381 tnl
->Driver
.Render
.Start( ctx
);
383 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
385 GLuint prim
= VB
->Primitive
[i
].mode
;
386 GLuint start
= VB
->Primitive
[i
].start
;
387 GLuint length
= VB
->Primitive
[i
].count
;
392 if (RADEON_DEBUG
& DEBUG_PRIMS
)
393 fprintf(stderr
, "radeon_render.c: prim %s %d..%d\n",
394 _mesa_lookup_enum_by_nr(prim
& PRIM_MODE_MASK
),
395 start
, start
+length
);
398 tab
[prim
& PRIM_MODE_MASK
]( ctx
, start
, start
+ length
, prim
);
401 tnl
->Driver
.Render
.Finish( ctx
);
403 return GL_FALSE
; /* finished the pipe */
408 const struct tnl_pipeline_stage _radeon_render_stage
=
415 radeon_run_render
/* run */
419 /**************************************************************************/
422 static const GLuint reduced_hw_prim
[GL_POLYGON
+1] = {
423 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
424 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
425 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
426 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
427 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
428 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
429 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
430 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
431 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
432 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
435 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
);
436 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
);
437 static void radeonResetLineStipple( GLcontext
*ctx
);
440 /***********************************************************************
441 * Emit primitives as inline vertices *
442 ***********************************************************************/
446 #define CTX_ARG r100ContextPtr rmesa
447 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
448 #define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, (size) * 4 )
451 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
452 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
453 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
454 #define VERTEX radeonVertex
456 #define TAG(x) radeon_##x
457 #include "tnl_dd/t_dd_triemit.h"
460 /***********************************************************************
461 * Macros for t_dd_tritmp.h to draw basic primitives *
462 ***********************************************************************/
464 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
465 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
466 #define LINE( a, b ) radeon_line( rmesa, a, b )
467 #define POINT( a ) radeon_point( rmesa, a )
469 /***********************************************************************
470 * Build render functions from dd templates *
471 ***********************************************************************/
473 #define RADEON_TWOSIDE_BIT 0x01
474 #define RADEON_UNFILLED_BIT 0x02
475 #define RADEON_MAX_TRIFUNC 0x04
479 tnl_points_func points
;
481 tnl_triangle_func triangle
;
483 } rast_tab
[RADEON_MAX_TRIFUNC
];
486 #define DO_FALLBACK 0
488 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
489 #define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
495 #define DO_FULL_QUAD 1
499 #define HAVE_BACK_COLORS 0
500 #define HAVE_HW_FLATSHADE 1
503 #define DEPTH_SCALE 1.0
504 #define UNFILLED_TRI unfilled_tri
505 #define UNFILLED_QUAD unfilled_quad
506 #define VERT_X(_v) _v->v.x
507 #define VERT_Y(_v) _v->v.y
508 #define VERT_Z(_v) _v->v.z
509 #define AREA_IS_CCW( a ) (a < 0)
510 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
512 #define VERT_SET_RGBA( v, c ) \
514 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
515 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
516 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
517 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
518 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
521 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
523 #define VERT_SET_SPEC( v, c ) \
526 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
527 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
528 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
529 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
532 #define VERT_COPY_SPEC( v0, v1 ) \
535 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
536 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
537 spec0->red = spec1->red; \
538 spec0->green = spec1->green; \
539 spec0->blue = spec1->blue; \
543 /* These don't need LE32_TO_CPU() as they used to save and restore
544 * colors which are already in the correct format.
546 #define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
547 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
548 #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
549 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
555 #define LOCAL_VARS(n) \
556 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
557 GLuint color[n], spec[n]; \
558 GLuint coloroffset = rmesa->swtcl.coloroffset; \
559 GLuint specoffset = rmesa->swtcl.specoffset; \
560 (void) color; (void) spec; (void) coloroffset; (void) specoffset;
562 /***********************************************************************
563 * Helpers for rendering unfilled primitives *
564 ***********************************************************************/
566 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
567 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
570 #include "tnl_dd/t_dd_unfilled.h"
574 /***********************************************************************
575 * Generate GL render functions *
576 ***********************************************************************/
581 #include "tnl_dd/t_dd_tritmp.h"
583 #define IND (RADEON_TWOSIDE_BIT)
584 #define TAG(x) x##_twoside
585 #include "tnl_dd/t_dd_tritmp.h"
587 #define IND (RADEON_UNFILLED_BIT)
588 #define TAG(x) x##_unfilled
589 #include "tnl_dd/t_dd_tritmp.h"
591 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
592 #define TAG(x) x##_twoside_unfilled
593 #include "tnl_dd/t_dd_tritmp.h"
596 static void init_rast_tab( void )
601 init_twoside_unfilled();
604 /**********************************************************************/
605 /* Render unclipped begin/end objects */
606 /**********************************************************************/
608 #define RENDER_POINTS( start, count ) \
609 for ( ; start < count ; start++) \
610 radeon_point( rmesa, VERT(start) )
611 #define RENDER_LINE( v0, v1 ) \
612 radeon_line( rmesa, VERT(v0), VERT(v1) )
613 #define RENDER_TRI( v0, v1, v2 ) \
614 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
615 #define RENDER_QUAD( v0, v1, v2, v3 ) \
616 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
618 #define INIT(x) do { \
619 radeonRenderPrimitive( ctx, x ); \
623 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
624 const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
625 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; \
626 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
627 const GLboolean stipple = ctx->Line.StippleFlag; \
628 (void) elt; (void) stipple;
629 #define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx );
630 #define RESET_OCCLUSION
631 #define PRESERVE_VB_DEFS
633 #define TAG(x) radeon_##x##_verts
634 #include "tnl/t_vb_rendertmp.h"
637 #define TAG(x) radeon_##x##_elts
638 #define ELT(x) elt[x]
639 #include "tnl/t_vb_rendertmp.h"
643 /**********************************************************************/
644 /* Choose render functions */
645 /**********************************************************************/
647 void radeonChooseRenderState( GLcontext
*ctx
)
649 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
650 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
652 GLuint flags
= ctx
->_TriangleCaps
;
654 if (!rmesa
->radeon
.TclFallback
|| rmesa
->radeon
.Fallback
)
657 if (flags
& DD_TRI_LIGHT_TWOSIDE
) index
|= RADEON_TWOSIDE_BIT
;
658 if (flags
& DD_TRI_UNFILLED
) index
|= RADEON_UNFILLED_BIT
;
660 if (index
!= rmesa
->radeon
.swtcl
.RenderIndex
) {
661 tnl
->Driver
.Render
.Points
= rast_tab
[index
].points
;
662 tnl
->Driver
.Render
.Line
= rast_tab
[index
].line
;
663 tnl
->Driver
.Render
.ClippedLine
= rast_tab
[index
].line
;
664 tnl
->Driver
.Render
.Triangle
= rast_tab
[index
].triangle
;
665 tnl
->Driver
.Render
.Quad
= rast_tab
[index
].quad
;
668 tnl
->Driver
.Render
.PrimTabVerts
= radeon_render_tab_verts
;
669 tnl
->Driver
.Render
.PrimTabElts
= radeon_render_tab_elts
;
670 tnl
->Driver
.Render
.ClippedPolygon
= radeon_fast_clipped_poly
;
672 tnl
->Driver
.Render
.PrimTabVerts
= _tnl_render_tab_verts
;
673 tnl
->Driver
.Render
.PrimTabElts
= _tnl_render_tab_elts
;
674 tnl
->Driver
.Render
.ClippedPolygon
= _tnl_RenderClippedPolygon
;
677 rmesa
->radeon
.swtcl
.RenderIndex
= index
;
682 /**********************************************************************/
683 /* High level hooks for t_vb_render.c */
684 /**********************************************************************/
687 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
)
689 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
691 if (rmesa
->radeon
.swtcl
.hw_primitive
!= hwprim
) {
692 RADEON_NEWPRIM( rmesa
);
693 rmesa
->radeon
.swtcl
.hw_primitive
= hwprim
;
697 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
)
699 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
700 rmesa
->radeon
.swtcl
.render_primitive
= prim
;
701 if (prim
< GL_TRIANGLES
|| !(ctx
->_TriangleCaps
& DD_TRI_UNFILLED
))
702 radeonRasterPrimitive( ctx
, reduced_hw_prim
[prim
] );
705 static void radeonRenderFinish( GLcontext
*ctx
)
709 static void radeonResetLineStipple( GLcontext
*ctx
)
711 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
712 RADEON_STATECHANGE( rmesa
, lin
);
716 /**********************************************************************/
717 /* Transition to/from hardware rasterization. */
718 /**********************************************************************/
720 static const char * const fallbackStrings
[] = {
722 "glDrawBuffer(GL_FRONT_AND_BACK)",
723 "glEnable(GL_STENCIL) without hw stencil buffer",
724 "glRenderMode(selection or feedback)",
728 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
732 static const char *getFallbackString(GLuint bit
)
739 return fallbackStrings
[i
];
743 void radeonFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
745 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
746 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
747 GLuint oldfallback
= rmesa
->radeon
.Fallback
;
750 rmesa
->radeon
.Fallback
|= bit
;
751 if (oldfallback
== 0) {
752 RADEON_FIREVERTICES( rmesa
);
753 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_TRUE
);
754 _swsetup_Wakeup( ctx
);
755 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
756 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
757 fprintf(stderr
, "Radeon begin rasterization fallback: 0x%x %s\n",
758 bit
, getFallbackString(bit
));
763 rmesa
->radeon
.Fallback
&= ~bit
;
764 if (oldfallback
== bit
) {
765 _swrast_flush( ctx
);
766 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
767 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
768 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
770 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
771 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
772 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
774 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
775 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_FALSE
);
776 if (rmesa
->radeon
.TclFallback
) {
777 /* These are already done if rmesa->radeon.TclFallback goes to
778 * zero above. But not if it doesn't (RADEON_NO_TCL for
781 _tnl_invalidate_vertex_state( ctx
, ~0 );
782 _tnl_invalidate_vertices( ctx
, ~0 );
783 RENDERINPUTS_ZERO( rmesa
->radeon
.tnl_index_bitset
);
784 radeonChooseVertexState( ctx
);
785 radeonChooseRenderState( ctx
);
787 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
788 fprintf(stderr
, "Radeon end rasterization fallback: 0x%x %s\n",
789 bit
, getFallbackString(bit
));
796 /**********************************************************************/
797 /* Initialization. */
798 /**********************************************************************/
800 void radeonInitSwtcl( GLcontext
*ctx
)
802 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
803 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
804 static int firsttime
= 1;
811 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
812 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
813 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
814 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
815 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
816 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
817 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
819 _tnl_init_vertices( ctx
, ctx
->Const
.MaxArrayLockSize
+ 12,
820 RADEON_MAX_TNL_VERTEX_SIZE
);
822 rmesa
->radeon
.swtcl
.verts
= (GLubyte
*)tnl
->clipspace
.vertex_buf
;
823 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
824 rmesa
->radeon
.swtcl
.render_primitive
= GL_TRIANGLES
;
825 rmesa
->radeon
.swtcl
.hw_primitive
= 0;
829 void radeonDestroySwtcl( GLcontext
*ctx
)
831 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
833 // if (rmesa->swtcl.indexed_verts.buf)
834 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,