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radeon: fix scissors harder.
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_swtcl.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 */
34
35 #include "main/glheader.h"
36 #include "main/mtypes.h"
37 #include "main/colormac.h"
38 #include "main/enums.h"
39 #include "main/imports.h"
40 #include "main/macros.h"
41 #include "main/simple_list.h"
42
43 #include "swrast_setup/swrast_setup.h"
44 #include "math/m_translate.h"
45 #include "tnl/tnl.h"
46 #include "tnl/t_context.h"
47 #include "tnl/t_pipeline.h"
48
49 #include "radeon_context.h"
50 #include "radeon_ioctl.h"
51 #include "radeon_state.h"
52 #include "radeon_swtcl.h"
53 #include "radeon_tcl.h"
54
55
56 /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
57 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
58 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */
59
60 /***********************************************************************
61 * Initialization
62 ***********************************************************************/
63
64 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
65 do { \
66 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
67 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
68 rmesa->radeon.swtcl.vertex_attr_count++; \
69 fmt_0 |= F0; \
70 } while (0)
71
72 #define EMIT_PAD( N ) \
73 do { \
74 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
75 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
76 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
77 rmesa->radeon.swtcl.vertex_attr_count++; \
78 } while (0)
79
80 static GLuint radeon_cp_vc_frmts[3][2] =
81 {
82 { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
83 { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
84 { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
85 };
86
87 static void radeonSetVertexFormat( GLcontext *ctx )
88 {
89 r100ContextPtr rmesa = R100_CONTEXT( ctx );
90 TNLcontext *tnl = TNL_CONTEXT(ctx);
91 struct vertex_buffer *VB = &tnl->vb;
92 DECLARE_RENDERINPUTS(index_bitset);
93 int fmt_0 = 0;
94 int offset = 0;
95
96 RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
97
98 /* Important:
99 */
100 if ( VB->NdcPtr != NULL ) {
101 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
102 }
103 else {
104 VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
105 }
106
107 assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
108 rmesa->radeon.swtcl.vertex_attr_count = 0;
109
110 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
111 * build up a hardware vertex.
112 */
113 if ( !rmesa->swtcl.needproj ||
114 RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) { /* for projtex */
115 EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
116 RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
117 offset = 4;
118 }
119 else {
120 EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
121 RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
122 offset = 3;
123 }
124
125 rmesa->swtcl.coloroffset = offset;
126 #if MESA_LITTLE_ENDIAN
127 EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
128 RADEON_CP_VC_FRMT_PKCOLOR );
129 #else
130 EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
131 RADEON_CP_VC_FRMT_PKCOLOR );
132 #endif
133 offset += 1;
134
135 rmesa->swtcl.specoffset = 0;
136 if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
137 RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
138
139 #if MESA_LITTLE_ENDIAN
140 if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
141 rmesa->swtcl.specoffset = offset;
142 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
143 RADEON_CP_VC_FRMT_PKSPEC );
144 }
145 else {
146 EMIT_PAD( 3 );
147 }
148
149 if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
150 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
151 RADEON_CP_VC_FRMT_PKSPEC );
152 }
153 else {
154 EMIT_PAD( 1 );
155 }
156 #else
157 if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
158 EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
159 RADEON_CP_VC_FRMT_PKSPEC );
160 }
161 else {
162 EMIT_PAD( 1 );
163 }
164
165 if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
166 rmesa->swtcl.specoffset = offset;
167 EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
168 RADEON_CP_VC_FRMT_PKSPEC );
169 }
170 else {
171 EMIT_PAD( 3 );
172 }
173 #endif
174 }
175
176 if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
177 int i;
178
179 for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
180 if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
181 GLuint sz = VB->TexCoordPtr[i]->size;
182
183 switch (sz) {
184 case 1:
185 case 2:
186 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
187 radeon_cp_vc_frmts[i][0] );
188 break;
189 case 3:
190 case 4:
191 if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
192 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
193 radeon_cp_vc_frmts[i][1] );
194 } else {
195 EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
196 radeon_cp_vc_frmts[i][1] );
197 }
198 break;
199 default:
200 continue;
201 };
202 }
203 }
204 }
205
206 if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
207 fmt_0 != rmesa->swtcl.vertex_format) {
208 RADEON_NEWPRIM(rmesa);
209 rmesa->swtcl.vertex_format = fmt_0;
210 rmesa->radeon.swtcl.vertex_size =
211 _tnl_install_attrs( ctx,
212 rmesa->radeon.swtcl.vertex_attrs,
213 rmesa->radeon.swtcl.vertex_attr_count,
214 NULL, 0 );
215 rmesa->radeon.swtcl.vertex_size /= 4;
216 RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
217 if (RADEON_DEBUG & DEBUG_VERTS)
218 fprintf( stderr, "%s: vertex_size= %d floats\n",
219 __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
220 }
221 }
222
223 static void radeon_predict_emit_size( GLcontext* ctx )
224 {
225 r100ContextPtr rmesa = R100_CONTEXT( ctx );
226
227 if (!rmesa->radeon.swtcl.emit_prediction) {
228 const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
229 const int scissor_size = 8;
230 const int prims_size = 8;
231 const int vertex_size = 7;
232
233 if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
234 state_size +
235 (scissor_size + prims_size + vertex_size),
236 __FUNCTION__))
237 rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
238 else
239 rmesa->radeon.swtcl.emit_prediction = state_size;
240 rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
241 + rmesa->radeon.cmdbuf.cs->cdw;
242 }
243 }
244
245 static void radeonRenderStart( GLcontext *ctx )
246 {
247 r100ContextPtr rmesa = R100_CONTEXT( ctx );
248
249 radeonSetVertexFormat( ctx );
250
251 if (rmesa->radeon.dma.flush != 0 &&
252 rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
253 rmesa->radeon.dma.flush( ctx );
254 radeon_predict_emit_size( ctx );
255 }
256
257
258 /**
259 * Set vertex state for SW TCL. The primary purpose of this function is to
260 * determine in advance whether or not the hardware can / should do the
261 * projection divide or Mesa should do it.
262 */
263 void radeonChooseVertexState( GLcontext *ctx )
264 {
265 r100ContextPtr rmesa = R100_CONTEXT( ctx );
266 TNLcontext *tnl = TNL_CONTEXT(ctx);
267
268 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
269
270 se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
271 RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
272 RADEON_VTX_W0_IS_NOT_1_OVER_W0);
273
274 /* We must ensure that we don't do _tnl_need_projected_coords while in a
275 * rasterization fallback. As this function will be called again when we
276 * leave a rasterization fallback, we can just skip it for now.
277 */
278 if (rmesa->radeon.Fallback != 0)
279 return;
280
281 /* HW perspective divide is a win, but tiny vertex formats are a
282 * bigger one.
283 */
284
285 if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
286 !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
287 || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
288 rmesa->swtcl.needproj = GL_TRUE;
289 se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
290 RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
291 }
292 else {
293 rmesa->swtcl.needproj = GL_FALSE;
294 se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
295 }
296
297 _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
298
299 if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
300 RADEON_STATECHANGE( rmesa, set );
301 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
302 }
303 }
304
305 void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
306 {
307 r100ContextPtr rmesa = R100_CONTEXT(ctx);
308
309
310
311 radeonEmitState(&rmesa->radeon);
312 radeonEmitVertexAOS( rmesa,
313 rmesa->radeon.swtcl.vertex_size,
314 first_elem(&rmesa->radeon.dma.reserved)->bo,
315 current_offset);
316
317
318 radeonEmitVbufPrim( rmesa,
319 rmesa->swtcl.vertex_format,
320 rmesa->radeon.swtcl.hw_primitive,
321 rmesa->radeon.swtcl.numverts);
322 if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
323 WARN_ONCE("Rendering was %d commands larger than predicted size."
324 " We might overflow command buffer.\n",
325 rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
326
327 radeon_predict_emit_size( ctx );
328
329 rmesa->radeon.swtcl.emit_prediction = 0;
330
331 }
332
333 /*
334 * Render unclipped vertex buffers by emitting vertices directly to
335 * dma buffers. Use strip/fan hardware primitives where possible.
336 * Try to simulate missing primitives with indexed vertices.
337 */
338 #define HAVE_POINTS 1
339 #define HAVE_LINES 1
340 #define HAVE_LINE_STRIPS 1
341 #define HAVE_TRIANGLES 1
342 #define HAVE_TRI_STRIPS 1
343 #define HAVE_TRI_STRIP_1 0
344 #define HAVE_TRI_FANS 1
345 #define HAVE_QUADS 0
346 #define HAVE_QUAD_STRIPS 0
347 #define HAVE_POLYGONS 0
348 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
349 #define HAVE_ELTS 0
350
351 static const GLuint hw_prim[GL_POLYGON+1] = {
352 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
353 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
354 0,
355 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
356 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
357 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
358 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
359 0,
360 0,
361 0
362 };
363
364 static INLINE void
365 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
366 {
367 RADEON_NEWPRIM( rmesa );
368 rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
369 // assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
370 }
371
372 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
373 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
374 #define FLUSH() RADEON_NEWPRIM( rmesa )
375 #define GET_CURRENT_VB_MAX_VERTS() 10\
376 // (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
377 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
378 ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
379 #define ALLOC_VERTS( nr ) \
380 rcommonAllocDmaLowVerts( &rmesa->radeon, nr, rmesa->radeon.swtcl.vertex_size * 4 )
381 #define EMIT_VERTS( ctx, j, nr, buf ) \
382 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
383
384 #define TAG(x) radeon_dma_##x
385 #include "tnl_dd/t_dd_dmatmp.h"
386
387
388 /**********************************************************************/
389 /* Render pipeline stage */
390 /**********************************************************************/
391
392
393 static GLboolean radeon_run_render( GLcontext *ctx,
394 struct tnl_pipeline_stage *stage )
395 {
396 r100ContextPtr rmesa = R100_CONTEXT(ctx);
397 TNLcontext *tnl = TNL_CONTEXT(ctx);
398 struct vertex_buffer *VB = &tnl->vb;
399 tnl_render_func *tab = TAG(render_tab_verts);
400 GLuint i;
401
402 if (rmesa->radeon.swtcl.RenderIndex != 0 ||
403 !radeon_dma_validate_render( ctx, VB ))
404 return GL_TRUE;
405
406 tnl->Driver.Render.Start( ctx );
407
408 for (i = 0 ; i < VB->PrimitiveCount ; i++)
409 {
410 GLuint prim = VB->Primitive[i].mode;
411 GLuint start = VB->Primitive[i].start;
412 GLuint length = VB->Primitive[i].count;
413
414 if (!length)
415 continue;
416
417 if (RADEON_DEBUG & DEBUG_PRIMS)
418 fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
419 _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
420 start, start+length);
421
422 if (length)
423 tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
424 }
425
426 tnl->Driver.Render.Finish( ctx );
427
428 return GL_FALSE; /* finished the pipe */
429 }
430
431
432
433 const struct tnl_pipeline_stage _radeon_render_stage =
434 {
435 "radeon render",
436 NULL,
437 NULL,
438 NULL,
439 NULL,
440 radeon_run_render /* run */
441 };
442
443
444 /**************************************************************************/
445
446
447 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
448 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
449 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
450 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
451 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
452 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
453 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
454 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
455 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
456 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
457 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
458 };
459
460 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
461 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
462 static void radeonResetLineStipple( GLcontext *ctx );
463
464
465 /***********************************************************************
466 * Emit primitives as inline vertices *
467 ***********************************************************************/
468
469 #undef LOCAL_VARS
470 #undef ALLOC_VERTS
471 #define CTX_ARG r100ContextPtr rmesa
472 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
473 #define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, (size) * 4 )
474 #undef LOCAL_VARS
475 #define LOCAL_VARS \
476 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
477 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
478 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
479 #define VERTEX radeonVertex
480 #undef TAG
481 #define TAG(x) radeon_##x
482 #include "tnl_dd/t_dd_triemit.h"
483
484
485 /***********************************************************************
486 * Macros for t_dd_tritmp.h to draw basic primitives *
487 ***********************************************************************/
488
489 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
490 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
491 #define LINE( a, b ) radeon_line( rmesa, a, b )
492 #define POINT( a ) radeon_point( rmesa, a )
493
494 /***********************************************************************
495 * Build render functions from dd templates *
496 ***********************************************************************/
497
498 #define RADEON_TWOSIDE_BIT 0x01
499 #define RADEON_UNFILLED_BIT 0x02
500 #define RADEON_MAX_TRIFUNC 0x04
501
502
503 static struct {
504 tnl_points_func points;
505 tnl_line_func line;
506 tnl_triangle_func triangle;
507 tnl_quad_func quad;
508 } rast_tab[RADEON_MAX_TRIFUNC];
509
510
511 #define DO_FALLBACK 0
512 #define DO_OFFSET 0
513 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
514 #define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
515 #define DO_FLAT 0
516 #define DO_TRI 1
517 #define DO_QUAD 1
518 #define DO_LINE 1
519 #define DO_POINTS 1
520 #define DO_FULL_QUAD 1
521
522 #define HAVE_RGBA 1
523 #define HAVE_SPEC 1
524 #define HAVE_BACK_COLORS 0
525 #define HAVE_HW_FLATSHADE 1
526 #define TAB rast_tab
527
528 #define DEPTH_SCALE 1.0
529 #define UNFILLED_TRI unfilled_tri
530 #define UNFILLED_QUAD unfilled_quad
531 #define VERT_X(_v) _v->v.x
532 #define VERT_Y(_v) _v->v.y
533 #define VERT_Z(_v) _v->v.z
534 #define AREA_IS_CCW( a ) (a < 0)
535 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
536
537 #define VERT_SET_RGBA( v, c ) \
538 do { \
539 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
540 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
541 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
542 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
543 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
544 } while (0)
545
546 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
547
548 #define VERT_SET_SPEC( v, c ) \
549 do { \
550 if (specoffset) { \
551 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
552 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
553 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
554 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
555 } \
556 } while (0)
557 #define VERT_COPY_SPEC( v0, v1 ) \
558 do { \
559 if (specoffset) { \
560 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
561 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
562 spec0->red = spec1->red; \
563 spec0->green = spec1->green; \
564 spec0->blue = spec1->blue; \
565 } \
566 } while (0)
567
568 /* These don't need LE32_TO_CPU() as they used to save and restore
569 * colors which are already in the correct format.
570 */
571 #define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
572 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
573 #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
574 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
575
576 #undef LOCAL_VARS
577 #undef TAG
578 #undef INIT
579
580 #define LOCAL_VARS(n) \
581 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
582 GLuint color[n] = {0}, spec[n] = {0}; \
583 GLuint coloroffset = rmesa->swtcl.coloroffset; \
584 GLuint specoffset = rmesa->swtcl.specoffset; \
585 (void) color; (void) spec; (void) coloroffset; (void) specoffset;
586
587 /***********************************************************************
588 * Helpers for rendering unfilled primitives *
589 ***********************************************************************/
590
591 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
592 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
593 #undef TAG
594 #define TAG(x) x
595 #include "tnl_dd/t_dd_unfilled.h"
596 #undef IND
597
598
599 /***********************************************************************
600 * Generate GL render functions *
601 ***********************************************************************/
602
603
604 #define IND (0)
605 #define TAG(x) x
606 #include "tnl_dd/t_dd_tritmp.h"
607
608 #define IND (RADEON_TWOSIDE_BIT)
609 #define TAG(x) x##_twoside
610 #include "tnl_dd/t_dd_tritmp.h"
611
612 #define IND (RADEON_UNFILLED_BIT)
613 #define TAG(x) x##_unfilled
614 #include "tnl_dd/t_dd_tritmp.h"
615
616 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
617 #define TAG(x) x##_twoside_unfilled
618 #include "tnl_dd/t_dd_tritmp.h"
619
620
621 static void init_rast_tab( void )
622 {
623 init();
624 init_twoside();
625 init_unfilled();
626 init_twoside_unfilled();
627 }
628
629 /**********************************************************************/
630 /* Render unclipped begin/end objects */
631 /**********************************************************************/
632
633 #define RENDER_POINTS( start, count ) \
634 for ( ; start < count ; start++) \
635 radeon_point( rmesa, VERT(start) )
636 #define RENDER_LINE( v0, v1 ) \
637 radeon_line( rmesa, VERT(v0), VERT(v1) )
638 #define RENDER_TRI( v0, v1, v2 ) \
639 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
640 #define RENDER_QUAD( v0, v1, v2, v3 ) \
641 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
642 #undef INIT
643 #define INIT(x) do { \
644 radeonRenderPrimitive( ctx, x ); \
645 } while (0)
646 #undef LOCAL_VARS
647 #define LOCAL_VARS \
648 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
649 const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
650 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; \
651 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
652 const GLboolean stipple = ctx->Line.StippleFlag; \
653 (void) elt; (void) stipple;
654 #define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx );
655 #define RESET_OCCLUSION
656 #define PRESERVE_VB_DEFS
657 #define ELT(x) (x)
658 #define TAG(x) radeon_##x##_verts
659 #include "tnl/t_vb_rendertmp.h"
660 #undef ELT
661 #undef TAG
662 #define TAG(x) radeon_##x##_elts
663 #define ELT(x) elt[x]
664 #include "tnl/t_vb_rendertmp.h"
665
666
667
668 /**********************************************************************/
669 /* Choose render functions */
670 /**********************************************************************/
671
672 void radeonChooseRenderState( GLcontext *ctx )
673 {
674 TNLcontext *tnl = TNL_CONTEXT(ctx);
675 r100ContextPtr rmesa = R100_CONTEXT(ctx);
676 GLuint index = 0;
677 GLuint flags = ctx->_TriangleCaps;
678
679 if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
680 return;
681
682 if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
683 if (flags & DD_TRI_UNFILLED) index |= RADEON_UNFILLED_BIT;
684
685 if (index != rmesa->radeon.swtcl.RenderIndex) {
686 tnl->Driver.Render.Points = rast_tab[index].points;
687 tnl->Driver.Render.Line = rast_tab[index].line;
688 tnl->Driver.Render.ClippedLine = rast_tab[index].line;
689 tnl->Driver.Render.Triangle = rast_tab[index].triangle;
690 tnl->Driver.Render.Quad = rast_tab[index].quad;
691
692 if (index == 0) {
693 tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
694 tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
695 tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
696 } else {
697 tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
698 tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
699 tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
700 }
701
702 rmesa->radeon.swtcl.RenderIndex = index;
703 }
704 }
705
706
707 /**********************************************************************/
708 /* High level hooks for t_vb_render.c */
709 /**********************************************************************/
710
711
712 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
713 {
714 r100ContextPtr rmesa = R100_CONTEXT(ctx);
715
716 if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
717 RADEON_NEWPRIM( rmesa );
718 rmesa->radeon.swtcl.hw_primitive = hwprim;
719 }
720 }
721
722 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
723 {
724 r100ContextPtr rmesa = R100_CONTEXT(ctx);
725 rmesa->radeon.swtcl.render_primitive = prim;
726 if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
727 radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
728 }
729
730 static void radeonRenderFinish( GLcontext *ctx )
731 {
732 }
733
734 static void radeonResetLineStipple( GLcontext *ctx )
735 {
736 r100ContextPtr rmesa = R100_CONTEXT(ctx);
737 RADEON_STATECHANGE( rmesa, lin );
738 }
739
740
741 /**********************************************************************/
742 /* Transition to/from hardware rasterization. */
743 /**********************************************************************/
744
745 static const char * const fallbackStrings[] = {
746 "Texture mode",
747 "glDrawBuffer(GL_FRONT_AND_BACK)",
748 "glEnable(GL_STENCIL) without hw stencil buffer",
749 "glRenderMode(selection or feedback)",
750 "glBlendEquation",
751 "glBlendFunc",
752 "RADEON_NO_RAST",
753 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
754 };
755
756
757 static const char *getFallbackString(GLuint bit)
758 {
759 int i = 0;
760 while (bit > 1) {
761 i++;
762 bit >>= 1;
763 }
764 return fallbackStrings[i];
765 }
766
767
768 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
769 {
770 r100ContextPtr rmesa = R100_CONTEXT(ctx);
771 TNLcontext *tnl = TNL_CONTEXT(ctx);
772 GLuint oldfallback = rmesa->radeon.Fallback;
773
774 if (mode) {
775 rmesa->radeon.Fallback |= bit;
776 if (oldfallback == 0) {
777 radeon_firevertices(&rmesa->radeon);
778 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
779 _swsetup_Wakeup( ctx );
780 rmesa->radeon.swtcl.RenderIndex = ~0;
781 if (RADEON_DEBUG & DEBUG_FALLBACKS) {
782 fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
783 bit, getFallbackString(bit));
784 }
785 }
786 }
787 else {
788 rmesa->radeon.Fallback &= ~bit;
789 if (oldfallback == bit) {
790 _swrast_flush( ctx );
791 tnl->Driver.Render.Start = radeonRenderStart;
792 tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
793 tnl->Driver.Render.Finish = radeonRenderFinish;
794
795 tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
796 tnl->Driver.Render.CopyPV = _tnl_copy_pv;
797 tnl->Driver.Render.Interp = _tnl_interp;
798
799 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
800 TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
801 if (rmesa->radeon.TclFallback) {
802 /* These are already done if rmesa->radeon.TclFallback goes to
803 * zero above. But not if it doesn't (RADEON_NO_TCL for
804 * example?)
805 */
806 _tnl_invalidate_vertex_state( ctx, ~0 );
807 _tnl_invalidate_vertices( ctx, ~0 );
808 RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
809 radeonChooseVertexState( ctx );
810 radeonChooseRenderState( ctx );
811 }
812 if (RADEON_DEBUG & DEBUG_FALLBACKS) {
813 fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
814 bit, getFallbackString(bit));
815 }
816 }
817 }
818 }
819
820
821 /**********************************************************************/
822 /* Initialization. */
823 /**********************************************************************/
824
825 void radeonInitSwtcl( GLcontext *ctx )
826 {
827 TNLcontext *tnl = TNL_CONTEXT(ctx);
828 r100ContextPtr rmesa = R100_CONTEXT(ctx);
829 static int firsttime = 1;
830
831 if (firsttime) {
832 init_rast_tab();
833 firsttime = 0;
834 }
835 rmesa->radeon.swtcl.emit_prediction = 0;
836
837 tnl->Driver.Render.Start = radeonRenderStart;
838 tnl->Driver.Render.Finish = radeonRenderFinish;
839 tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
840 tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
841 tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
842 tnl->Driver.Render.CopyPV = _tnl_copy_pv;
843 tnl->Driver.Render.Interp = _tnl_interp;
844
845 _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
846 RADEON_MAX_TNL_VERTEX_SIZE);
847
848 rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
849 rmesa->radeon.swtcl.RenderIndex = ~0;
850 rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
851 rmesa->radeon.swtcl.hw_primitive = 0;
852 }
853