1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Keith Whitwell <keith@tungstengraphics.com>
43 #include "swrast_setup/swrast_setup.h"
44 #include "math/m_translate.h"
46 #include "tnl/t_context.h"
47 #include "tnl/t_pipeline.h"
48 #include "tnl/t_vtx_api.h" /* for _tnl_FlushVertices */
50 #include "radeon_context.h"
51 #include "radeon_ioctl.h"
52 #include "radeon_state.h"
53 #include "radeon_swtcl.h"
54 #include "radeon_tcl.h"
57 static void flush_last_swtcl_prim( radeonContextPtr rmesa
);
59 /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */
63 /***********************************************************************
65 ***********************************************************************/
67 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
69 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \
70 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \
71 rmesa->swtcl.vertex_attr_count++; \
75 #define EMIT_PAD( N ) \
77 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \
78 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \
79 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \
80 rmesa->swtcl.vertex_attr_count++; \
83 static GLuint radeon_cp_vc_frmts
[3][2] =
85 { RADEON_CP_VC_FRMT_ST0
, RADEON_CP_VC_FRMT_ST0
| RADEON_CP_VC_FRMT_Q0
},
86 { RADEON_CP_VC_FRMT_ST1
, RADEON_CP_VC_FRMT_ST1
| RADEON_CP_VC_FRMT_Q1
},
87 { RADEON_CP_VC_FRMT_ST2
, RADEON_CP_VC_FRMT_ST2
| RADEON_CP_VC_FRMT_Q2
},
90 static void radeonSetVertexFormat( GLcontext
*ctx
)
92 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
93 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
94 struct vertex_buffer
*VB
= &tnl
->vb
;
95 GLuint index
= tnl
->render_inputs
;
102 if ( VB
->NdcPtr
!= NULL
) {
103 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
106 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->ClipPtr
;
109 assert( VB
->AttribPtr
[VERT_ATTRIB_POS
] != NULL
);
110 rmesa
->swtcl
.vertex_attr_count
= 0;
112 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
113 * build up a hardware vertex.
115 if ( !rmesa
->swtcl
.needproj
||
116 (index
& _TNL_BITS_TEX_ANY
)) { /* for projtex */
117 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_4F
,
118 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
| RADEON_CP_VC_FRMT_W0
);
122 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_3F
,
123 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
);
127 rmesa
->swtcl
.coloroffset
= offset
;
128 #if MESA_LITTLE_ENDIAN
129 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_RGBA
,
130 RADEON_CP_VC_FRMT_PKCOLOR
);
132 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_ABGR
,
133 RADEON_CP_VC_FRMT_PKCOLOR
);
137 rmesa
->swtcl
.specoffset
= 0;
138 if (index
& (_TNL_BIT_COLOR1
|_TNL_BIT_FOG
)) {
140 #if MESA_LITTLE_ENDIAN
141 if (index
& _TNL_BIT_COLOR1
) {
142 rmesa
->swtcl
.specoffset
= offset
;
143 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_RGB
,
144 RADEON_CP_VC_FRMT_PKSPEC
);
150 if (index
& _TNL_BIT_FOG
) {
151 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
152 RADEON_CP_VC_FRMT_PKSPEC
);
158 if (index
& _TNL_BIT_FOG
) {
159 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
160 RADEON_CP_VC_FRMT_PKSPEC
);
166 if (index
& _TNL_BIT_COLOR1
) {
167 rmesa
->swtcl
.specoffset
= offset
;
168 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
,
169 RADEON_CP_VC_FRMT_PKSPEC
);
177 if (index
& _TNL_BITS_TEX_ANY
) {
180 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
181 if (index
& _TNL_BIT_TEX(i
)) {
182 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
188 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_2F
,
189 radeon_cp_vc_frmts
[i
][0] );
192 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F_XYW
,
193 radeon_cp_vc_frmts
[i
][1] );
202 if ( rmesa
->tnl_index
!= index
||
203 fmt_0
!= rmesa
->swtcl
.vertex_format
) {
204 RADEON_NEWPRIM(rmesa
);
205 rmesa
->swtcl
.vertex_format
= fmt_0
;
206 rmesa
->swtcl
.vertex_size
=
207 _tnl_install_attrs( ctx
,
208 rmesa
->swtcl
.vertex_attrs
,
209 rmesa
->swtcl
.vertex_attr_count
,
211 rmesa
->swtcl
.vertex_size
/= 4;
212 rmesa
->tnl_index
= index
;
213 if (RADEON_DEBUG
& DEBUG_VERTS
)
214 fprintf( stderr
, "%s: vertex_size= %d floats\n",
215 __FUNCTION__
, rmesa
->swtcl
.vertex_size
);
220 static void radeonRenderStart( GLcontext
*ctx
)
222 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
224 radeonSetVertexFormat( ctx
);
226 if (rmesa
->dma
.flush
!= 0 &&
227 rmesa
->dma
.flush
!= flush_last_swtcl_prim
)
228 rmesa
->dma
.flush( rmesa
);
233 * Set vertex state for SW TCL. The primary purpose of this function is to
234 * determine in advance whether or not the hardware can / should do the
235 * projection divide or Mesa should do it.
237 void radeonChooseVertexState( GLcontext
*ctx
)
239 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
240 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
244 /* We must ensure that we don't do _tnl_need_projected_coords while in a
245 * rasterization fallback. As this function will be called again when we
246 * leave a rasterization fallback, we can just skip it for now.
248 if (rmesa
->Fallback
!= 0)
251 /* HW perspective divide is a win, but tiny vertex formats are a
255 if ( ((tnl
->render_inputs
& (_TNL_BITS_TEX_ANY
|_TNL_BIT_COLOR1
) ) == 0)
256 || (ctx
->_TriangleCaps
& (DD_TRI_LIGHT_TWOSIDE
|DD_TRI_UNFILLED
))) {
257 rmesa
->swtcl
.needproj
= GL_TRUE
;
258 se_coord_fmt
= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
259 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
260 RADEON_TEX1_W_ROUTING_USE_Q1
);
263 rmesa
->swtcl
.needproj
= GL_FALSE
;
264 se_coord_fmt
= (RADEON_VTX_W0_IS_NOT_1_OVER_W0
|
265 RADEON_TEX1_W_ROUTING_USE_Q1
);
268 _tnl_need_projected_coords( ctx
, rmesa
->swtcl
.needproj
);
270 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
271 RADEON_STATECHANGE( rmesa
, set
);
272 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
277 /* Flush vertices in the current dma region.
279 static void flush_last_swtcl_prim( radeonContextPtr rmesa
)
281 if (RADEON_DEBUG
& DEBUG_IOCTL
)
282 fprintf(stderr
, "%s\n", __FUNCTION__
);
284 rmesa
->dma
.flush
= NULL
;
286 if (rmesa
->dma
.current
.buf
) {
287 struct radeon_dma_region
*current
= &rmesa
->dma
.current
;
288 GLuint current_offset
= (rmesa
->radeonScreen
->gart_buffer_offset
+
289 current
->buf
->buf
->idx
* RADEON_BUFFER_SIZE
+
292 assert (!(rmesa
->swtcl
.hw_primitive
& RADEON_CP_VC_CNTL_PRIM_WALK_IND
));
294 assert (current
->start
+
295 rmesa
->swtcl
.numverts
* rmesa
->swtcl
.vertex_size
* 4 ==
298 if (rmesa
->dma
.current
.start
!= rmesa
->dma
.current
.ptr
) {
299 radeonEnsureCmdBufSpace( rmesa
, VERT_AOS_BUFSZ
+
300 rmesa
->hw
.max_state_size
+ VBUF_BUFSZ
);
302 radeonEmitVertexAOS( rmesa
,
303 rmesa
->swtcl
.vertex_size
,
306 radeonEmitVbufPrim( rmesa
,
307 rmesa
->swtcl
.vertex_format
,
308 rmesa
->swtcl
.hw_primitive
,
309 rmesa
->swtcl
.numverts
);
312 rmesa
->swtcl
.numverts
= 0;
313 current
->start
= current
->ptr
;
318 /* Alloc space in the current dma region.
321 radeonAllocDmaLowVerts( radeonContextPtr rmesa
, int nverts
, int vsize
)
323 GLuint bytes
= vsize
* nverts
;
325 if ( rmesa
->dma
.current
.ptr
+ bytes
> rmesa
->dma
.current
.end
)
326 radeonRefillCurrentDmaRegion( rmesa
);
328 if (!rmesa
->dma
.flush
) {
329 rmesa
->glCtx
->Driver
.NeedFlush
|= FLUSH_STORED_VERTICES
;
330 rmesa
->dma
.flush
= flush_last_swtcl_prim
;
333 assert( vsize
== rmesa
->swtcl
.vertex_size
* 4 );
334 assert( rmesa
->dma
.flush
== flush_last_swtcl_prim
);
335 assert (rmesa
->dma
.current
.start
+
336 rmesa
->swtcl
.numverts
* rmesa
->swtcl
.vertex_size
* 4 ==
337 rmesa
->dma
.current
.ptr
);
341 GLubyte
*head
= (GLubyte
*)(rmesa
->dma
.current
.address
+ rmesa
->dma
.current
.ptr
);
342 rmesa
->dma
.current
.ptr
+= bytes
;
343 rmesa
->swtcl
.numverts
+= nverts
;
351 * Render unclipped vertex buffers by emitting vertices directly to
352 * dma buffers. Use strip/fan hardware primitives where possible.
353 * Try to simulate missing primitives with indexed vertices.
355 #define HAVE_POINTS 1
357 #define HAVE_LINE_STRIPS 1
358 #define HAVE_TRIANGLES 1
359 #define HAVE_TRI_STRIPS 1
360 #define HAVE_TRI_STRIP_1 0
361 #define HAVE_TRI_FANS 1
363 #define HAVE_QUAD_STRIPS 0
364 #define HAVE_POLYGONS 0
365 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
368 static const GLuint hw_prim
[GL_POLYGON
+1] = {
369 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
370 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
372 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
,
373 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
374 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
,
375 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
,
382 radeonDmaPrimitive( radeonContextPtr rmesa
, GLenum prim
)
384 RADEON_NEWPRIM( rmesa
);
385 rmesa
->swtcl
.hw_primitive
= hw_prim
[prim
];
386 assert(rmesa
->dma
.current
.ptr
== rmesa
->dma
.current
.start
);
389 #define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx); (void)rmesa
390 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
391 #define FLUSH() RADEON_NEWPRIM( rmesa )
392 #define GET_CURRENT_VB_MAX_VERTS() \
393 (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4))
394 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
395 ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4))
396 #define ALLOC_VERTS( nr ) \
397 radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 )
398 #define EMIT_VERTS( ctx, j, nr, buf ) \
399 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
401 #define TAG(x) radeon_dma_##x
402 #include "tnl_dd/t_dd_dmatmp.h"
405 /**********************************************************************/
406 /* Render pipeline stage */
407 /**********************************************************************/
410 static GLboolean
radeon_run_render( GLcontext
*ctx
,
411 struct tnl_pipeline_stage
*stage
)
413 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
414 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
415 struct vertex_buffer
*VB
= &tnl
->vb
;
416 tnl_render_func
*tab
= TAG(render_tab_verts
);
419 if (rmesa
->swtcl
.indexed_verts
.buf
)
422 if (rmesa
->swtcl
.RenderIndex
!= 0 ||
423 !radeon_dma_validate_render( ctx
, VB
))
426 tnl
->Driver
.Render
.Start( ctx
);
428 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
430 GLuint prim
= VB
->Primitive
[i
].mode
;
431 GLuint start
= VB
->Primitive
[i
].start
;
432 GLuint length
= VB
->Primitive
[i
].count
;
437 if (RADEON_DEBUG
& DEBUG_PRIMS
)
438 fprintf(stderr
, "radeon_render.c: prim %s %d..%d\n",
439 _mesa_lookup_enum_by_nr(prim
& PRIM_MODE_MASK
),
440 start
, start
+length
);
443 tab
[prim
& PRIM_MODE_MASK
]( ctx
, start
, start
+ length
, prim
);
446 tnl
->Driver
.Render
.Finish( ctx
);
448 return GL_FALSE
; /* finished the pipe */
454 const struct tnl_pipeline_stage _radeon_render_stage
=
461 radeon_run_render
/* run */
465 /**************************************************************************/
467 /* Radeon texture rectangle expects coords in 0..1 range, not 0..dimension
468 * as in the extension spec. Need to translate here.
470 * Note that swrast expects 0..dimension, so if a fallback is active,
471 * don't do anything. (Maybe need to configure swrast to match hw)
473 struct texrect_stage_data
{
474 GLvector4f texcoord
[MAX_TEXTURE_UNITS
];
477 #define TEXRECT_STAGE_DATA(stage) ((struct texrect_stage_data *)stage->privatePtr)
480 static GLboolean
run_texrect_stage( GLcontext
*ctx
,
481 struct tnl_pipeline_stage
*stage
)
483 struct texrect_stage_data
*store
= TEXRECT_STAGE_DATA(stage
);
484 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
485 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
486 struct vertex_buffer
*VB
= &tnl
->vb
;
492 for (i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
493 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
& TEXTURE_RECT_BIT
) {
494 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
].CurrentRect
;
495 struct gl_texture_image
*texImage
= texObj
->Image
[0][texObj
->BaseLevel
];
496 const GLfloat iw
= 1.0/texImage
->Width
;
497 const GLfloat ih
= 1.0/texImage
->Height
;
498 GLfloat
*in
= (GLfloat
*)VB
->TexCoordPtr
[i
]->data
;
499 GLint instride
= VB
->TexCoordPtr
[i
]->stride
;
500 GLfloat (*out
)[4] = store
->texcoord
[i
].data
;
503 store
->texcoord
[i
].size
= VB
->TexCoordPtr
[i
]->size
;
504 for (j
= 0 ; j
< VB
->Count
; j
++) {
505 switch (VB
->TexCoordPtr
[i
]->size
) {
513 out
[j
][0] = in
[0] * iw
;
514 out
[j
][1] = in
[1] * ih
;
516 in
= (GLfloat
*)((GLubyte
*)in
+ instride
);
519 VB
->AttribPtr
[VERT_ATTRIB_TEX0
+i
] = VB
->TexCoordPtr
[i
] = &store
->texcoord
[i
];
527 /* Called the first time stage->run() is invoked.
529 static GLboolean
alloc_texrect_data( GLcontext
*ctx
,
530 struct tnl_pipeline_stage
*stage
)
532 struct vertex_buffer
*VB
= &TNL_CONTEXT(ctx
)->vb
;
533 struct texrect_stage_data
*store
;
536 stage
->privatePtr
= CALLOC(sizeof(*store
));
537 store
= TEXRECT_STAGE_DATA(stage
);
541 for (i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++)
542 _mesa_vector4f_alloc( &store
->texcoord
[i
], 0, VB
->Size
, 32 );
547 static void free_texrect_data( struct tnl_pipeline_stage
*stage
)
549 struct texrect_stage_data
*store
= TEXRECT_STAGE_DATA(stage
);
553 for (i
= 0 ; i
< MAX_TEXTURE_UNITS
; i
++)
554 if (store
->texcoord
[i
].data
)
555 _mesa_vector4f_free( &store
->texcoord
[i
] );
557 stage
->privatePtr
= NULL
;
561 const struct tnl_pipeline_stage _radeon_texrect_stage
=
563 "radeon texrect stage", /* name */
572 /**************************************************************************/
575 static const GLuint reduced_hw_prim
[GL_POLYGON
+1] = {
576 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
577 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
578 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
579 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
580 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
581 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
582 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
583 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
584 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
585 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
588 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
);
589 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
);
590 static void radeonResetLineStipple( GLcontext
*ctx
);
593 /***********************************************************************
594 * Emit primitives as inline vertices *
595 ***********************************************************************/
599 #define CTX_ARG radeonContextPtr rmesa
600 #define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size
601 #define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 )
604 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
605 const char *radeonverts = (char *)rmesa->swtcl.verts;
606 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
607 #define VERTEX radeonVertex
609 #define TAG(x) radeon_##x
610 #include "tnl_dd/t_dd_triemit.h"
613 /***********************************************************************
614 * Macros for t_dd_tritmp.h to draw basic primitives *
615 ***********************************************************************/
617 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
618 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
619 #define LINE( a, b ) radeon_line( rmesa, a, b )
620 #define POINT( a ) radeon_point( rmesa, a )
622 /***********************************************************************
623 * Build render functions from dd templates *
624 ***********************************************************************/
626 #define RADEON_TWOSIDE_BIT 0x01
627 #define RADEON_UNFILLED_BIT 0x02
628 #define RADEON_MAX_TRIFUNC 0x08
632 tnl_points_func points
;
634 tnl_triangle_func triangle
;
636 } rast_tab
[RADEON_MAX_TRIFUNC
];
639 #define DO_FALLBACK 0
641 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
642 #define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
648 #define DO_FULL_QUAD 1
652 #define HAVE_BACK_COLORS 0
653 #define HAVE_HW_FLATSHADE 1
656 #define DEPTH_SCALE 1.0
657 #define UNFILLED_TRI unfilled_tri
658 #define UNFILLED_QUAD unfilled_quad
659 #define VERT_X(_v) _v->v.x
660 #define VERT_Y(_v) _v->v.y
661 #define VERT_Z(_v) _v->v.z
662 #define AREA_IS_CCW( a ) (a < 0)
663 #define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int)))
665 #define VERT_SET_RGBA( v, c ) \
667 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
668 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
669 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
670 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
671 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
674 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
676 #define VERT_SET_SPEC( v, c ) \
679 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
680 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
681 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
682 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
685 #define VERT_COPY_SPEC( v0, v1 ) \
688 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
689 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
690 spec0->red = spec1->red; \
691 spec0->green = spec1->green; \
692 spec0->blue = spec1->blue; \
696 /* These don't need LE32_TO_CPU() as they used to save and restore
697 * colors which are already in the correct format.
699 #define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
700 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
701 #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
702 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
708 #define LOCAL_VARS(n) \
709 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
710 GLuint color[n], spec[n]; \
711 GLuint coloroffset = rmesa->swtcl.coloroffset; \
712 GLuint specoffset = rmesa->swtcl.specoffset; \
713 (void) color; (void) spec; (void) coloroffset; (void) specoffset;
715 /***********************************************************************
716 * Helpers for rendering unfilled primitives *
717 ***********************************************************************/
719 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
720 #define RENDER_PRIMITIVE rmesa->swtcl.render_primitive
723 #include "tnl_dd/t_dd_unfilled.h"
727 /***********************************************************************
728 * Generate GL render functions *
729 ***********************************************************************/
734 #include "tnl_dd/t_dd_tritmp.h"
736 #define IND (RADEON_TWOSIDE_BIT)
737 #define TAG(x) x##_twoside
738 #include "tnl_dd/t_dd_tritmp.h"
740 #define IND (RADEON_UNFILLED_BIT)
741 #define TAG(x) x##_unfilled
742 #include "tnl_dd/t_dd_tritmp.h"
744 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
745 #define TAG(x) x##_twoside_unfilled
746 #include "tnl_dd/t_dd_tritmp.h"
749 static void init_rast_tab( void )
754 init_twoside_unfilled();
757 /**********************************************************************/
758 /* Render unclipped begin/end objects */
759 /**********************************************************************/
761 #define RENDER_POINTS( start, count ) \
762 for ( ; start < count ; start++) \
763 radeon_point( rmesa, VERT(start) )
764 #define RENDER_LINE( v0, v1 ) \
765 radeon_line( rmesa, VERT(v0), VERT(v1) )
766 #define RENDER_TRI( v0, v1, v2 ) \
767 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
768 #define RENDER_QUAD( v0, v1, v2, v3 ) \
769 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
771 #define INIT(x) do { \
772 radeonRenderPrimitive( ctx, x ); \
776 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
777 const GLuint vertsize = rmesa->swtcl.vertex_size; \
778 const char *radeonverts = (char *)rmesa->swtcl.verts; \
779 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
780 const GLboolean stipple = ctx->Line.StippleFlag; \
781 (void) elt; (void) stipple;
782 #define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx );
783 #define RESET_OCCLUSION
784 #define PRESERVE_VB_DEFS
786 #define TAG(x) radeon_##x##_verts
787 #include "tnl/t_vb_rendertmp.h"
790 #define TAG(x) radeon_##x##_elts
791 #define ELT(x) elt[x]
792 #include "tnl/t_vb_rendertmp.h"
796 /**********************************************************************/
797 /* Choose render functions */
798 /**********************************************************************/
800 void radeonChooseRenderState( GLcontext
*ctx
)
802 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
803 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
805 GLuint flags
= ctx
->_TriangleCaps
;
807 if (!rmesa
->TclFallback
|| rmesa
->Fallback
)
810 if (flags
& DD_TRI_LIGHT_TWOSIDE
) index
|= RADEON_TWOSIDE_BIT
;
811 if (flags
& DD_TRI_UNFILLED
) index
|= RADEON_UNFILLED_BIT
;
813 if (index
!= rmesa
->swtcl
.RenderIndex
) {
814 tnl
->Driver
.Render
.Points
= rast_tab
[index
].points
;
815 tnl
->Driver
.Render
.Line
= rast_tab
[index
].line
;
816 tnl
->Driver
.Render
.ClippedLine
= rast_tab
[index
].line
;
817 tnl
->Driver
.Render
.Triangle
= rast_tab
[index
].triangle
;
818 tnl
->Driver
.Render
.Quad
= rast_tab
[index
].quad
;
821 tnl
->Driver
.Render
.PrimTabVerts
= radeon_render_tab_verts
;
822 tnl
->Driver
.Render
.PrimTabElts
= radeon_render_tab_elts
;
823 tnl
->Driver
.Render
.ClippedPolygon
= radeon_fast_clipped_poly
;
825 tnl
->Driver
.Render
.PrimTabVerts
= _tnl_render_tab_verts
;
826 tnl
->Driver
.Render
.PrimTabElts
= _tnl_render_tab_elts
;
827 tnl
->Driver
.Render
.ClippedPolygon
= _tnl_RenderClippedPolygon
;
830 rmesa
->swtcl
.RenderIndex
= index
;
835 /**********************************************************************/
836 /* High level hooks for t_vb_render.c */
837 /**********************************************************************/
840 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
)
842 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
844 if (rmesa
->swtcl
.hw_primitive
!= hwprim
) {
845 RADEON_NEWPRIM( rmesa
);
846 rmesa
->swtcl
.hw_primitive
= hwprim
;
850 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
)
852 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
853 rmesa
->swtcl
.render_primitive
= prim
;
854 if (prim
< GL_TRIANGLES
|| !(ctx
->_TriangleCaps
& DD_TRI_UNFILLED
))
855 radeonRasterPrimitive( ctx
, reduced_hw_prim
[prim
] );
858 static void radeonRenderFinish( GLcontext
*ctx
)
862 static void radeonResetLineStipple( GLcontext
*ctx
)
864 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
865 RADEON_STATECHANGE( rmesa
, lin
);
869 /**********************************************************************/
870 /* Transition to/from hardware rasterization. */
871 /**********************************************************************/
873 static const char * const fallbackStrings
[] = {
875 "glDrawBuffer(GL_FRONT_AND_BACK)",
876 "glEnable(GL_STENCIL) without hw stencil buffer",
877 "glRenderMode(selection or feedback)",
881 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
885 static const char *getFallbackString(GLuint bit
)
892 return fallbackStrings
[i
];
896 void radeonFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
898 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
899 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
900 GLuint oldfallback
= rmesa
->Fallback
;
903 rmesa
->Fallback
|= bit
;
904 if (oldfallback
== 0) {
905 RADEON_FIREVERTICES( rmesa
);
906 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_TRUE
);
907 _swsetup_Wakeup( ctx
);
908 rmesa
->swtcl
.RenderIndex
= ~0;
909 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
910 fprintf(stderr
, "Radeon begin rasterization fallback: 0x%x %s\n",
911 bit
, getFallbackString(bit
));
916 rmesa
->Fallback
&= ~bit
;
917 if (oldfallback
== bit
) {
918 _swrast_flush( ctx
);
919 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
920 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
921 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
923 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
924 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
925 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
927 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
928 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_FALSE
);
929 if (rmesa
->TclFallback
) {
930 /* These are already done if rmesa->TclFallback goes to
931 * zero above. But not if it doesn't (RADEON_NO_TCL for
934 radeonChooseVertexState( ctx
);
935 radeonChooseRenderState( ctx
);
937 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
938 fprintf(stderr
, "Radeon end rasterization fallback: 0x%x %s\n",
939 bit
, getFallbackString(bit
));
946 void radeonFlushVertices( GLcontext
*ctx
, GLuint flags
)
948 _tnl_FlushVertices( ctx
, flags
);
950 if (flags
& FLUSH_STORED_VERTICES
)
951 RADEON_NEWPRIM( RADEON_CONTEXT( ctx
) );
954 /**********************************************************************/
955 /* Initialization. */
956 /**********************************************************************/
958 void radeonInitSwtcl( GLcontext
*ctx
)
960 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
961 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
962 static int firsttime
= 1;
969 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
970 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
971 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
972 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
973 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
974 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
975 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
977 _tnl_init_vertices( ctx
, ctx
->Const
.MaxArrayLockSize
+ 12,
978 RADEON_MAX_TNL_VERTEX_SIZE
);
980 rmesa
->swtcl
.verts
= (GLubyte
*)tnl
->clipspace
.vertex_buf
;
981 rmesa
->swtcl
.RenderIndex
= ~0;
982 rmesa
->swtcl
.render_primitive
= GL_TRIANGLES
;
983 rmesa
->swtcl
.hw_primitive
= 0;
987 void radeonDestroySwtcl( GLcontext
*ctx
)
989 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
991 if (rmesa
->swtcl
.indexed_verts
.buf
)
992 radeonReleaseDmaRegion( rmesa
, &rmesa
->swtcl
.indexed_verts
,