src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      VA Linux Systems Inc., Fremont, California.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Keith Whitwell <keith@tungstengraphics.com>
  34  */
  35
  36 #include "glheader.h"
  37 #include "mtypes.h"
  38 #include "colormac.h"
  39 #include "enums.h"
  40 #include "imports.h"
  41 #include "macros.h"
  42
  43 #include "swrast_setup/swrast_setup.h"
  44 #include "math/m_translate.h"
  45 #include "tnl/tnl.h"
  46 #include "tnl/t_context.h"
  47 #include "tnl/t_pipeline.h"
  48 #include "tnl/t_vtx_api.h"      /* for _tnl_FlushVertices */
  49
  50 #include "radeon_context.h"
  51 #include "radeon_ioctl.h"
  52 #include "radeon_state.h"
  53 #include "radeon_swtcl.h"
  54 #include "radeon_tcl.h"
  55
  56
  57 static void flush_last_swtcl_prim( radeonContextPtr rmesa  );
  58
  59 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  62
  63 /***********************************************************************
  64  *                         Initialization
  65  ***********************************************************************/
  66
  67 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  68 do {                                                                    \
  69    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR);   \
  70    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE);  \
  71    rmesa->swtcl.vertex_attr_count++;                                    \
  72    fmt_0 |= F0;                                                         \
  73 } while (0)
  74
  75 #define EMIT_PAD( N )                                                   \
  76 do {                                                                    \
  77    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0;                \
  78    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \
  79    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N);              \
  80    rmesa->swtcl.vertex_attr_count++;                                    \
  81 } while (0)
  82
  83 static GLuint radeon_cp_vc_frmts[3][2] =
  84 {
  85    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  86    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  87    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  88 };
  89
  90 static void radeonSetVertexFormat( GLcontext *ctx )
  91 {
  92    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
  93    TNLcontext *tnl = TNL_CONTEXT(ctx);
  94    struct vertex_buffer *VB = &tnl->vb;
  95    GLuint index = tnl->render_inputs;
  96    int fmt_0 = 0;
  97    int offset = 0;
  98
  99
 100    /* Important:
 101     */
 102    if ( VB->NdcPtr != NULL ) {
 103       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 104    }
 105    else {
 106       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 107    }
 108
 109    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 110    rmesa->swtcl.vertex_attr_count = 0;
 111
 112    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 113     * build up a hardware vertex.
 114     */
 115    if ( !rmesa->swtcl.needproj ||
 116         (index & _TNL_BITS_TEX_ANY)) {  /* for projtex */
 117       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 118                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 119       offset = 4;
 120    }
 121    else {
 122       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 123                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 124       offset = 3;
 125    }
 126
 127    rmesa->swtcl.coloroffset = offset;
 128 #if MESA_LITTLE_ENDIAN
 129    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 130               RADEON_CP_VC_FRMT_PKCOLOR );
 131 #else
 132    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 133               RADEON_CP_VC_FRMT_PKCOLOR );
 134 #endif
 135    offset += 1;
 136
 137    rmesa->swtcl.specoffset = 0;
 138    if (index & (_TNL_BIT_COLOR1|_TNL_BIT_FOG)) {
 139
 140 #if MESA_LITTLE_ENDIAN
 141       if (index & _TNL_BIT_COLOR1) {
 142          rmesa->swtcl.specoffset = offset;
 143          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 144                     RADEON_CP_VC_FRMT_PKSPEC );
 145       }
 146       else {
 147          EMIT_PAD( 3 );
 148       }
 149
 150       if (index & _TNL_BIT_FOG) {
 151          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 152                     RADEON_CP_VC_FRMT_PKSPEC );
 153       }
 154       else {
 155          EMIT_PAD( 1 );
 156       }
 157 #else
 158       if (index & _TNL_BIT_FOG) {
 159          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 160                     RADEON_CP_VC_FRMT_PKSPEC );
 161       }
 162       else {
 163          EMIT_PAD( 1 );
 164       }
 165
 166       if (index & _TNL_BIT_COLOR1) {
 167          rmesa->swtcl.specoffset = offset;
 168          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 169                     RADEON_CP_VC_FRMT_PKSPEC );
 170       }
 171       else {
 172          EMIT_PAD( 3 );
 173       }
 174 #endif
 175    }
 176
 177    if (index & _TNL_BITS_TEX_ANY) {
 178       int i;
 179
 180       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 181          if (index & _TNL_BIT_TEX(i)) {
 182             GLuint sz = VB->TexCoordPtr[i]->size;
 183
 184             switch (sz) {
 185             case 1:
 186             case 2:
 187             case 3:
 188                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 189                           radeon_cp_vc_frmts[i][0] );
 190                break;
 191             case 4:
 192                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 193                           radeon_cp_vc_frmts[i][1] );
 194                break;
 195             default:
 196                continue;
 197             };
 198          }
 199       }
 200    }
 201
 202    if ( rmesa->tnl_index != index ||
 203         fmt_0 != rmesa->swtcl.vertex_format) {
 204       RADEON_NEWPRIM(rmesa);
 205       rmesa->swtcl.vertex_format = fmt_0;
 206       rmesa->swtcl.vertex_size =
 207           _tnl_install_attrs( ctx,
 208                               rmesa->swtcl.vertex_attrs,
 209                               rmesa->swtcl.vertex_attr_count,
 210                               NULL, 0 );
 211       rmesa->swtcl.vertex_size /= 4;
 212       rmesa->tnl_index = index;
 213       if (RADEON_DEBUG & DEBUG_VERTS)
 214          fprintf( stderr, "%s: vertex_size= %d floats\n",
 215                   __FUNCTION__, rmesa->swtcl.vertex_size);
 216    }
 217 }
 218
 219
 220 static void radeonRenderStart( GLcontext *ctx )
 221 {
 222    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 223
 224    radeonSetVertexFormat( ctx );
 225
 226    if (rmesa->dma.flush != 0 &&
 227        rmesa->dma.flush != flush_last_swtcl_prim)
 228       rmesa->dma.flush( rmesa );
 229 }
 230
 231
 232 /**
 233  * Set vertex state for SW TCL.  The primary purpose of this function is to
 234  * determine in advance whether or not the hardware can / should do the
 235  * projection divide or Mesa should do it.
 236  */
 237 void radeonChooseVertexState( GLcontext *ctx )
 238 {
 239    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 240    TNLcontext *tnl = TNL_CONTEXT(ctx);
 241
 242    GLuint se_coord_fmt;
 243
 244    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 245     * rasterization fallback.  As this function will be called again when we
 246     * leave a rasterization fallback, we can just skip it for now.
 247     */
 248    if (rmesa->Fallback != 0)
 249       return;
 250
 251    /* HW perspective divide is a win, but tiny vertex formats are a
 252     * bigger one.
 253     */
 254
 255    if ( ((tnl->render_inputs & (_TNL_BITS_TEX_ANY|_TNL_BIT_COLOR1) ) == 0)
 256         || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 257       rmesa->swtcl.needproj = GL_TRUE;
 258       se_coord_fmt = (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 259                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 260                       RADEON_TEX1_W_ROUTING_USE_Q1);
 261    }
 262    else {
 263       rmesa->swtcl.needproj = GL_FALSE;
 264       se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
 265                       RADEON_TEX1_W_ROUTING_USE_Q1);
 266    }
 267
 268    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 269
 270    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 271       RADEON_STATECHANGE( rmesa, set );
 272       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 273    }
 274 }
 275
 276
 277 /* Flush vertices in the current dma region.
 278  */
 279 static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
 280 {
 281    if (RADEON_DEBUG & DEBUG_IOCTL)
 282       fprintf(stderr, "%s\n", __FUNCTION__);
 283
 284    rmesa->dma.flush = NULL;
 285
 286    if (rmesa->dma.current.buf) {
 287       struct radeon_dma_region *current = &rmesa->dma.current;
 288       GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset +
 289                                current->buf->buf->idx * RADEON_BUFFER_SIZE +
 290                                current->start);
 291
 292       assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
 293
 294       assert (current->start +
 295               rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 296               current->ptr);
 297
 298       if (rmesa->dma.current.start != rmesa->dma.current.ptr) {
 299          radeonEnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ +
 300                                   rmesa->hw.max_state_size + VBUF_BUFSZ );
 301
 302          radeonEmitVertexAOS( rmesa,
 303                               rmesa->swtcl.vertex_size,
 304                               current_offset);
 305
 306          radeonEmitVbufPrim( rmesa,
 307                              rmesa->swtcl.vertex_format,
 308                              rmesa->swtcl.hw_primitive,
 309                              rmesa->swtcl.numverts);
 310       }
 311
 312       rmesa->swtcl.numverts = 0;
 313       current->start = current->ptr;
 314    }
 315 }
 316
 317
 318 /* Alloc space in the current dma region.
 319  */
 320 static INLINE void *
 321 radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize )
 322 {
 323    GLuint bytes = vsize * nverts;
 324
 325    if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end )
 326       radeonRefillCurrentDmaRegion( rmesa );
 327
 328    if (!rmesa->dma.flush) {
 329       rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 330       rmesa->dma.flush = flush_last_swtcl_prim;
 331    }
 332
 333    assert( vsize == rmesa->swtcl.vertex_size * 4 );
 334    assert( rmesa->dma.flush == flush_last_swtcl_prim );
 335    assert (rmesa->dma.current.start +
 336            rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 337            rmesa->dma.current.ptr);
 338
 339
 340    {
 341       GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr);
 342       rmesa->dma.current.ptr += bytes;
 343       rmesa->swtcl.numverts += nverts;
 344       return head;
 345    }
 346
 347 }
 348
 349
 350 /*
 351  * Render unclipped vertex buffers by emitting vertices directly to
 352  * dma buffers.  Use strip/fan hardware primitives where possible.
 353  * Try to simulate missing primitives with indexed vertices.
 354  */
 355 #define HAVE_POINTS      1
 356 #define HAVE_LINES       1
 357 #define HAVE_LINE_STRIPS 1
 358 #define HAVE_TRIANGLES   1
 359 #define HAVE_TRI_STRIPS  1
 360 #define HAVE_TRI_STRIP_1 0
 361 #define HAVE_TRI_FANS    1
 362 #define HAVE_QUADS       0
 363 #define HAVE_QUAD_STRIPS 0
 364 #define HAVE_POLYGONS    0
 365 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 366 #define HAVE_ELTS        0
 367
 368 static const GLuint hw_prim[GL_POLYGON+1] = {
 369    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 370    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 371    0,
 372    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 373    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 374    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 375    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 376    0,
 377    0,
 378    0
 379 };
 380
 381 static INLINE void
 382 radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim )
 383 {
 384    RADEON_NEWPRIM( rmesa );
 385    rmesa->swtcl.hw_primitive = hw_prim[prim];
 386    assert(rmesa->dma.current.ptr == rmesa->dma.current.start);
 387 }
 388
 389 #define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx); (void)rmesa
 390 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 391 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 392 #define GET_CURRENT_VB_MAX_VERTS() \
 393   (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4))
 394 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 395   ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4))
 396 #define ALLOC_VERTS( nr ) \
 397   radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 )
 398 #define EMIT_VERTS( ctx, j, nr, buf ) \
 399   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 400
 401 #define TAG(x) radeon_dma_##x
 402 #include "tnl_dd/t_dd_dmatmp.h"
 403
 404
 405 /**********************************************************************/
 406 /*                          Render pipeline stage                     */
 407 /**********************************************************************/
 408
 409
 410 static GLboolean radeon_run_render( GLcontext *ctx,
 411                                     struct tnl_pipeline_stage *stage )
 412 {
 413    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 414    TNLcontext *tnl = TNL_CONTEXT(ctx);
 415    struct vertex_buffer *VB = &tnl->vb;
 416    tnl_render_func *tab = TAG(render_tab_verts);
 417    GLuint i;
 418
 419    if (rmesa->swtcl.indexed_verts.buf)
 420       RELEASE_ELT_VERTS();
 421
 422    if (rmesa->swtcl.RenderIndex != 0 ||
 423        !radeon_dma_validate_render( ctx, VB ))
 424       return GL_TRUE;
 425
 426    tnl->Driver.Render.Start( ctx );
 427
 428    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 429    {
 430       GLuint prim = VB->Primitive[i].mode;
 431       GLuint start = VB->Primitive[i].start;
 432       GLuint length = VB->Primitive[i].count;
 433
 434       if (!length)
 435          continue;
 436
 437       if (RADEON_DEBUG & DEBUG_PRIMS)
 438          fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
 439                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 440                  start, start+length);
 441
 442       if (length)
 443          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 444    }
 445
 446    tnl->Driver.Render.Finish( ctx );
 447
 448    return GL_FALSE;             /* finished the pipe */
 449 }
 450
 451
 452
 453
 454 const struct tnl_pipeline_stage _radeon_render_stage =
 455 {
 456    "radeon render",
 457    NULL,
 458    NULL,
 459    NULL,
 460    NULL,
 461    radeon_run_render            /* run */
 462 };
 463
 464
 465 /**************************************************************************/
 466
 467 /* Radeon texture rectangle expects coords in 0..1 range, not 0..dimension
 468  * as in the extension spec.  Need to translate here.
 469  *
 470  * Note that swrast expects 0..dimension, so if a fallback is active,
 471  * don't do anything.  (Maybe need to configure swrast to match hw)
 472  */
 473 struct texrect_stage_data {
 474    GLvector4f texcoord[MAX_TEXTURE_UNITS];
 475 };
 476
 477 #define TEXRECT_STAGE_DATA(stage) ((struct texrect_stage_data *)stage->privatePtr)
 478
 479
 480 static GLboolean run_texrect_stage( GLcontext *ctx,
 481                                     struct tnl_pipeline_stage *stage )
 482 {
 483    struct texrect_stage_data *store = TEXRECT_STAGE_DATA(stage);
 484    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 485    TNLcontext *tnl = TNL_CONTEXT(ctx);
 486    struct vertex_buffer *VB = &tnl->vb;
 487    GLuint i;
 488
 489    if (rmesa->Fallback)
 490       return GL_TRUE;
 491
 492    for (i = 0 ; i < ctx->Const.MaxTextureUnits ; i++) {
 493       if (ctx->Texture.Unit[i]._ReallyEnabled & TEXTURE_RECT_BIT) {
 494          struct gl_texture_object *texObj = ctx->Texture.Unit[i].CurrentRect;
 495          struct gl_texture_image *texImage = texObj->Image[0][texObj->BaseLevel];
 496          const GLfloat iw = 1.0/texImage->Width;
 497          const GLfloat ih = 1.0/texImage->Height;
 498          GLfloat *in = (GLfloat *)VB->TexCoordPtr[i]->data;
 499          GLint instride = VB->TexCoordPtr[i]->stride;
 500          GLfloat (*out)[4] = store->texcoord[i].data;
 501          GLint j;
 502
 503          store->texcoord[i].size = VB->TexCoordPtr[i]->size;
 504          for (j = 0 ; j < VB->Count ; j++) {
 505             switch (VB->TexCoordPtr[i]->size) {
 506             case 4:
 507                out[j][3] = in[3];
 508             /* fallthrough */
 509             case 3:
 510                out[j][2] = in[2];
 511             /* fallthrough */
 512             default:
 513                out[j][0] = in[0] * iw;
 514                out[j][1] = in[1] * ih;
 515             }
 516             in = (GLfloat *)((GLubyte *)in + instride);
 517          }
 518
 519          VB->AttribPtr[VERT_ATTRIB_TEX0+i] = VB->TexCoordPtr[i] = &store->texcoord[i];
 520       }
 521    }
 522
 523    return GL_TRUE;
 524 }
 525
 526
 527 /* Called the first time stage->run() is invoked.
 528  */
 529 static GLboolean alloc_texrect_data( GLcontext *ctx,
 530                                      struct tnl_pipeline_stage *stage )
 531 {
 532    struct vertex_buffer *VB = &TNL_CONTEXT(ctx)->vb;
 533    struct texrect_stage_data *store;
 534    GLuint i;
 535
 536    stage->privatePtr = CALLOC(sizeof(*store));
 537    store = TEXRECT_STAGE_DATA(stage);
 538    if (!store)
 539       return GL_FALSE;
 540
 541    for (i = 0 ; i < ctx->Const.MaxTextureUnits ; i++)
 542       _mesa_vector4f_alloc( &store->texcoord[i], 0, VB->Size, 32 );
 543
 544    return GL_TRUE;
 545 }
 546
 547 static void free_texrect_data( struct tnl_pipeline_stage *stage )
 548 {
 549    struct texrect_stage_data *store = TEXRECT_STAGE_DATA(stage);
 550    GLuint i;
 551
 552    if (store) {
 553       for (i = 0 ; i < MAX_TEXTURE_UNITS ; i++)
 554          if (store->texcoord[i].data)
 555             _mesa_vector4f_free( &store->texcoord[i] );
 556       FREE( store );
 557       stage->privatePtr = NULL;
 558    }
 559 }
 560
 561 const struct tnl_pipeline_stage _radeon_texrect_stage =
 562 {
 563    "radeon texrect stage",                      /* name */
 564    NULL,
 565    alloc_texrect_data,
 566    free_texrect_data,
 567    NULL,
 568    run_texrect_stage
 569 };
 570
 571
 572 /**************************************************************************/
 573
 574
 575 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 576    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 577    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 578    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 579    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 580    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 581    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 582    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 583    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 584    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 585    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 586 };
 587
 588 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
 589 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
 590 static void radeonResetLineStipple( GLcontext *ctx );
 591
 592
 593 /***********************************************************************
 594  *                    Emit primitives as inline vertices               *
 595  ***********************************************************************/
 596
 597 #undef LOCAL_VARS
 598 #undef ALLOC_VERTS
 599 #define CTX_ARG radeonContextPtr rmesa
 600 #define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size
 601 #define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 )
 602 #undef LOCAL_VARS
 603 #define LOCAL_VARS                                              \
 604    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                \
 605    const char *radeonverts = (char *)rmesa->swtcl.verts;
 606 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 607 #define VERTEX radeonVertex
 608 #undef TAG
 609 #define TAG(x) radeon_##x
 610 #include "tnl_dd/t_dd_triemit.h"
 611
 612
 613 /***********************************************************************
 614  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 615  ***********************************************************************/
 616
 617 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 618 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 619 #define LINE( a, b )       radeon_line( rmesa, a, b )
 620 #define POINT( a )         radeon_point( rmesa, a )
 621
 622 /***********************************************************************
 623  *              Build render functions from dd templates               *
 624  ***********************************************************************/
 625
 626 #define RADEON_TWOSIDE_BIT      0x01
 627 #define RADEON_UNFILLED_BIT     0x02
 628 #define RADEON_MAX_TRIFUNC      0x08
 629
 630
 631 static struct {
 632    tnl_points_func              points;
 633    tnl_line_func                line;
 634    tnl_triangle_func    triangle;
 635    tnl_quad_func                quad;
 636 } rast_tab[RADEON_MAX_TRIFUNC];
 637
 638
 639 #define DO_FALLBACK  0
 640 #define DO_OFFSET    0
 641 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 642 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 643 #define DO_FLAT      0
 644 #define DO_TRI       1
 645 #define DO_QUAD      1
 646 #define DO_LINE      1
 647 #define DO_POINTS    1
 648 #define DO_FULL_QUAD 1
 649
 650 #define HAVE_RGBA   1
 651 #define HAVE_SPEC   1
 652 #define HAVE_BACK_COLORS  0
 653 #define HAVE_HW_FLATSHADE 1
 654 #define TAB rast_tab
 655
 656 #define DEPTH_SCALE 1.0
 657 #define UNFILLED_TRI unfilled_tri
 658 #define UNFILLED_QUAD unfilled_quad
 659 #define VERT_X(_v) _v->v.x
 660 #define VERT_Y(_v) _v->v.y
 661 #define VERT_Z(_v) _v->v.z
 662 #define AREA_IS_CCW( a ) (a < 0)
 663 #define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int)))
 664
 665 #define VERT_SET_RGBA( v, c )                                   \
 666 do {                                                            \
 667    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 668    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 669    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 670    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 671    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 672 } while (0)
 673
 674 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 675
 676 #define VERT_SET_SPEC( v, c )                                   \
 677 do {                                                            \
 678    if (specoffset) {                                            \
 679       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 680       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 681       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 682       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 683    }                                                            \
 684 } while (0)
 685 #define VERT_COPY_SPEC( v0, v1 )                        \
 686 do {                                                    \
 687    if (specoffset) {                                    \
 688       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 689       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 690       spec0->red   = spec1->red;        \
 691       spec0->green = spec1->green;      \
 692       spec0->blue  = spec1->blue;       \
 693    }                                                    \
 694 } while (0)
 695
 696 /* These don't need LE32_TO_CPU() as they used to save and restore
 697  * colors which are already in the correct format.
 698  */
 699 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 700 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 701 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 702 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 703
 704 #undef LOCAL_VARS
 705 #undef TAG
 706 #undef INIT
 707
 708 #define LOCAL_VARS(n)                                                   \
 709    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                        \
 710    GLuint color[n], spec[n];                                            \
 711    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 712    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 713    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 714
 715 /***********************************************************************
 716  *                Helpers for rendering unfilled primitives            *
 717  ***********************************************************************/
 718
 719 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 720 #define RENDER_PRIMITIVE rmesa->swtcl.render_primitive
 721 #undef TAG
 722 #define TAG(x) x
 723 #include "tnl_dd/t_dd_unfilled.h"
 724 #undef IND
 725
 726
 727 /***********************************************************************
 728  *                      Generate GL render functions                   *
 729  ***********************************************************************/
 730
 731
 732 #define IND (0)
 733 #define TAG(x) x
 734 #include "tnl_dd/t_dd_tritmp.h"
 735
 736 #define IND (RADEON_TWOSIDE_BIT)
 737 #define TAG(x) x##_twoside
 738 #include "tnl_dd/t_dd_tritmp.h"
 739
 740 #define IND (RADEON_UNFILLED_BIT)
 741 #define TAG(x) x##_unfilled
 742 #include "tnl_dd/t_dd_tritmp.h"
 743
 744 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 745 #define TAG(x) x##_twoside_unfilled
 746 #include "tnl_dd/t_dd_tritmp.h"
 747
 748
 749 static void init_rast_tab( void )
 750 {
 751    init();
 752    init_twoside();
 753    init_unfilled();
 754    init_twoside_unfilled();
 755 }
 756
 757 /**********************************************************************/
 758 /*               Render unclipped begin/end objects                   */
 759 /**********************************************************************/
 760
 761 #define RENDER_POINTS( start, count )           \
 762    for ( ; start < count ; start++)             \
 763       radeon_point( rmesa, VERT(start) )
 764 #define RENDER_LINE( v0, v1 ) \
 765    radeon_line( rmesa, VERT(v0), VERT(v1) )
 766 #define RENDER_TRI( v0, v1, v2 )  \
 767    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 768 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 769    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 770 #undef INIT
 771 #define INIT(x) do {                                    \
 772    radeonRenderPrimitive( ctx, x );                     \
 773 } while (0)
 774 #undef LOCAL_VARS
 775 #define LOCAL_VARS                                              \
 776    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                \
 777    const GLuint vertsize = rmesa->swtcl.vertex_size;            \
 778    const char *radeonverts = (char *)rmesa->swtcl.verts;                \
 779    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 780    const GLboolean stipple = ctx->Line.StippleFlag;             \
 781    (void) elt; (void) stipple;
 782 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 783 #define RESET_OCCLUSION
 784 #define PRESERVE_VB_DEFS
 785 #define ELT(x) (x)
 786 #define TAG(x) radeon_##x##_verts
 787 #include "tnl/t_vb_rendertmp.h"
 788 #undef ELT
 789 #undef TAG
 790 #define TAG(x) radeon_##x##_elts
 791 #define ELT(x) elt[x]
 792 #include "tnl/t_vb_rendertmp.h"
 793
 794
 795
 796 /**********************************************************************/
 797 /*                    Choose render functions                         */
 798 /**********************************************************************/
 799
 800 void radeonChooseRenderState( GLcontext *ctx )
 801 {
 802    TNLcontext *tnl = TNL_CONTEXT(ctx);
 803    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 804    GLuint index = 0;
 805    GLuint flags = ctx->_TriangleCaps;
 806
 807    if (!rmesa->TclFallback || rmesa->Fallback)
 808       return;
 809
 810    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 811    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 812
 813    if (index != rmesa->swtcl.RenderIndex) {
 814       tnl->Driver.Render.Points = rast_tab[index].points;
 815       tnl->Driver.Render.Line = rast_tab[index].line;
 816       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 817       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 818       tnl->Driver.Render.Quad = rast_tab[index].quad;
 819
 820       if (index == 0) {
 821          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 822          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 823          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 824       } else {
 825          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 826          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 827          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 828       }
 829
 830       rmesa->swtcl.RenderIndex = index;
 831    }
 832 }
 833
 834
 835 /**********************************************************************/
 836 /*                 High level hooks for t_vb_render.c                 */
 837 /**********************************************************************/
 838
 839
 840 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 841 {
 842    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 843
 844    if (rmesa->swtcl.hw_primitive != hwprim) {
 845       RADEON_NEWPRIM( rmesa );
 846       rmesa->swtcl.hw_primitive = hwprim;
 847    }
 848 }
 849
 850 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 851 {
 852    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 853    rmesa->swtcl.render_primitive = prim;
 854    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 855       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 856 }
 857
 858 static void radeonRenderFinish( GLcontext *ctx )
 859 {
 860 }
 861
 862 static void radeonResetLineStipple( GLcontext *ctx )
 863 {
 864    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 865    RADEON_STATECHANGE( rmesa, lin );
 866 }
 867
 868
 869 /**********************************************************************/
 870 /*           Transition to/from hardware rasterization.               */
 871 /**********************************************************************/
 872
 873 static const char * const fallbackStrings[] = {
 874    "Texture mode",
 875    "glDrawBuffer(GL_FRONT_AND_BACK)",
 876    "glEnable(GL_STENCIL) without hw stencil buffer",
 877    "glRenderMode(selection or feedback)",
 878    "glBlendEquation",
 879    "glBlendFunc",
 880    "RADEON_NO_RAST",
 881    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 882 };
 883
 884
 885 static const char *getFallbackString(GLuint bit)
 886 {
 887    int i = 0;
 888    while (bit > 1) {
 889       i++;
 890       bit >>= 1;
 891    }
 892    return fallbackStrings[i];
 893 }
 894
 895
 896 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 897 {
 898    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 899    TNLcontext *tnl = TNL_CONTEXT(ctx);
 900    GLuint oldfallback = rmesa->Fallback;
 901
 902    if (mode) {
 903       rmesa->Fallback |= bit;
 904       if (oldfallback == 0) {
 905          RADEON_FIREVERTICES( rmesa );
 906          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 907          _swsetup_Wakeup( ctx );
 908          rmesa->swtcl.RenderIndex = ~0;
 909          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 910             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 911                     bit, getFallbackString(bit));
 912          }
 913       }
 914    }
 915    else {
 916       rmesa->Fallback &= ~bit;
 917       if (oldfallback == bit) {
 918          _swrast_flush( ctx );
 919          tnl->Driver.Render.Start = radeonRenderStart;
 920          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 921          tnl->Driver.Render.Finish = radeonRenderFinish;
 922
 923          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 924          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 925          tnl->Driver.Render.Interp = _tnl_interp;
 926
 927          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 928          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 929          if (rmesa->TclFallback) {
 930             /* These are already done if rmesa->TclFallback goes to
 931              * zero above. But not if it doesn't (RADEON_NO_TCL for
 932              * example?)
 933              */
 934             radeonChooseVertexState( ctx );
 935             radeonChooseRenderState( ctx );
 936          }
 937          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 938             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 939                     bit, getFallbackString(bit));
 940          }
 941       }
 942    }
 943 }
 944
 945
 946 void radeonFlushVertices( GLcontext *ctx, GLuint flags )
 947 {
 948    _tnl_FlushVertices( ctx, flags );
 949
 950    if (flags & FLUSH_STORED_VERTICES)
 951       RADEON_NEWPRIM( RADEON_CONTEXT( ctx ) );
 952 }
 953
 954 /**********************************************************************/
 955 /*                            Initialization.                         */
 956 /**********************************************************************/
 957
 958 void radeonInitSwtcl( GLcontext *ctx )
 959 {
 960    TNLcontext *tnl = TNL_CONTEXT(ctx);
 961    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 962    static int firsttime = 1;
 963
 964    if (firsttime) {
 965       init_rast_tab();
 966       firsttime = 0;
 967    }
 968
 969    tnl->Driver.Render.Start = radeonRenderStart;
 970    tnl->Driver.Render.Finish = radeonRenderFinish;
 971    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 972    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 973    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 974    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 975    tnl->Driver.Render.Interp = _tnl_interp;
 976
 977    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 978                        RADEON_MAX_TNL_VERTEX_SIZE);
 979
 980    rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 981    rmesa->swtcl.RenderIndex = ~0;
 982    rmesa->swtcl.render_primitive = GL_TRIANGLES;
 983    rmesa->swtcl.hw_primitive = 0;
 984 }
 985
 986
 987 void radeonDestroySwtcl( GLcontext *ctx )
 988 {
 989    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 990
 991    if (rmesa->swtcl.indexed_verts.buf)
 992       radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 993                               __FUNCTION__ );
 994 }