src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41
  42 #include "swrast_setup/swrast_setup.h"
  43 #include "math/m_translate.h"
  44 #include "tnl/tnl.h"
  45 #include "tnl/t_context.h"
  46 #include "tnl/t_pipeline.h"
  47
  48 #include "radeon_context.h"
  49 #include "radeon_ioctl.h"
  50 #include "radeon_state.h"
  51 #include "radeon_swtcl.h"
  52 #include "radeon_tcl.h"
  53
  54
  55 static void flush_last_swtcl_prim(GLcontext *ctx);
  56
  57 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  58 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  59 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  60
  61 /***********************************************************************
  62  *                         Initialization
  63  ***********************************************************************/
  64
  65 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  66 do {                                                                    \
  67    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR);   \
  68    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE);  \
  69    rmesa->swtcl.vertex_attr_count++;                                    \
  70    fmt_0 |= F0;                                                         \
  71 } while (0)
  72
  73 #define EMIT_PAD( N )                                                   \
  74 do {                                                                    \
  75    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0;                \
  76    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \
  77    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N);              \
  78    rmesa->swtcl.vertex_attr_count++;                                    \
  79 } while (0)
  80
  81 static GLuint radeon_cp_vc_frmts[3][2] =
  82 {
  83    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  84    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  85    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  86 };
  87
  88 static void radeonSetVertexFormat( GLcontext *ctx )
  89 {
  90    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  91    TNLcontext *tnl = TNL_CONTEXT(ctx);
  92    struct vertex_buffer *VB = &tnl->vb;
  93    DECLARE_RENDERINPUTS(index_bitset);
  94    int fmt_0 = 0;
  95    int offset = 0;
  96
  97    RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
  98
  99    /* Important:
 100     */
 101    if ( VB->NdcPtr != NULL ) {
 102       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 103    }
 104    else {
 105       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 106    }
 107
 108    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 109    rmesa->swtcl.vertex_attr_count = 0;
 110
 111    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 112     * build up a hardware vertex.
 113     */
 114    if ( !rmesa->swtcl.needproj ||
 115         RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {       /* for projtex */
 116       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 117                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 118       offset = 4;
 119    }
 120    else {
 121       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 122                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 123       offset = 3;
 124    }
 125
 126    rmesa->swtcl.coloroffset = offset;
 127 #if MESA_LITTLE_ENDIAN
 128    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 129               RADEON_CP_VC_FRMT_PKCOLOR );
 130 #else
 131    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 132               RADEON_CP_VC_FRMT_PKCOLOR );
 133 #endif
 134    offset += 1;
 135
 136    rmesa->swtcl.specoffset = 0;
 137    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
 138        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 139
 140 #if MESA_LITTLE_ENDIAN
 141       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 142          rmesa->swtcl.specoffset = offset;
 143          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 144                     RADEON_CP_VC_FRMT_PKSPEC );
 145       }
 146       else {
 147          EMIT_PAD( 3 );
 148       }
 149
 150       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 151          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 152                     RADEON_CP_VC_FRMT_PKSPEC );
 153       }
 154       else {
 155          EMIT_PAD( 1 );
 156       }
 157 #else
 158       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 159          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 160                     RADEON_CP_VC_FRMT_PKSPEC );
 161       }
 162       else {
 163          EMIT_PAD( 1 );
 164       }
 165
 166       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 167          rmesa->swtcl.specoffset = offset;
 168          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 169                     RADEON_CP_VC_FRMT_PKSPEC );
 170       }
 171       else {
 172          EMIT_PAD( 3 );
 173       }
 174 #endif
 175    }
 176
 177    if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
 178       int i;
 179
 180       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 181          if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
 182             GLuint sz = VB->TexCoordPtr[i]->size;
 183
 184             switch (sz) {
 185             case 1:
 186             case 2:
 187                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 188                           radeon_cp_vc_frmts[i][0] );
 189                break;
 190             case 3:
 191             case 4:
 192                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 193                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 194                              radeon_cp_vc_frmts[i][1] );
 195                } else {
 196                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 197                              radeon_cp_vc_frmts[i][1] );
 198                }
 199                break;
 200             default:
 201                continue;
 202             };
 203          }
 204       }
 205    }
 206
 207    if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 208         fmt_0 != rmesa->swtcl.vertex_format) {
 209       RADEON_NEWPRIM(rmesa);
 210       rmesa->swtcl.vertex_format = fmt_0;
 211       rmesa->swtcl.vertex_size =
 212           _tnl_install_attrs( ctx,
 213                               rmesa->swtcl.vertex_attrs,
 214                               rmesa->swtcl.vertex_attr_count,
 215                               NULL, 0 );
 216       rmesa->swtcl.vertex_size /= 4;
 217       RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
 218       if (RADEON_DEBUG & DEBUG_VERTS)
 219          fprintf( stderr, "%s: vertex_size= %d floats\n",
 220                   __FUNCTION__, rmesa->swtcl.vertex_size);
 221    }
 222 }
 223
 224
 225 static void radeonRenderStart( GLcontext *ctx )
 226 {
 227    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 228
 229    radeonSetVertexFormat( ctx );
 230
 231    if (rmesa->dma.flush != 0 &&
 232        rmesa->dma.flush != flush_last_swtcl_prim)
 233       rmesa->dma.flush( ctx );
 234 }
 235
 236
 237 /**
 238  * Set vertex state for SW TCL.  The primary purpose of this function is to
 239  * determine in advance whether or not the hardware can / should do the
 240  * projection divide or Mesa should do it.
 241  */
 242 void radeonChooseVertexState( GLcontext *ctx )
 243 {
 244    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 245    TNLcontext *tnl = TNL_CONTEXT(ctx);
 246
 247    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 248
 249    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 250                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 251                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 252
 253    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 254     * rasterization fallback.  As this function will be called again when we
 255     * leave a rasterization fallback, we can just skip it for now.
 256     */
 257    if (rmesa->radeon.Fallback != 0)
 258       return;
 259
 260    /* HW perspective divide is a win, but tiny vertex formats are a
 261     * bigger one.
 262     */
 263
 264    if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
 265        !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
 266        || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 267       rmesa->swtcl.needproj = GL_TRUE;
 268       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 269                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 270    }
 271    else {
 272       rmesa->swtcl.needproj = GL_FALSE;
 273       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 274    }
 275
 276    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 277
 278    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 279       RADEON_STATECHANGE( rmesa, set );
 280       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 281    }
 282 }
 283
 284
 285 /* Flush vertices in the current dma region.
 286  */
 287 static void flush_last_swtcl_prim(GLcontext *ctx)
 288 {
 289    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 290    if (RADEON_DEBUG & DEBUG_IOCTL)
 291       fprintf(stderr, "%s\n", __FUNCTION__);
 292
 293    rmesa->dma.flush = NULL;
 294
 295    if (rmesa->dma.current.buf) {
 296       struct radeon_dma_region *current = &rmesa->dma.current;
 297       GLuint current_offset = (rmesa->radeon.radeonScreen->gart_buffer_offset +
 298                                current->buf->buf->idx * RADEON_BUFFER_SIZE +
 299                                current->start);
 300
 301       assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
 302
 303       assert (current->start +
 304               rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 305               current->ptr);
 306
 307       if (rmesa->dma.current.start != rmesa->dma.current.ptr) {
 308          radeonEnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ +
 309                                   rmesa->hw.max_state_size + VBUF_BUFSZ );
 310
 311          radeonEmitVertexAOS( rmesa,
 312                               rmesa->swtcl.vertex_size,
 313                               current_offset);
 314
 315          radeonEmitVbufPrim( rmesa,
 316                              rmesa->swtcl.vertex_format,
 317                              rmesa->swtcl.hw_primitive,
 318                              rmesa->swtcl.numverts);
 319       }
 320
 321       rmesa->swtcl.numverts = 0;
 322       current->start = current->ptr;
 323    }
 324 }
 325
 326
 327 /* Alloc space in the current dma region.
 328  */
 329 static INLINE void *
 330 radeonAllocDmaLowVerts( r100ContextPtr rmesa, int nverts, int vsize )
 331 {
 332    GLuint bytes = vsize * nverts;
 333
 334    if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end )
 335       radeonRefillCurrentDmaRegion( rmesa );
 336
 337    if (!rmesa->dma.flush) {
 338       rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 339       rmesa->dma.flush = flush_last_swtcl_prim;
 340    }
 341
 342    assert( vsize == rmesa->swtcl.vertex_size * 4 );
 343    assert( rmesa->dma.flush == flush_last_swtcl_prim );
 344    assert (rmesa->dma.current.start +
 345            rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 346            rmesa->dma.current.ptr);
 347
 348
 349    {
 350       GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr);
 351       rmesa->dma.current.ptr += bytes;
 352       rmesa->swtcl.numverts += nverts;
 353       return head;
 354    }
 355
 356 }
 357
 358
 359 /*
 360  * Render unclipped vertex buffers by emitting vertices directly to
 361  * dma buffers.  Use strip/fan hardware primitives where possible.
 362  * Try to simulate missing primitives with indexed vertices.
 363  */
 364 #define HAVE_POINTS      1
 365 #define HAVE_LINES       1
 366 #define HAVE_LINE_STRIPS 1
 367 #define HAVE_TRIANGLES   1
 368 #define HAVE_TRI_STRIPS  1
 369 #define HAVE_TRI_STRIP_1 0
 370 #define HAVE_TRI_FANS    1
 371 #define HAVE_QUADS       0
 372 #define HAVE_QUAD_STRIPS 0
 373 #define HAVE_POLYGONS    0
 374 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 375 #define HAVE_ELTS        0
 376
 377 static const GLuint hw_prim[GL_POLYGON+1] = {
 378    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 379    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 380    0,
 381    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 382    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 383    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 384    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 385    0,
 386    0,
 387    0
 388 };
 389
 390 static INLINE void
 391 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 392 {
 393    RADEON_NEWPRIM( rmesa );
 394    rmesa->swtcl.hw_primitive = hw_prim[prim];
 395    assert(rmesa->dma.current.ptr == rmesa->dma.current.start);
 396 }
 397
 398 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 399 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 400 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 401 #define GET_CURRENT_VB_MAX_VERTS() \
 402   (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4))
 403 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 404   ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4))
 405 #define ALLOC_VERTS( nr ) \
 406   radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 )
 407 #define EMIT_VERTS( ctx, j, nr, buf ) \
 408   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 409
 410 #define TAG(x) radeon_dma_##x
 411 #include "tnl_dd/t_dd_dmatmp.h"
 412
 413
 414 /**********************************************************************/
 415 /*                          Render pipeline stage                     */
 416 /**********************************************************************/
 417
 418
 419 static GLboolean radeon_run_render( GLcontext *ctx,
 420                                     struct tnl_pipeline_stage *stage )
 421 {
 422    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 423    TNLcontext *tnl = TNL_CONTEXT(ctx);
 424    struct vertex_buffer *VB = &tnl->vb;
 425    tnl_render_func *tab = TAG(render_tab_verts);
 426    GLuint i;
 427
 428    if (rmesa->swtcl.indexed_verts.buf)
 429       RELEASE_ELT_VERTS();
 430
 431    if (rmesa->swtcl.RenderIndex != 0 ||
 432        !radeon_dma_validate_render( ctx, VB ))
 433       return GL_TRUE;
 434
 435    tnl->Driver.Render.Start( ctx );
 436
 437    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 438    {
 439       GLuint prim = VB->Primitive[i].mode;
 440       GLuint start = VB->Primitive[i].start;
 441       GLuint length = VB->Primitive[i].count;
 442
 443       if (!length)
 444          continue;
 445
 446       if (RADEON_DEBUG & DEBUG_PRIMS)
 447          fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
 448                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 449                  start, start+length);
 450
 451       if (length)
 452          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 453    }
 454
 455    tnl->Driver.Render.Finish( ctx );
 456
 457    return GL_FALSE;             /* finished the pipe */
 458 }
 459
 460
 461
 462 const struct tnl_pipeline_stage _radeon_render_stage =
 463 {
 464    "radeon render",
 465    NULL,
 466    NULL,
 467    NULL,
 468    NULL,
 469    radeon_run_render            /* run */
 470 };
 471
 472
 473 /**************************************************************************/
 474
 475
 476 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 477    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 478    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 479    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 480    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 481    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 482    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 483    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 484    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 485    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 486    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 487 };
 488
 489 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
 490 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
 491 static void radeonResetLineStipple( GLcontext *ctx );
 492
 493
 494 /***********************************************************************
 495  *                    Emit primitives as inline vertices               *
 496  ***********************************************************************/
 497
 498 #undef LOCAL_VARS
 499 #undef ALLOC_VERTS
 500 #define CTX_ARG r100ContextPtr rmesa
 501 #define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size
 502 #define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 )
 503 #undef LOCAL_VARS
 504 #define LOCAL_VARS                                              \
 505    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 506    const char *radeonverts = (char *)rmesa->swtcl.verts;
 507 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 508 #define VERTEX radeonVertex
 509 #undef TAG
 510 #define TAG(x) radeon_##x
 511 #include "tnl_dd/t_dd_triemit.h"
 512
 513
 514 /***********************************************************************
 515  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 516  ***********************************************************************/
 517
 518 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 519 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 520 #define LINE( a, b )       radeon_line( rmesa, a, b )
 521 #define POINT( a )         radeon_point( rmesa, a )
 522
 523 /***********************************************************************
 524  *              Build render functions from dd templates               *
 525  ***********************************************************************/
 526
 527 #define RADEON_TWOSIDE_BIT      0x01
 528 #define RADEON_UNFILLED_BIT     0x02
 529 #define RADEON_MAX_TRIFUNC      0x04
 530
 531
 532 static struct {
 533    tnl_points_func              points;
 534    tnl_line_func                line;
 535    tnl_triangle_func    triangle;
 536    tnl_quad_func                quad;
 537 } rast_tab[RADEON_MAX_TRIFUNC];
 538
 539
 540 #define DO_FALLBACK  0
 541 #define DO_OFFSET    0
 542 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 543 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 544 #define DO_FLAT      0
 545 #define DO_TRI       1
 546 #define DO_QUAD      1
 547 #define DO_LINE      1
 548 #define DO_POINTS    1
 549 #define DO_FULL_QUAD 1
 550
 551 #define HAVE_RGBA   1
 552 #define HAVE_SPEC   1
 553 #define HAVE_BACK_COLORS  0
 554 #define HAVE_HW_FLATSHADE 1
 555 #define TAB rast_tab
 556
 557 #define DEPTH_SCALE 1.0
 558 #define UNFILLED_TRI unfilled_tri
 559 #define UNFILLED_QUAD unfilled_quad
 560 #define VERT_X(_v) _v->v.x
 561 #define VERT_Y(_v) _v->v.y
 562 #define VERT_Z(_v) _v->v.z
 563 #define AREA_IS_CCW( a ) (a < 0)
 564 #define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int)))
 565
 566 #define VERT_SET_RGBA( v, c )                                   \
 567 do {                                                            \
 568    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 569    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 570    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 571    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 572    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 573 } while (0)
 574
 575 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 576
 577 #define VERT_SET_SPEC( v, c )                                   \
 578 do {                                                            \
 579    if (specoffset) {                                            \
 580       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 581       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 582       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 583       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 584    }                                                            \
 585 } while (0)
 586 #define VERT_COPY_SPEC( v0, v1 )                        \
 587 do {                                                    \
 588    if (specoffset) {                                    \
 589       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 590       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 591       spec0->red   = spec1->red;        \
 592       spec0->green = spec1->green;      \
 593       spec0->blue  = spec1->blue;       \
 594    }                                                    \
 595 } while (0)
 596
 597 /* These don't need LE32_TO_CPU() as they used to save and restore
 598  * colors which are already in the correct format.
 599  */
 600 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 601 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 602 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 603 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 604
 605 #undef LOCAL_VARS
 606 #undef TAG
 607 #undef INIT
 608
 609 #define LOCAL_VARS(n)                                                   \
 610    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 611    GLuint color[n], spec[n];                                            \
 612    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 613    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 614    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 615
 616 /***********************************************************************
 617  *                Helpers for rendering unfilled primitives            *
 618  ***********************************************************************/
 619
 620 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 621 #define RENDER_PRIMITIVE rmesa->swtcl.render_primitive
 622 #undef TAG
 623 #define TAG(x) x
 624 #include "tnl_dd/t_dd_unfilled.h"
 625 #undef IND
 626
 627
 628 /***********************************************************************
 629  *                      Generate GL render functions                   *
 630  ***********************************************************************/
 631
 632
 633 #define IND (0)
 634 #define TAG(x) x
 635 #include "tnl_dd/t_dd_tritmp.h"
 636
 637 #define IND (RADEON_TWOSIDE_BIT)
 638 #define TAG(x) x##_twoside
 639 #include "tnl_dd/t_dd_tritmp.h"
 640
 641 #define IND (RADEON_UNFILLED_BIT)
 642 #define TAG(x) x##_unfilled
 643 #include "tnl_dd/t_dd_tritmp.h"
 644
 645 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 646 #define TAG(x) x##_twoside_unfilled
 647 #include "tnl_dd/t_dd_tritmp.h"
 648
 649
 650 static void init_rast_tab( void )
 651 {
 652    init();
 653    init_twoside();
 654    init_unfilled();
 655    init_twoside_unfilled();
 656 }
 657
 658 /**********************************************************************/
 659 /*               Render unclipped begin/end objects                   */
 660 /**********************************************************************/
 661
 662 #define RENDER_POINTS( start, count )           \
 663    for ( ; start < count ; start++)             \
 664       radeon_point( rmesa, VERT(start) )
 665 #define RENDER_LINE( v0, v1 ) \
 666    radeon_line( rmesa, VERT(v0), VERT(v1) )
 667 #define RENDER_TRI( v0, v1, v2 )  \
 668    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 669 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 670    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 671 #undef INIT
 672 #define INIT(x) do {                                    \
 673    radeonRenderPrimitive( ctx, x );                     \
 674 } while (0)
 675 #undef LOCAL_VARS
 676 #define LOCAL_VARS                                              \
 677    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 678    const GLuint vertsize = rmesa->swtcl.vertex_size;            \
 679    const char *radeonverts = (char *)rmesa->swtcl.verts;                \
 680    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 681    const GLboolean stipple = ctx->Line.StippleFlag;             \
 682    (void) elt; (void) stipple;
 683 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 684 #define RESET_OCCLUSION
 685 #define PRESERVE_VB_DEFS
 686 #define ELT(x) (x)
 687 #define TAG(x) radeon_##x##_verts
 688 #include "tnl/t_vb_rendertmp.h"
 689 #undef ELT
 690 #undef TAG
 691 #define TAG(x) radeon_##x##_elts
 692 #define ELT(x) elt[x]
 693 #include "tnl/t_vb_rendertmp.h"
 694
 695
 696
 697 /**********************************************************************/
 698 /*                    Choose render functions                         */
 699 /**********************************************************************/
 700
 701 void radeonChooseRenderState( GLcontext *ctx )
 702 {
 703    TNLcontext *tnl = TNL_CONTEXT(ctx);
 704    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 705    GLuint index = 0;
 706    GLuint flags = ctx->_TriangleCaps;
 707
 708    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 709       return;
 710
 711    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 712    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 713
 714    if (index != rmesa->swtcl.RenderIndex) {
 715       tnl->Driver.Render.Points = rast_tab[index].points;
 716       tnl->Driver.Render.Line = rast_tab[index].line;
 717       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 718       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 719       tnl->Driver.Render.Quad = rast_tab[index].quad;
 720
 721       if (index == 0) {
 722          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 723          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 724          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 725       } else {
 726          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 727          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 728          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 729       }
 730
 731       rmesa->swtcl.RenderIndex = index;
 732    }
 733 }
 734
 735
 736 /**********************************************************************/
 737 /*                 High level hooks for t_vb_render.c                 */
 738 /**********************************************************************/
 739
 740
 741 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 742 {
 743    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 744
 745    if (rmesa->swtcl.hw_primitive != hwprim) {
 746       RADEON_NEWPRIM( rmesa );
 747       rmesa->swtcl.hw_primitive = hwprim;
 748    }
 749 }
 750
 751 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 752 {
 753    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 754    rmesa->swtcl.render_primitive = prim;
 755    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 756       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 757 }
 758
 759 static void radeonRenderFinish( GLcontext *ctx )
 760 {
 761 }
 762
 763 static void radeonResetLineStipple( GLcontext *ctx )
 764 {
 765    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 766    RADEON_STATECHANGE( rmesa, lin );
 767 }
 768
 769
 770 /**********************************************************************/
 771 /*           Transition to/from hardware rasterization.               */
 772 /**********************************************************************/
 773
 774 static const char * const fallbackStrings[] = {
 775    "Texture mode",
 776    "glDrawBuffer(GL_FRONT_AND_BACK)",
 777    "glEnable(GL_STENCIL) without hw stencil buffer",
 778    "glRenderMode(selection or feedback)",
 779    "glBlendEquation",
 780    "glBlendFunc",
 781    "RADEON_NO_RAST",
 782    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 783 };
 784
 785
 786 static const char *getFallbackString(GLuint bit)
 787 {
 788    int i = 0;
 789    while (bit > 1) {
 790       i++;
 791       bit >>= 1;
 792    }
 793    return fallbackStrings[i];
 794 }
 795
 796
 797 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 798 {
 799    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 800    TNLcontext *tnl = TNL_CONTEXT(ctx);
 801    GLuint oldfallback = rmesa->radeon.Fallback;
 802
 803    if (mode) {
 804       rmesa->radeon.Fallback |= bit;
 805       if (oldfallback == 0) {
 806          RADEON_FIREVERTICES( rmesa );
 807          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 808          _swsetup_Wakeup( ctx );
 809          rmesa->swtcl.RenderIndex = ~0;
 810          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 811             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 812                     bit, getFallbackString(bit));
 813          }
 814       }
 815    }
 816    else {
 817       rmesa->radeon.Fallback &= ~bit;
 818       if (oldfallback == bit) {
 819          _swrast_flush( ctx );
 820          tnl->Driver.Render.Start = radeonRenderStart;
 821          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 822          tnl->Driver.Render.Finish = radeonRenderFinish;
 823
 824          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 825          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 826          tnl->Driver.Render.Interp = _tnl_interp;
 827
 828          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 829          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 830          if (rmesa->radeon.TclFallback) {
 831             /* These are already done if rmesa->radeon.TclFallback goes to
 832              * zero above. But not if it doesn't (RADEON_NO_TCL for
 833              * example?)
 834              */
 835             _tnl_invalidate_vertex_state( ctx, ~0 );
 836             _tnl_invalidate_vertices( ctx, ~0 );
 837             RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 838             radeonChooseVertexState( ctx );
 839             radeonChooseRenderState( ctx );
 840          }
 841          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 842             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 843                     bit, getFallbackString(bit));
 844          }
 845       }
 846    }
 847 }
 848
 849
 850 /**********************************************************************/
 851 /*                            Initialization.                         */
 852 /**********************************************************************/
 853
 854 void radeonInitSwtcl( GLcontext *ctx )
 855 {
 856    TNLcontext *tnl = TNL_CONTEXT(ctx);
 857    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 858    static int firsttime = 1;
 859
 860    if (firsttime) {
 861       init_rast_tab();
 862       firsttime = 0;
 863    }
 864
 865    tnl->Driver.Render.Start = radeonRenderStart;
 866    tnl->Driver.Render.Finish = radeonRenderFinish;
 867    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 868    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 869    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 870    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 871    tnl->Driver.Render.Interp = _tnl_interp;
 872
 873    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 874                        RADEON_MAX_TNL_VERTEX_SIZE);
 875
 876    rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 877    rmesa->swtcl.RenderIndex = ~0;
 878    rmesa->swtcl.render_primitive = GL_TRIANGLES;
 879    rmesa->swtcl.hw_primitive = 0;
 880 }
 881
 882
 883 void radeonDestroySwtcl( GLcontext *ctx )
 884 {
 885    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 886
 887    if (rmesa->swtcl.indexed_verts.buf)
 888       radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 889                               __FUNCTION__ );
 890 }