src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41
  42 #include "swrast_setup/swrast_setup.h"
  43 #include "math/m_translate.h"
  44 #include "tnl/tnl.h"
  45 #include "tnl/t_context.h"
  46 #include "tnl/t_pipeline.h"
  47
  48 #include "radeon_context.h"
  49 #include "radeon_ioctl.h"
  50 #include "radeon_state.h"
  51 #include "radeon_swtcl.h"
  52 #include "radeon_tcl.h"
  53
  54
  55 static void flush_last_swtcl_prim( radeonContextPtr rmesa  );
  56
  57 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  58 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  59 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  60
  61 /***********************************************************************
  62  *                         Initialization
  63  ***********************************************************************/
  64
  65 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  66 do {                                                                    \
  67    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR);   \
  68    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE);  \
  69    rmesa->swtcl.vertex_attr_count++;                                    \
  70    fmt_0 |= F0;                                                         \
  71 } while (0)
  72
  73 #define EMIT_PAD( N )                                                   \
  74 do {                                                                    \
  75    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0;                \
  76    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \
  77    rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N);              \
  78    rmesa->swtcl.vertex_attr_count++;                                    \
  79 } while (0)
  80
  81 static GLuint radeon_cp_vc_frmts[3][2] =
  82 {
  83    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  84    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  85    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  86 };
  87
  88 static void radeonSetVertexFormat( GLcontext *ctx )
  89 {
  90    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
  91    TNLcontext *tnl = TNL_CONTEXT(ctx);
  92    struct vertex_buffer *VB = &tnl->vb;
  93    DECLARE_RENDERINPUTS(index_bitset);
  94    int fmt_0 = 0;
  95    int offset = 0;
  96
  97    RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
  98
  99    /* Important:
 100     */
 101    if ( VB->NdcPtr != NULL ) {
 102       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 103    }
 104    else {
 105       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 106    }
 107
 108    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 109    rmesa->swtcl.vertex_attr_count = 0;
 110
 111    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 112     * build up a hardware vertex.
 113     */
 114    if ( !rmesa->swtcl.needproj ||
 115         RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {       /* for projtex */
 116       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 117                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 118       offset = 4;
 119    }
 120    else {
 121       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 122                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 123       offset = 3;
 124    }
 125
 126    rmesa->swtcl.coloroffset = offset;
 127 #if MESA_LITTLE_ENDIAN
 128    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 129               RADEON_CP_VC_FRMT_PKCOLOR );
 130 #else
 131    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 132               RADEON_CP_VC_FRMT_PKCOLOR );
 133 #endif
 134    offset += 1;
 135
 136    rmesa->swtcl.specoffset = 0;
 137    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
 138        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 139
 140 #if MESA_LITTLE_ENDIAN
 141       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 142          rmesa->swtcl.specoffset = offset;
 143          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 144                     RADEON_CP_VC_FRMT_PKSPEC );
 145       }
 146       else {
 147          EMIT_PAD( 3 );
 148       }
 149
 150       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 151          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 152                     RADEON_CP_VC_FRMT_PKSPEC );
 153       }
 154       else {
 155          EMIT_PAD( 1 );
 156       }
 157 #else
 158       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 159          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 160                     RADEON_CP_VC_FRMT_PKSPEC );
 161       }
 162       else {
 163          EMIT_PAD( 1 );
 164       }
 165
 166       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 167          rmesa->swtcl.specoffset = offset;
 168          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 169                     RADEON_CP_VC_FRMT_PKSPEC );
 170       }
 171       else {
 172          EMIT_PAD( 3 );
 173       }
 174 #endif
 175    }
 176
 177    if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
 178       int i;
 179
 180       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 181          if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
 182             GLuint sz = VB->TexCoordPtr[i]->size;
 183
 184             switch (sz) {
 185             case 1:
 186             case 2:
 187                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 188                           radeon_cp_vc_frmts[i][0] );
 189                break;
 190             case 3:
 191             case 4:
 192                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 193                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 194                              radeon_cp_vc_frmts[i][1] );
 195                } else {
 196                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 197                              radeon_cp_vc_frmts[i][1] );
 198                }
 199                break;
 200             default:
 201                continue;
 202             };
 203          }
 204       }
 205    }
 206
 207    if (!RENDERINPUTS_EQUAL( rmesa->tnl_index_bitset, index_bitset ) ||
 208         fmt_0 != rmesa->swtcl.vertex_format) {
 209       RADEON_NEWPRIM(rmesa);
 210       rmesa->swtcl.vertex_format = fmt_0;
 211       rmesa->swtcl.vertex_size =
 212           _tnl_install_attrs( ctx,
 213                               rmesa->swtcl.vertex_attrs,
 214                               rmesa->swtcl.vertex_attr_count,
 215                               NULL, 0 );
 216       rmesa->swtcl.vertex_size /= 4;
 217       RENDERINPUTS_COPY( rmesa->tnl_index_bitset, index_bitset );
 218       if (RADEON_DEBUG & DEBUG_VERTS)
 219          fprintf( stderr, "%s: vertex_size= %d floats\n",
 220                   __FUNCTION__, rmesa->swtcl.vertex_size);
 221    }
 222 }
 223
 224
 225 static void radeonRenderStart( GLcontext *ctx )
 226 {
 227    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 228
 229    radeonSetVertexFormat( ctx );
 230
 231    if (rmesa->dma.flush != 0 &&
 232        rmesa->dma.flush != flush_last_swtcl_prim)
 233       rmesa->dma.flush( rmesa );
 234 }
 235
 236
 237 /**
 238  * Set vertex state for SW TCL.  The primary purpose of this function is to
 239  * determine in advance whether or not the hardware can / should do the
 240  * projection divide or Mesa should do it.
 241  */
 242 void radeonChooseVertexState( GLcontext *ctx )
 243 {
 244    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 245    TNLcontext *tnl = TNL_CONTEXT(ctx);
 246
 247    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 248
 249    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 250                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 251                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 252
 253    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 254     * rasterization fallback.  As this function will be called again when we
 255     * leave a rasterization fallback, we can just skip it for now.
 256     */
 257    if (rmesa->Fallback != 0)
 258       return;
 259
 260    /* HW perspective divide is a win, but tiny vertex formats are a
 261     * bigger one.
 262     */
 263
 264    if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
 265        !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
 266        || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 267       rmesa->swtcl.needproj = GL_TRUE;
 268       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 269                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 270    }
 271    else {
 272       rmesa->swtcl.needproj = GL_FALSE;
 273       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 274    }
 275
 276    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 277
 278    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 279       RADEON_STATECHANGE( rmesa, set );
 280       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 281    }
 282 }
 283
 284
 285 /* Flush vertices in the current dma region.
 286  */
 287 static void flush_last_swtcl_prim( radeonContextPtr rmesa  )
 288 {
 289    if (RADEON_DEBUG & DEBUG_IOCTL)
 290       fprintf(stderr, "%s\n", __FUNCTION__);
 291
 292    rmesa->dma.flush = NULL;
 293
 294    if (rmesa->dma.current.buf) {
 295       struct radeon_dma_region *current = &rmesa->dma.current;
 296       GLuint current_offset = (rmesa->radeonScreen->gart_buffer_offset +
 297                                current->buf->buf->idx * RADEON_BUFFER_SIZE +
 298                                current->start);
 299
 300       assert (!(rmesa->swtcl.hw_primitive & RADEON_CP_VC_CNTL_PRIM_WALK_IND));
 301
 302       assert (current->start +
 303               rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 304               current->ptr);
 305
 306       if (rmesa->dma.current.start != rmesa->dma.current.ptr) {
 307          radeonEnsureCmdBufSpace( rmesa, VERT_AOS_BUFSZ +
 308                                   rmesa->hw.max_state_size + VBUF_BUFSZ );
 309
 310          radeonEmitVertexAOS( rmesa,
 311                               rmesa->swtcl.vertex_size,
 312                               current_offset);
 313
 314          radeonEmitVbufPrim( rmesa,
 315                              rmesa->swtcl.vertex_format,
 316                              rmesa->swtcl.hw_primitive,
 317                              rmesa->swtcl.numverts);
 318       }
 319
 320       rmesa->swtcl.numverts = 0;
 321       current->start = current->ptr;
 322    }
 323 }
 324
 325
 326 /* Alloc space in the current dma region.
 327  */
 328 static INLINE void *
 329 radeonAllocDmaLowVerts( radeonContextPtr rmesa, int nverts, int vsize )
 330 {
 331    GLuint bytes = vsize * nverts;
 332
 333    if ( rmesa->dma.current.ptr + bytes > rmesa->dma.current.end )
 334       radeonRefillCurrentDmaRegion( rmesa );
 335
 336    if (!rmesa->dma.flush) {
 337       rmesa->glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES;
 338       rmesa->dma.flush = flush_last_swtcl_prim;
 339    }
 340
 341    assert( vsize == rmesa->swtcl.vertex_size * 4 );
 342    assert( rmesa->dma.flush == flush_last_swtcl_prim );
 343    assert (rmesa->dma.current.start +
 344            rmesa->swtcl.numverts * rmesa->swtcl.vertex_size * 4 ==
 345            rmesa->dma.current.ptr);
 346
 347
 348    {
 349       GLubyte *head = (GLubyte *)(rmesa->dma.current.address + rmesa->dma.current.ptr);
 350       rmesa->dma.current.ptr += bytes;
 351       rmesa->swtcl.numverts += nverts;
 352       return head;
 353    }
 354
 355 }
 356
 357
 358 /*
 359  * Render unclipped vertex buffers by emitting vertices directly to
 360  * dma buffers.  Use strip/fan hardware primitives where possible.
 361  * Try to simulate missing primitives with indexed vertices.
 362  */
 363 #define HAVE_POINTS      1
 364 #define HAVE_LINES       1
 365 #define HAVE_LINE_STRIPS 1
 366 #define HAVE_TRIANGLES   1
 367 #define HAVE_TRI_STRIPS  1
 368 #define HAVE_TRI_STRIP_1 0
 369 #define HAVE_TRI_FANS    1
 370 #define HAVE_QUADS       0
 371 #define HAVE_QUAD_STRIPS 0
 372 #define HAVE_POLYGONS    0
 373 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 374 #define HAVE_ELTS        0
 375
 376 static const GLuint hw_prim[GL_POLYGON+1] = {
 377    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 378    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 379    0,
 380    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 381    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 382    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 383    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 384    0,
 385    0,
 386    0
 387 };
 388
 389 static INLINE void
 390 radeonDmaPrimitive( radeonContextPtr rmesa, GLenum prim )
 391 {
 392    RADEON_NEWPRIM( rmesa );
 393    rmesa->swtcl.hw_primitive = hw_prim[prim];
 394    assert(rmesa->dma.current.ptr == rmesa->dma.current.start);
 395 }
 396
 397 #define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
 398 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 399 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 400 #define GET_CURRENT_VB_MAX_VERTS() \
 401   (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4))
 402 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 403   ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4))
 404 #define ALLOC_VERTS( nr ) \
 405   radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 )
 406 #define EMIT_VERTS( ctx, j, nr, buf ) \
 407   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 408
 409 #define TAG(x) radeon_dma_##x
 410 #include "tnl_dd/t_dd_dmatmp.h"
 411
 412
 413 /**********************************************************************/
 414 /*                          Render pipeline stage                     */
 415 /**********************************************************************/
 416
 417
 418 static GLboolean radeon_run_render( GLcontext *ctx,
 419                                     struct tnl_pipeline_stage *stage )
 420 {
 421    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 422    TNLcontext *tnl = TNL_CONTEXT(ctx);
 423    struct vertex_buffer *VB = &tnl->vb;
 424    tnl_render_func *tab = TAG(render_tab_verts);
 425    GLuint i;
 426
 427    if (rmesa->swtcl.indexed_verts.buf)
 428       RELEASE_ELT_VERTS();
 429
 430    if (rmesa->swtcl.RenderIndex != 0 ||
 431        !radeon_dma_validate_render( ctx, VB ))
 432       return GL_TRUE;
 433
 434    tnl->Driver.Render.Start( ctx );
 435
 436    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 437    {
 438       GLuint prim = VB->Primitive[i].mode;
 439       GLuint start = VB->Primitive[i].start;
 440       GLuint length = VB->Primitive[i].count;
 441
 442       if (!length)
 443          continue;
 444
 445       if (RADEON_DEBUG & DEBUG_PRIMS)
 446          fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
 447                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 448                  start, start+length);
 449
 450       if (length)
 451          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 452    }
 453
 454    tnl->Driver.Render.Finish( ctx );
 455
 456    return GL_FALSE;             /* finished the pipe */
 457 }
 458
 459
 460
 461 const struct tnl_pipeline_stage _radeon_render_stage =
 462 {
 463    "radeon render",
 464    NULL,
 465    NULL,
 466    NULL,
 467    NULL,
 468    radeon_run_render            /* run */
 469 };
 470
 471
 472 /**************************************************************************/
 473
 474
 475 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 476    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 477    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 478    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 479    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 480    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 481    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 482    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 483    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 484    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 485    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 486 };
 487
 488 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
 489 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
 490 static void radeonResetLineStipple( GLcontext *ctx );
 491
 492
 493 /***********************************************************************
 494  *                    Emit primitives as inline vertices               *
 495  ***********************************************************************/
 496
 497 #undef LOCAL_VARS
 498 #undef ALLOC_VERTS
 499 #define CTX_ARG radeonContextPtr rmesa
 500 #define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size
 501 #define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 )
 502 #undef LOCAL_VARS
 503 #define LOCAL_VARS                                              \
 504    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                \
 505    const char *radeonverts = (char *)rmesa->swtcl.verts;
 506 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 507 #define VERTEX radeonVertex
 508 #undef TAG
 509 #define TAG(x) radeon_##x
 510 #include "tnl_dd/t_dd_triemit.h"
 511
 512
 513 /***********************************************************************
 514  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 515  ***********************************************************************/
 516
 517 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 518 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 519 #define LINE( a, b )       radeon_line( rmesa, a, b )
 520 #define POINT( a )         radeon_point( rmesa, a )
 521
 522 /***********************************************************************
 523  *              Build render functions from dd templates               *
 524  ***********************************************************************/
 525
 526 #define RADEON_TWOSIDE_BIT      0x01
 527 #define RADEON_UNFILLED_BIT     0x02
 528 #define RADEON_MAX_TRIFUNC      0x04
 529
 530
 531 static struct {
 532    tnl_points_func              points;
 533    tnl_line_func                line;
 534    tnl_triangle_func    triangle;
 535    tnl_quad_func                quad;
 536 } rast_tab[RADEON_MAX_TRIFUNC];
 537
 538
 539 #define DO_FALLBACK  0
 540 #define DO_OFFSET    0
 541 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 542 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 543 #define DO_FLAT      0
 544 #define DO_TRI       1
 545 #define DO_QUAD      1
 546 #define DO_LINE      1
 547 #define DO_POINTS    1
 548 #define DO_FULL_QUAD 1
 549
 550 #define HAVE_RGBA   1
 551 #define HAVE_SPEC   1
 552 #define HAVE_BACK_COLORS  0
 553 #define HAVE_HW_FLATSHADE 1
 554 #define TAB rast_tab
 555
 556 #define DEPTH_SCALE 1.0
 557 #define UNFILLED_TRI unfilled_tri
 558 #define UNFILLED_QUAD unfilled_quad
 559 #define VERT_X(_v) _v->v.x
 560 #define VERT_Y(_v) _v->v.y
 561 #define VERT_Z(_v) _v->v.z
 562 #define AREA_IS_CCW( a ) (a < 0)
 563 #define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int)))
 564
 565 #define VERT_SET_RGBA( v, c )                                   \
 566 do {                                                            \
 567    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 568    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 569    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 570    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 571    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 572 } while (0)
 573
 574 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 575
 576 #define VERT_SET_SPEC( v, c )                                   \
 577 do {                                                            \
 578    if (specoffset) {                                            \
 579       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 580       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 581       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 582       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 583    }                                                            \
 584 } while (0)
 585 #define VERT_COPY_SPEC( v0, v1 )                        \
 586 do {                                                    \
 587    if (specoffset) {                                    \
 588       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 589       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 590       spec0->red   = spec1->red;        \
 591       spec0->green = spec1->green;      \
 592       spec0->blue  = spec1->blue;       \
 593    }                                                    \
 594 } while (0)
 595
 596 /* These don't need LE32_TO_CPU() as they used to save and restore
 597  * colors which are already in the correct format.
 598  */
 599 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 600 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 601 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 602 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 603
 604 #undef LOCAL_VARS
 605 #undef TAG
 606 #undef INIT
 607
 608 #define LOCAL_VARS(n)                                                   \
 609    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                        \
 610    GLuint color[n], spec[n];                                            \
 611    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 612    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 613    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 614
 615 /***********************************************************************
 616  *                Helpers for rendering unfilled primitives            *
 617  ***********************************************************************/
 618
 619 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 620 #define RENDER_PRIMITIVE rmesa->swtcl.render_primitive
 621 #undef TAG
 622 #define TAG(x) x
 623 #include "tnl_dd/t_dd_unfilled.h"
 624 #undef IND
 625
 626
 627 /***********************************************************************
 628  *                      Generate GL render functions                   *
 629  ***********************************************************************/
 630
 631
 632 #define IND (0)
 633 #define TAG(x) x
 634 #include "tnl_dd/t_dd_tritmp.h"
 635
 636 #define IND (RADEON_TWOSIDE_BIT)
 637 #define TAG(x) x##_twoside
 638 #include "tnl_dd/t_dd_tritmp.h"
 639
 640 #define IND (RADEON_UNFILLED_BIT)
 641 #define TAG(x) x##_unfilled
 642 #include "tnl_dd/t_dd_tritmp.h"
 643
 644 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 645 #define TAG(x) x##_twoside_unfilled
 646 #include "tnl_dd/t_dd_tritmp.h"
 647
 648
 649 static void init_rast_tab( void )
 650 {
 651    init();
 652    init_twoside();
 653    init_unfilled();
 654    init_twoside_unfilled();
 655 }
 656
 657 /**********************************************************************/
 658 /*               Render unclipped begin/end objects                   */
 659 /**********************************************************************/
 660
 661 #define RENDER_POINTS( start, count )           \
 662    for ( ; start < count ; start++)             \
 663       radeon_point( rmesa, VERT(start) )
 664 #define RENDER_LINE( v0, v1 ) \
 665    radeon_line( rmesa, VERT(v0), VERT(v1) )
 666 #define RENDER_TRI( v0, v1, v2 )  \
 667    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 668 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 669    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 670 #undef INIT
 671 #define INIT(x) do {                                    \
 672    radeonRenderPrimitive( ctx, x );                     \
 673 } while (0)
 674 #undef LOCAL_VARS
 675 #define LOCAL_VARS                                              \
 676    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);                \
 677    const GLuint vertsize = rmesa->swtcl.vertex_size;            \
 678    const char *radeonverts = (char *)rmesa->swtcl.verts;                \
 679    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 680    const GLboolean stipple = ctx->Line.StippleFlag;             \
 681    (void) elt; (void) stipple;
 682 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 683 #define RESET_OCCLUSION
 684 #define PRESERVE_VB_DEFS
 685 #define ELT(x) (x)
 686 #define TAG(x) radeon_##x##_verts
 687 #include "tnl/t_vb_rendertmp.h"
 688 #undef ELT
 689 #undef TAG
 690 #define TAG(x) radeon_##x##_elts
 691 #define ELT(x) elt[x]
 692 #include "tnl/t_vb_rendertmp.h"
 693
 694
 695
 696 /**********************************************************************/
 697 /*                    Choose render functions                         */
 698 /**********************************************************************/
 699
 700 void radeonChooseRenderState( GLcontext *ctx )
 701 {
 702    TNLcontext *tnl = TNL_CONTEXT(ctx);
 703    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 704    GLuint index = 0;
 705    GLuint flags = ctx->_TriangleCaps;
 706
 707    if (!rmesa->TclFallback || rmesa->Fallback)
 708       return;
 709
 710    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 711    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 712
 713    if (index != rmesa->swtcl.RenderIndex) {
 714       tnl->Driver.Render.Points = rast_tab[index].points;
 715       tnl->Driver.Render.Line = rast_tab[index].line;
 716       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 717       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 718       tnl->Driver.Render.Quad = rast_tab[index].quad;
 719
 720       if (index == 0) {
 721          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 722          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 723          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 724       } else {
 725          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 726          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 727          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 728       }
 729
 730       rmesa->swtcl.RenderIndex = index;
 731    }
 732 }
 733
 734
 735 /**********************************************************************/
 736 /*                 High level hooks for t_vb_render.c                 */
 737 /**********************************************************************/
 738
 739
 740 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 741 {
 742    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 743
 744    if (rmesa->swtcl.hw_primitive != hwprim) {
 745       RADEON_NEWPRIM( rmesa );
 746       rmesa->swtcl.hw_primitive = hwprim;
 747    }
 748 }
 749
 750 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 751 {
 752    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 753    rmesa->swtcl.render_primitive = prim;
 754    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 755       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 756 }
 757
 758 static void radeonRenderFinish( GLcontext *ctx )
 759 {
 760 }
 761
 762 static void radeonResetLineStipple( GLcontext *ctx )
 763 {
 764    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 765    RADEON_STATECHANGE( rmesa, lin );
 766 }
 767
 768
 769 /**********************************************************************/
 770 /*           Transition to/from hardware rasterization.               */
 771 /**********************************************************************/
 772
 773 static const char * const fallbackStrings[] = {
 774    "Texture mode",
 775    "glDrawBuffer(GL_FRONT_AND_BACK)",
 776    "glEnable(GL_STENCIL) without hw stencil buffer",
 777    "glRenderMode(selection or feedback)",
 778    "glBlendEquation",
 779    "glBlendFunc",
 780    "RADEON_NO_RAST",
 781    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 782 };
 783
 784
 785 static const char *getFallbackString(GLuint bit)
 786 {
 787    int i = 0;
 788    while (bit > 1) {
 789       i++;
 790       bit >>= 1;
 791    }
 792    return fallbackStrings[i];
 793 }
 794
 795
 796 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 797 {
 798    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 799    TNLcontext *tnl = TNL_CONTEXT(ctx);
 800    GLuint oldfallback = rmesa->Fallback;
 801
 802    if (mode) {
 803       rmesa->Fallback |= bit;
 804       if (oldfallback == 0) {
 805          RADEON_FIREVERTICES( rmesa );
 806          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 807          _swsetup_Wakeup( ctx );
 808          rmesa->swtcl.RenderIndex = ~0;
 809          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 810             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 811                     bit, getFallbackString(bit));
 812          }
 813       }
 814    }
 815    else {
 816       rmesa->Fallback &= ~bit;
 817       if (oldfallback == bit) {
 818          _swrast_flush( ctx );
 819          tnl->Driver.Render.Start = radeonRenderStart;
 820          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 821          tnl->Driver.Render.Finish = radeonRenderFinish;
 822
 823          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 824          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 825          tnl->Driver.Render.Interp = _tnl_interp;
 826
 827          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 828          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 829          if (rmesa->TclFallback) {
 830             /* These are already done if rmesa->TclFallback goes to
 831              * zero above. But not if it doesn't (RADEON_NO_TCL for
 832              * example?)
 833              */
 834             _tnl_invalidate_vertex_state( ctx, ~0 );
 835             _tnl_invalidate_vertices( ctx, ~0 );
 836             RENDERINPUTS_ZERO( rmesa->tnl_index_bitset );
 837             radeonChooseVertexState( ctx );
 838             radeonChooseRenderState( ctx );
 839          }
 840          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 841             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 842                     bit, getFallbackString(bit));
 843          }
 844       }
 845    }
 846 }
 847
 848
 849 /**********************************************************************/
 850 /*                            Initialization.                         */
 851 /**********************************************************************/
 852
 853 void radeonInitSwtcl( GLcontext *ctx )
 854 {
 855    TNLcontext *tnl = TNL_CONTEXT(ctx);
 856    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 857    static int firsttime = 1;
 858
 859    if (firsttime) {
 860       init_rast_tab();
 861       firsttime = 0;
 862    }
 863
 864    tnl->Driver.Render.Start = radeonRenderStart;
 865    tnl->Driver.Render.Finish = radeonRenderFinish;
 866    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 867    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 868    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 869    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 870    tnl->Driver.Render.Interp = _tnl_interp;
 871
 872    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 873                        RADEON_MAX_TNL_VERTEX_SIZE);
 874
 875    rmesa->swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 876    rmesa->swtcl.RenderIndex = ~0;
 877    rmesa->swtcl.render_primitive = GL_TRIANGLES;
 878    rmesa->swtcl.hw_primitive = 0;
 879 }
 880
 881
 882 void radeonDestroySwtcl( GLcontext *ctx )
 883 {
 884    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 885
 886    if (rmesa->swtcl.indexed_verts.buf)
 887       radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 888                               __FUNCTION__ );
 889 }