1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_swtcl.c,v 1.6 2003/05/06 23:52:08 daenzer Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Keith Whitwell <keith@tungstengraphics.com>
43 #include "swrast_setup/swrast_setup.h"
44 #include "math/m_translate.h"
46 #include "tnl/t_context.h"
47 #include "tnl/t_pipeline.h"
49 #include "radeon_context.h"
50 #include "radeon_ioctl.h"
51 #include "radeon_state.h"
52 #include "radeon_swtcl.h"
53 #include "radeon_tcl.h"
56 static void flush_last_swtcl_prim( radeonContextPtr rmesa
);
58 /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
59 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
60 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */
62 /***********************************************************************
64 ***********************************************************************/
66 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
68 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = (ATTR); \
69 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = (STYLE); \
70 rmesa->swtcl.vertex_attr_count++; \
74 #define EMIT_PAD( N ) \
76 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].attrib = 0; \
77 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].format = EMIT_PAD; \
78 rmesa->swtcl.vertex_attrs[rmesa->swtcl.vertex_attr_count].offset = (N); \
79 rmesa->swtcl.vertex_attr_count++; \
82 static GLuint radeon_cp_vc_frmts
[3][2] =
84 { RADEON_CP_VC_FRMT_ST0
, RADEON_CP_VC_FRMT_ST0
| RADEON_CP_VC_FRMT_Q0
},
85 { RADEON_CP_VC_FRMT_ST1
, RADEON_CP_VC_FRMT_ST1
| RADEON_CP_VC_FRMT_Q1
},
86 { RADEON_CP_VC_FRMT_ST2
, RADEON_CP_VC_FRMT_ST2
| RADEON_CP_VC_FRMT_Q2
},
89 static void radeonSetVertexFormat( GLcontext
*ctx
)
91 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
92 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
93 struct vertex_buffer
*VB
= &tnl
->vb
;
94 DECLARE_RENDERINPUTS(index_bitset
);
98 RENDERINPUTS_COPY( index_bitset
, tnl
->render_inputs_bitset
);
102 if ( VB
->NdcPtr
!= NULL
) {
103 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
106 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->ClipPtr
;
109 assert( VB
->AttribPtr
[VERT_ATTRIB_POS
] != NULL
);
110 rmesa
->swtcl
.vertex_attr_count
= 0;
112 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
113 * build up a hardware vertex.
115 if ( !rmesa
->swtcl
.needproj
||
116 RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) { /* for projtex */
117 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_4F
,
118 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
| RADEON_CP_VC_FRMT_W0
);
122 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_3F
,
123 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
);
127 rmesa
->swtcl
.coloroffset
= offset
;
128 #if MESA_LITTLE_ENDIAN
129 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_RGBA
,
130 RADEON_CP_VC_FRMT_PKCOLOR
);
132 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_ABGR
,
133 RADEON_CP_VC_FRMT_PKCOLOR
);
137 rmesa
->swtcl
.specoffset
= 0;
138 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
) ||
139 RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
141 #if MESA_LITTLE_ENDIAN
142 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
143 rmesa
->swtcl
.specoffset
= offset
;
144 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_RGB
,
145 RADEON_CP_VC_FRMT_PKSPEC
);
151 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
152 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
153 RADEON_CP_VC_FRMT_PKSPEC
);
159 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
160 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
161 RADEON_CP_VC_FRMT_PKSPEC
);
167 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
168 rmesa
->swtcl
.specoffset
= offset
;
169 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
,
170 RADEON_CP_VC_FRMT_PKSPEC
);
178 if (RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
181 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
182 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_TEX(i
) )) {
183 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
188 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_2F
,
189 radeon_cp_vc_frmts
[i
][0] );
193 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
& (TEXTURE_CUBE_BIT
) ) {
194 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F
,
195 radeon_cp_vc_frmts
[i
][1] );
197 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F_XYW
,
198 radeon_cp_vc_frmts
[i
][1] );
208 if (!RENDERINPUTS_EQUAL( rmesa
->tnl_index_bitset
, index_bitset
) ||
209 fmt_0
!= rmesa
->swtcl
.vertex_format
) {
210 RADEON_NEWPRIM(rmesa
);
211 rmesa
->swtcl
.vertex_format
= fmt_0
;
212 rmesa
->swtcl
.vertex_size
=
213 _tnl_install_attrs( ctx
,
214 rmesa
->swtcl
.vertex_attrs
,
215 rmesa
->swtcl
.vertex_attr_count
,
217 rmesa
->swtcl
.vertex_size
/= 4;
218 RENDERINPUTS_COPY( rmesa
->tnl_index_bitset
, index_bitset
);
219 if (RADEON_DEBUG
& DEBUG_VERTS
)
220 fprintf( stderr
, "%s: vertex_size= %d floats\n",
221 __FUNCTION__
, rmesa
->swtcl
.vertex_size
);
226 static void radeonRenderStart( GLcontext
*ctx
)
228 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
230 radeonSetVertexFormat( ctx
);
232 if (rmesa
->dma
.flush
!= 0 &&
233 rmesa
->dma
.flush
!= flush_last_swtcl_prim
)
234 rmesa
->dma
.flush( rmesa
);
239 * Set vertex state for SW TCL. The primary purpose of this function is to
240 * determine in advance whether or not the hardware can / should do the
241 * projection divide or Mesa should do it.
243 void radeonChooseVertexState( GLcontext
*ctx
)
245 radeonContextPtr rmesa
= RADEON_CONTEXT( ctx
);
246 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
248 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
250 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
251 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
252 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
254 /* We must ensure that we don't do _tnl_need_projected_coords while in a
255 * rasterization fallback. As this function will be called again when we
256 * leave a rasterization fallback, we can just skip it for now.
258 if (rmesa
->Fallback
!= 0)
261 /* HW perspective divide is a win, but tiny vertex formats are a
265 if ((!RENDERINPUTS_TEST_RANGE( tnl
->render_inputs_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
) &&
266 !RENDERINPUTS_TEST( tnl
->render_inputs_bitset
, _TNL_ATTRIB_COLOR1
))
267 || (ctx
->_TriangleCaps
& (DD_TRI_LIGHT_TWOSIDE
|DD_TRI_UNFILLED
))) {
268 rmesa
->swtcl
.needproj
= GL_TRUE
;
269 se_coord_fmt
|= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
270 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
);
273 rmesa
->swtcl
.needproj
= GL_FALSE
;
274 se_coord_fmt
|= (RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
277 _tnl_need_projected_coords( ctx
, rmesa
->swtcl
.needproj
);
279 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
280 RADEON_STATECHANGE( rmesa
, set
);
281 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
286 /* Flush vertices in the current dma region.
288 static void flush_last_swtcl_prim( radeonContextPtr rmesa
)
290 if (RADEON_DEBUG
& DEBUG_IOCTL
)
291 fprintf(stderr
, "%s\n", __FUNCTION__
);
293 rmesa
->dma
.flush
= NULL
;
295 if (rmesa
->dma
.current
.buf
) {
296 struct radeon_dma_region
*current
= &rmesa
->dma
.current
;
297 GLuint current_offset
= (rmesa
->radeonScreen
->gart_buffer_offset
+
298 current
->buf
->buf
->idx
* RADEON_BUFFER_SIZE
+
301 assert (!(rmesa
->swtcl
.hw_primitive
& RADEON_CP_VC_CNTL_PRIM_WALK_IND
));
303 assert (current
->start
+
304 rmesa
->swtcl
.numverts
* rmesa
->swtcl
.vertex_size
* 4 ==
307 if (rmesa
->dma
.current
.start
!= rmesa
->dma
.current
.ptr
) {
308 radeonEnsureCmdBufSpace( rmesa
, VERT_AOS_BUFSZ
+
309 rmesa
->hw
.max_state_size
+ VBUF_BUFSZ
);
311 radeonEmitVertexAOS( rmesa
,
312 rmesa
->swtcl
.vertex_size
,
315 radeonEmitVbufPrim( rmesa
,
316 rmesa
->swtcl
.vertex_format
,
317 rmesa
->swtcl
.hw_primitive
,
318 rmesa
->swtcl
.numverts
);
321 rmesa
->swtcl
.numverts
= 0;
322 current
->start
= current
->ptr
;
327 /* Alloc space in the current dma region.
330 radeonAllocDmaLowVerts( radeonContextPtr rmesa
, int nverts
, int vsize
)
332 GLuint bytes
= vsize
* nverts
;
334 if ( rmesa
->dma
.current
.ptr
+ bytes
> rmesa
->dma
.current
.end
)
335 radeonRefillCurrentDmaRegion( rmesa
);
337 if (!rmesa
->dma
.flush
) {
338 rmesa
->glCtx
->Driver
.NeedFlush
|= FLUSH_STORED_VERTICES
;
339 rmesa
->dma
.flush
= flush_last_swtcl_prim
;
342 assert( vsize
== rmesa
->swtcl
.vertex_size
* 4 );
343 assert( rmesa
->dma
.flush
== flush_last_swtcl_prim
);
344 assert (rmesa
->dma
.current
.start
+
345 rmesa
->swtcl
.numverts
* rmesa
->swtcl
.vertex_size
* 4 ==
346 rmesa
->dma
.current
.ptr
);
350 GLubyte
*head
= (GLubyte
*)(rmesa
->dma
.current
.address
+ rmesa
->dma
.current
.ptr
);
351 rmesa
->dma
.current
.ptr
+= bytes
;
352 rmesa
->swtcl
.numverts
+= nverts
;
360 * Render unclipped vertex buffers by emitting vertices directly to
361 * dma buffers. Use strip/fan hardware primitives where possible.
362 * Try to simulate missing primitives with indexed vertices.
364 #define HAVE_POINTS 1
366 #define HAVE_LINE_STRIPS 1
367 #define HAVE_TRIANGLES 1
368 #define HAVE_TRI_STRIPS 1
369 #define HAVE_TRI_STRIP_1 0
370 #define HAVE_TRI_FANS 1
372 #define HAVE_QUAD_STRIPS 0
373 #define HAVE_POLYGONS 0
374 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
377 static const GLuint hw_prim
[GL_POLYGON
+1] = {
378 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
379 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
381 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
,
382 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
383 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
,
384 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
,
391 radeonDmaPrimitive( radeonContextPtr rmesa
, GLenum prim
)
393 RADEON_NEWPRIM( rmesa
);
394 rmesa
->swtcl
.hw_primitive
= hw_prim
[prim
];
395 assert(rmesa
->dma
.current
.ptr
== rmesa
->dma
.current
.start
);
398 #define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
399 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
400 #define FLUSH() RADEON_NEWPRIM( rmesa )
401 #define GET_CURRENT_VB_MAX_VERTS() \
402 (((int)rmesa->dma.current.end - (int)rmesa->dma.current.ptr) / (rmesa->swtcl.vertex_size*4))
403 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
404 ((RADEON_BUFFER_SIZE) / (rmesa->swtcl.vertex_size*4))
405 #define ALLOC_VERTS( nr ) \
406 radeonAllocDmaLowVerts( rmesa, nr, rmesa->swtcl.vertex_size * 4 )
407 #define EMIT_VERTS( ctx, j, nr, buf ) \
408 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
410 #define TAG(x) radeon_dma_##x
411 #include "tnl_dd/t_dd_dmatmp.h"
414 /**********************************************************************/
415 /* Render pipeline stage */
416 /**********************************************************************/
419 static GLboolean
radeon_run_render( GLcontext
*ctx
,
420 struct tnl_pipeline_stage
*stage
)
422 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
423 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
424 struct vertex_buffer
*VB
= &tnl
->vb
;
425 tnl_render_func
*tab
= TAG(render_tab_verts
);
428 if (rmesa
->swtcl
.indexed_verts
.buf
)
431 if (rmesa
->swtcl
.RenderIndex
!= 0 ||
432 !radeon_dma_validate_render( ctx
, VB
))
435 tnl
->Driver
.Render
.Start( ctx
);
437 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
439 GLuint prim
= VB
->Primitive
[i
].mode
;
440 GLuint start
= VB
->Primitive
[i
].start
;
441 GLuint length
= VB
->Primitive
[i
].count
;
446 if (RADEON_DEBUG
& DEBUG_PRIMS
)
447 fprintf(stderr
, "radeon_render.c: prim %s %d..%d\n",
448 _mesa_lookup_enum_by_nr(prim
& PRIM_MODE_MASK
),
449 start
, start
+length
);
452 tab
[prim
& PRIM_MODE_MASK
]( ctx
, start
, start
+ length
, prim
);
455 tnl
->Driver
.Render
.Finish( ctx
);
457 return GL_FALSE
; /* finished the pipe */
462 const struct tnl_pipeline_stage _radeon_render_stage
=
469 radeon_run_render
/* run */
473 /**************************************************************************/
476 static const GLuint reduced_hw_prim
[GL_POLYGON
+1] = {
477 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
478 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
479 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
480 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
481 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
482 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
483 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
484 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
485 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
486 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
489 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
);
490 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
);
491 static void radeonResetLineStipple( GLcontext
*ctx
);
494 /***********************************************************************
495 * Emit primitives as inline vertices *
496 ***********************************************************************/
500 #define CTX_ARG radeonContextPtr rmesa
501 #define GET_VERTEX_DWORDS() rmesa->swtcl.vertex_size
502 #define ALLOC_VERTS( n, size ) radeonAllocDmaLowVerts( rmesa, n, (size) * 4 )
505 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
506 const char *radeonverts = (char *)rmesa->swtcl.verts;
507 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
508 #define VERTEX radeonVertex
510 #define TAG(x) radeon_##x
511 #include "tnl_dd/t_dd_triemit.h"
514 /***********************************************************************
515 * Macros for t_dd_tritmp.h to draw basic primitives *
516 ***********************************************************************/
518 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
519 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
520 #define LINE( a, b ) radeon_line( rmesa, a, b )
521 #define POINT( a ) radeon_point( rmesa, a )
523 /***********************************************************************
524 * Build render functions from dd templates *
525 ***********************************************************************/
527 #define RADEON_TWOSIDE_BIT 0x01
528 #define RADEON_UNFILLED_BIT 0x02
529 #define RADEON_MAX_TRIFUNC 0x04
533 tnl_points_func points
;
535 tnl_triangle_func triangle
;
537 } rast_tab
[RADEON_MAX_TRIFUNC
];
540 #define DO_FALLBACK 0
542 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
543 #define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
549 #define DO_FULL_QUAD 1
553 #define HAVE_BACK_COLORS 0
554 #define HAVE_HW_FLATSHADE 1
557 #define DEPTH_SCALE 1.0
558 #define UNFILLED_TRI unfilled_tri
559 #define UNFILLED_QUAD unfilled_quad
560 #define VERT_X(_v) _v->v.x
561 #define VERT_Y(_v) _v->v.y
562 #define VERT_Z(_v) _v->v.z
563 #define AREA_IS_CCW( a ) (a < 0)
564 #define GET_VERTEX(e) (rmesa->swtcl.verts + ((e) * rmesa->swtcl.vertex_size * sizeof(int)))
566 #define VERT_SET_RGBA( v, c ) \
568 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
569 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
570 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
571 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
572 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
575 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
577 #define VERT_SET_SPEC( v, c ) \
580 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
581 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
582 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
583 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
586 #define VERT_COPY_SPEC( v0, v1 ) \
589 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
590 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
591 spec0->red = spec1->red; \
592 spec0->green = spec1->green; \
593 spec0->blue = spec1->blue; \
597 /* These don't need LE32_TO_CPU() as they used to save and restore
598 * colors which are already in the correct format.
600 #define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
601 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
602 #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
603 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
609 #define LOCAL_VARS(n) \
610 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
611 GLuint color[n], spec[n]; \
612 GLuint coloroffset = rmesa->swtcl.coloroffset; \
613 GLuint specoffset = rmesa->swtcl.specoffset; \
614 (void) color; (void) spec; (void) coloroffset; (void) specoffset;
616 /***********************************************************************
617 * Helpers for rendering unfilled primitives *
618 ***********************************************************************/
620 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
621 #define RENDER_PRIMITIVE rmesa->swtcl.render_primitive
624 #include "tnl_dd/t_dd_unfilled.h"
628 /***********************************************************************
629 * Generate GL render functions *
630 ***********************************************************************/
635 #include "tnl_dd/t_dd_tritmp.h"
637 #define IND (RADEON_TWOSIDE_BIT)
638 #define TAG(x) x##_twoside
639 #include "tnl_dd/t_dd_tritmp.h"
641 #define IND (RADEON_UNFILLED_BIT)
642 #define TAG(x) x##_unfilled
643 #include "tnl_dd/t_dd_tritmp.h"
645 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
646 #define TAG(x) x##_twoside_unfilled
647 #include "tnl_dd/t_dd_tritmp.h"
650 static void init_rast_tab( void )
655 init_twoside_unfilled();
658 /**********************************************************************/
659 /* Render unclipped begin/end objects */
660 /**********************************************************************/
662 #define RENDER_POINTS( start, count ) \
663 for ( ; start < count ; start++) \
664 radeon_point( rmesa, VERT(start) )
665 #define RENDER_LINE( v0, v1 ) \
666 radeon_line( rmesa, VERT(v0), VERT(v1) )
667 #define RENDER_TRI( v0, v1, v2 ) \
668 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
669 #define RENDER_QUAD( v0, v1, v2, v3 ) \
670 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
672 #define INIT(x) do { \
673 radeonRenderPrimitive( ctx, x ); \
677 radeonContextPtr rmesa = RADEON_CONTEXT(ctx); \
678 const GLuint vertsize = rmesa->swtcl.vertex_size; \
679 const char *radeonverts = (char *)rmesa->swtcl.verts; \
680 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
681 const GLboolean stipple = ctx->Line.StippleFlag; \
682 (void) elt; (void) stipple;
683 #define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx );
684 #define RESET_OCCLUSION
685 #define PRESERVE_VB_DEFS
687 #define TAG(x) radeon_##x##_verts
688 #include "tnl/t_vb_rendertmp.h"
691 #define TAG(x) radeon_##x##_elts
692 #define ELT(x) elt[x]
693 #include "tnl/t_vb_rendertmp.h"
697 /**********************************************************************/
698 /* Choose render functions */
699 /**********************************************************************/
701 void radeonChooseRenderState( GLcontext
*ctx
)
703 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
704 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
706 GLuint flags
= ctx
->_TriangleCaps
;
708 if (!rmesa
->TclFallback
|| rmesa
->Fallback
)
711 if (flags
& DD_TRI_LIGHT_TWOSIDE
) index
|= RADEON_TWOSIDE_BIT
;
712 if (flags
& DD_TRI_UNFILLED
) index
|= RADEON_UNFILLED_BIT
;
714 if (index
!= rmesa
->swtcl
.RenderIndex
) {
715 tnl
->Driver
.Render
.Points
= rast_tab
[index
].points
;
716 tnl
->Driver
.Render
.Line
= rast_tab
[index
].line
;
717 tnl
->Driver
.Render
.ClippedLine
= rast_tab
[index
].line
;
718 tnl
->Driver
.Render
.Triangle
= rast_tab
[index
].triangle
;
719 tnl
->Driver
.Render
.Quad
= rast_tab
[index
].quad
;
722 tnl
->Driver
.Render
.PrimTabVerts
= radeon_render_tab_verts
;
723 tnl
->Driver
.Render
.PrimTabElts
= radeon_render_tab_elts
;
724 tnl
->Driver
.Render
.ClippedPolygon
= radeon_fast_clipped_poly
;
726 tnl
->Driver
.Render
.PrimTabVerts
= _tnl_render_tab_verts
;
727 tnl
->Driver
.Render
.PrimTabElts
= _tnl_render_tab_elts
;
728 tnl
->Driver
.Render
.ClippedPolygon
= _tnl_RenderClippedPolygon
;
731 rmesa
->swtcl
.RenderIndex
= index
;
736 /**********************************************************************/
737 /* High level hooks for t_vb_render.c */
738 /**********************************************************************/
741 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
)
743 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
745 if (rmesa
->swtcl
.hw_primitive
!= hwprim
) {
746 RADEON_NEWPRIM( rmesa
);
747 rmesa
->swtcl
.hw_primitive
= hwprim
;
751 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
)
753 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
754 rmesa
->swtcl
.render_primitive
= prim
;
755 if (prim
< GL_TRIANGLES
|| !(ctx
->_TriangleCaps
& DD_TRI_UNFILLED
))
756 radeonRasterPrimitive( ctx
, reduced_hw_prim
[prim
] );
759 static void radeonRenderFinish( GLcontext
*ctx
)
763 static void radeonResetLineStipple( GLcontext
*ctx
)
765 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
766 RADEON_STATECHANGE( rmesa
, lin
);
770 /**********************************************************************/
771 /* Transition to/from hardware rasterization. */
772 /**********************************************************************/
774 static const char * const fallbackStrings
[] = {
776 "glDrawBuffer(GL_FRONT_AND_BACK)",
777 "glEnable(GL_STENCIL) without hw stencil buffer",
778 "glRenderMode(selection or feedback)",
782 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
786 static const char *getFallbackString(GLuint bit
)
793 return fallbackStrings
[i
];
797 void radeonFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
799 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
800 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
801 GLuint oldfallback
= rmesa
->Fallback
;
804 rmesa
->Fallback
|= bit
;
805 if (oldfallback
== 0) {
806 RADEON_FIREVERTICES( rmesa
);
807 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_TRUE
);
808 _swsetup_Wakeup( ctx
);
809 rmesa
->swtcl
.RenderIndex
= ~0;
810 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
811 fprintf(stderr
, "Radeon begin rasterization fallback: 0x%x %s\n",
812 bit
, getFallbackString(bit
));
817 rmesa
->Fallback
&= ~bit
;
818 if (oldfallback
== bit
) {
819 _swrast_flush( ctx
);
820 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
821 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
822 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
824 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
825 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
826 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
828 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
829 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_FALSE
);
830 if (rmesa
->TclFallback
) {
831 /* These are already done if rmesa->TclFallback goes to
832 * zero above. But not if it doesn't (RADEON_NO_TCL for
835 _tnl_invalidate_vertex_state( ctx
, ~0 );
836 _tnl_invalidate_vertices( ctx
, ~0 );
837 RENDERINPUTS_ZERO( rmesa
->tnl_index_bitset
);
838 radeonChooseVertexState( ctx
);
839 radeonChooseRenderState( ctx
);
841 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
842 fprintf(stderr
, "Radeon end rasterization fallback: 0x%x %s\n",
843 bit
, getFallbackString(bit
));
850 /**********************************************************************/
851 /* Initialization. */
852 /**********************************************************************/
854 void radeonInitSwtcl( GLcontext
*ctx
)
856 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
857 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
858 static int firsttime
= 1;
865 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
866 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
867 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
868 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
869 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
870 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
871 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
873 _tnl_init_vertices( ctx
, ctx
->Const
.MaxArrayLockSize
+ 12,
874 RADEON_MAX_TNL_VERTEX_SIZE
);
876 rmesa
->swtcl
.verts
= (GLubyte
*)tnl
->clipspace
.vertex_buf
;
877 rmesa
->swtcl
.RenderIndex
= ~0;
878 rmesa
->swtcl
.render_primitive
= GL_TRIANGLES
;
879 rmesa
->swtcl
.hw_primitive
= 0;
883 void radeonDestroySwtcl( GLcontext
*ctx
)
885 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
887 if (rmesa
->swtcl
.indexed_verts
.buf
)
888 radeonReleaseDmaRegion( rmesa
, &rmesa
->swtcl
.indexed_verts
,