1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/mtypes.h"
37 #include "main/colormac.h"
38 #include "main/enums.h"
39 #include "main/imports.h"
40 #include "main/macros.h"
41 #include "main/simple_list.h"
43 #include "swrast_setup/swrast_setup.h"
44 #include "math/m_translate.h"
46 #include "tnl/t_context.h"
47 #include "tnl/t_pipeline.h"
49 #include "radeon_context.h"
50 #include "radeon_ioctl.h"
51 #include "radeon_state.h"
52 #include "radeon_swtcl.h"
53 #include "radeon_tcl.h"
54 #include "radeon_debug.h"
57 /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
58 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
59 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */
61 /***********************************************************************
63 ***********************************************************************/
65 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
67 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
68 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
69 rmesa->radeon.swtcl.vertex_attr_count++; \
73 #define EMIT_PAD( N ) \
75 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
76 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
77 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
78 rmesa->radeon.swtcl.vertex_attr_count++; \
81 static GLuint radeon_cp_vc_frmts
[3][2] =
83 { RADEON_CP_VC_FRMT_ST0
, RADEON_CP_VC_FRMT_ST0
| RADEON_CP_VC_FRMT_Q0
},
84 { RADEON_CP_VC_FRMT_ST1
, RADEON_CP_VC_FRMT_ST1
| RADEON_CP_VC_FRMT_Q1
},
85 { RADEON_CP_VC_FRMT_ST2
, RADEON_CP_VC_FRMT_ST2
| RADEON_CP_VC_FRMT_Q2
},
88 static void radeonSetVertexFormat( GLcontext
*ctx
)
90 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
91 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
92 struct vertex_buffer
*VB
= &tnl
->vb
;
93 DECLARE_RENDERINPUTS(index_bitset
);
97 RENDERINPUTS_COPY( index_bitset
, tnl
->render_inputs_bitset
);
101 if ( VB
->NdcPtr
!= NULL
) {
102 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
105 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->ClipPtr
;
108 assert( VB
->AttribPtr
[VERT_ATTRIB_POS
] != NULL
);
109 rmesa
->radeon
.swtcl
.vertex_attr_count
= 0;
111 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
112 * build up a hardware vertex.
114 if ( !rmesa
->swtcl
.needproj
||
115 RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) { /* for projtex */
116 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_4F
,
117 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
| RADEON_CP_VC_FRMT_W0
);
121 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_3F
,
122 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
);
126 rmesa
->swtcl
.coloroffset
= offset
;
127 #if MESA_LITTLE_ENDIAN
128 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_RGBA
,
129 RADEON_CP_VC_FRMT_PKCOLOR
);
131 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_ABGR
,
132 RADEON_CP_VC_FRMT_PKCOLOR
);
136 rmesa
->swtcl
.specoffset
= 0;
137 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
) ||
138 RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
140 #if MESA_LITTLE_ENDIAN
141 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
142 rmesa
->swtcl
.specoffset
= offset
;
143 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_RGB
,
144 RADEON_CP_VC_FRMT_PKSPEC
);
150 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
151 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
152 RADEON_CP_VC_FRMT_PKSPEC
);
158 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
159 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
160 RADEON_CP_VC_FRMT_PKSPEC
);
166 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
167 rmesa
->swtcl
.specoffset
= offset
;
168 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
,
169 RADEON_CP_VC_FRMT_PKSPEC
);
177 if (RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
180 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
181 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_TEX(i
) )) {
182 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
187 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_2F
,
188 radeon_cp_vc_frmts
[i
][0] );
192 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
& (TEXTURE_CUBE_BIT
) ) {
193 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F
,
194 radeon_cp_vc_frmts
[i
][1] );
196 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F_XYW
,
197 radeon_cp_vc_frmts
[i
][1] );
207 if (!RENDERINPUTS_EQUAL( rmesa
->radeon
.tnl_index_bitset
, index_bitset
) ||
208 fmt_0
!= rmesa
->swtcl
.vertex_format
) {
209 RADEON_NEWPRIM(rmesa
);
210 rmesa
->swtcl
.vertex_format
= fmt_0
;
211 rmesa
->radeon
.swtcl
.vertex_size
=
212 _tnl_install_attrs( ctx
,
213 rmesa
->radeon
.swtcl
.vertex_attrs
,
214 rmesa
->radeon
.swtcl
.vertex_attr_count
,
216 rmesa
->radeon
.swtcl
.vertex_size
/= 4;
217 RENDERINPUTS_COPY( rmesa
->radeon
.tnl_index_bitset
, index_bitset
);
218 radeon_print(RADEON_SWRENDER
, RADEON_VERBOSE
,
219 "%s: vertex_size= %d floats\n", __FUNCTION__
, rmesa
->radeon
.swtcl
.vertex_size
);
223 static void radeon_predict_emit_size( r100ContextPtr rmesa
)
226 if (!rmesa
->radeon
.swtcl
.emit_prediction
) {
227 const int state_size
= radeonCountStateEmitSize( &rmesa
->radeon
);
228 const int scissor_size
= 8;
229 const int prims_size
= 8;
230 const int vertex_size
= 7;
232 if (rcommonEnsureCmdBufSpace(&rmesa
->radeon
,
234 (scissor_size
+ prims_size
+ vertex_size
),
236 rmesa
->radeon
.swtcl
.emit_prediction
= radeonCountStateEmitSize( &rmesa
->radeon
);
238 rmesa
->radeon
.swtcl
.emit_prediction
= state_size
;
239 rmesa
->radeon
.swtcl
.emit_prediction
+= scissor_size
+ prims_size
+ vertex_size
240 + rmesa
->radeon
.cmdbuf
.cs
->cdw
;
244 static void radeonRenderStart( GLcontext
*ctx
)
246 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
248 radeonSetVertexFormat( ctx
);
250 if (rmesa
->radeon
.dma
.flush
!= 0 &&
251 rmesa
->radeon
.dma
.flush
!= rcommon_flush_last_swtcl_prim
)
252 rmesa
->radeon
.dma
.flush( ctx
);
257 * Set vertex state for SW TCL. The primary purpose of this function is to
258 * determine in advance whether or not the hardware can / should do the
259 * projection divide or Mesa should do it.
261 void radeonChooseVertexState( GLcontext
*ctx
)
263 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
264 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
266 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
268 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
269 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
270 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
272 /* We must ensure that we don't do _tnl_need_projected_coords while in a
273 * rasterization fallback. As this function will be called again when we
274 * leave a rasterization fallback, we can just skip it for now.
276 if (rmesa
->radeon
.Fallback
!= 0)
279 /* HW perspective divide is a win, but tiny vertex formats are a
283 if ((!RENDERINPUTS_TEST_RANGE( tnl
->render_inputs_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
) &&
284 !RENDERINPUTS_TEST( tnl
->render_inputs_bitset
, _TNL_ATTRIB_COLOR1
))
285 || (ctx
->_TriangleCaps
& (DD_TRI_LIGHT_TWOSIDE
|DD_TRI_UNFILLED
))) {
286 rmesa
->swtcl
.needproj
= GL_TRUE
;
287 se_coord_fmt
|= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
288 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
);
291 rmesa
->swtcl
.needproj
= GL_FALSE
;
292 se_coord_fmt
|= (RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
295 _tnl_need_projected_coords( ctx
, rmesa
->swtcl
.needproj
);
297 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
298 RADEON_STATECHANGE( rmesa
, set
);
299 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
303 void r100_swtcl_flush(GLcontext
*ctx
, uint32_t current_offset
)
305 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
309 radeonEmitState(&rmesa
->radeon
);
310 radeonEmitVertexAOS( rmesa
,
311 rmesa
->radeon
.swtcl
.vertex_size
,
312 first_elem(&rmesa
->radeon
.dma
.reserved
)->bo
,
316 radeonEmitVbufPrim( rmesa
,
317 rmesa
->swtcl
.vertex_format
,
318 rmesa
->radeon
.swtcl
.hw_primitive
,
319 rmesa
->radeon
.swtcl
.numverts
);
320 if ( rmesa
->radeon
.swtcl
.emit_prediction
< rmesa
->radeon
.cmdbuf
.cs
->cdw
)
321 WARN_ONCE("Rendering was %d commands larger than predicted size."
322 " We might overflow command buffer.\n",
323 rmesa
->radeon
.cmdbuf
.cs
->cdw
- rmesa
->radeon
.swtcl
.emit_prediction
);
326 rmesa
->radeon
.swtcl
.emit_prediction
= 0;
331 * Render unclipped vertex buffers by emitting vertices directly to
332 * dma buffers. Use strip/fan hardware primitives where possible.
333 * Try to simulate missing primitives with indexed vertices.
335 #define HAVE_POINTS 1
337 #define HAVE_LINE_STRIPS 1
338 #define HAVE_TRIANGLES 1
339 #define HAVE_TRI_STRIPS 1
340 #define HAVE_TRI_STRIP_1 0
341 #define HAVE_TRI_FANS 1
343 #define HAVE_QUAD_STRIPS 0
344 #define HAVE_POLYGONS 0
345 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
348 static const GLuint hw_prim
[GL_POLYGON
+1] = {
349 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
350 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
352 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
,
353 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
354 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
,
355 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
,
362 radeonDmaPrimitive( r100ContextPtr rmesa
, GLenum prim
)
364 RADEON_NEWPRIM( rmesa
);
365 rmesa
->radeon
.swtcl
.hw_primitive
= hw_prim
[prim
];
366 // assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
369 static void* radeon_alloc_verts( r100ContextPtr rmesa
, GLuint nr
, GLuint size
)
373 radeon_predict_emit_size( rmesa
);
374 rv
= rcommonAllocDmaLowVerts( &rmesa
->radeon
, nr
, size
);
379 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
380 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
381 #define FLUSH() RADEON_NEWPRIM( rmesa )
382 #define GET_CURRENT_VB_MAX_VERTS() 10\
383 // (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
384 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
385 ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
386 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
387 #define EMIT_VERTS( ctx, j, nr, buf ) \
388 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
390 #define TAG(x) radeon_dma_##x
391 #include "tnl_dd/t_dd_dmatmp.h"
394 /**********************************************************************/
395 /* Render pipeline stage */
396 /**********************************************************************/
399 static GLboolean
radeon_run_render( GLcontext
*ctx
,
400 struct tnl_pipeline_stage
*stage
)
402 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
403 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
404 struct vertex_buffer
*VB
= &tnl
->vb
;
405 tnl_render_func
*tab
= TAG(render_tab_verts
);
408 if (rmesa
->radeon
.swtcl
.RenderIndex
!= 0 ||
409 !radeon_dma_validate_render( ctx
, VB
))
412 tnl
->Driver
.Render
.Start( ctx
);
414 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
416 GLuint prim
= VB
->Primitive
[i
].mode
;
417 GLuint start
= VB
->Primitive
[i
].start
;
418 GLuint length
= VB
->Primitive
[i
].count
;
423 radeon_print(RADEON_SWRENDER
, RADEON_NORMAL
,
424 "radeon_render.c: prim %s %d..%d\n",
425 _mesa_lookup_enum_by_nr(prim
& PRIM_MODE_MASK
),
426 start
, start
+length
);
429 tab
[prim
& PRIM_MODE_MASK
]( ctx
, start
, start
+ length
, prim
);
432 tnl
->Driver
.Render
.Finish( ctx
);
434 return GL_FALSE
; /* finished the pipe */
439 const struct tnl_pipeline_stage _radeon_render_stage
=
446 radeon_run_render
/* run */
450 /**************************************************************************/
453 static const GLuint reduced_hw_prim
[GL_POLYGON
+1] = {
454 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
455 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
456 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
457 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
458 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
459 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
460 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
461 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
462 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
463 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
466 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
);
467 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
);
468 static void radeonResetLineStipple( GLcontext
*ctx
);
471 /***********************************************************************
472 * Emit primitives as inline vertices *
473 ***********************************************************************/
477 #define CTX_ARG r100ContextPtr rmesa
478 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
479 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
482 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
483 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
484 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
485 #define VERTEX radeonVertex
487 #define TAG(x) radeon_##x
488 #include "tnl_dd/t_dd_triemit.h"
491 /***********************************************************************
492 * Macros for t_dd_tritmp.h to draw basic primitives *
493 ***********************************************************************/
495 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
496 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
497 #define LINE( a, b ) radeon_line( rmesa, a, b )
498 #define POINT( a ) radeon_point( rmesa, a )
500 /***********************************************************************
501 * Build render functions from dd templates *
502 ***********************************************************************/
504 #define RADEON_TWOSIDE_BIT 0x01
505 #define RADEON_UNFILLED_BIT 0x02
506 #define RADEON_MAX_TRIFUNC 0x04
510 tnl_points_func points
;
512 tnl_triangle_func triangle
;
514 } rast_tab
[RADEON_MAX_TRIFUNC
];
517 #define DO_FALLBACK 0
519 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
520 #define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
526 #define DO_FULL_QUAD 1
530 #define HAVE_BACK_COLORS 0
531 #define HAVE_HW_FLATSHADE 1
534 #define DEPTH_SCALE 1.0
535 #define UNFILLED_TRI unfilled_tri
536 #define UNFILLED_QUAD unfilled_quad
537 #define VERT_X(_v) _v->v.x
538 #define VERT_Y(_v) _v->v.y
539 #define VERT_Z(_v) _v->v.z
540 #define AREA_IS_CCW( a ) (a < 0)
541 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
543 #define VERT_SET_RGBA( v, c ) \
545 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
546 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
547 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
548 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
549 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
552 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
554 #define VERT_SET_SPEC( v, c ) \
557 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
558 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
559 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
560 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
563 #define VERT_COPY_SPEC( v0, v1 ) \
566 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
567 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
568 spec0->red = spec1->red; \
569 spec0->green = spec1->green; \
570 spec0->blue = spec1->blue; \
574 /* These don't need LE32_TO_CPU() as they used to save and restore
575 * colors which are already in the correct format.
577 #define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
578 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
579 #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
580 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
586 #define LOCAL_VARS(n) \
587 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
588 GLuint color[n] = {0}, spec[n] = {0}; \
589 GLuint coloroffset = rmesa->swtcl.coloroffset; \
590 GLuint specoffset = rmesa->swtcl.specoffset; \
591 (void) color; (void) spec; (void) coloroffset; (void) specoffset;
593 /***********************************************************************
594 * Helpers for rendering unfilled primitives *
595 ***********************************************************************/
597 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
598 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
601 #include "tnl_dd/t_dd_unfilled.h"
605 /***********************************************************************
606 * Generate GL render functions *
607 ***********************************************************************/
612 #include "tnl_dd/t_dd_tritmp.h"
614 #define IND (RADEON_TWOSIDE_BIT)
615 #define TAG(x) x##_twoside
616 #include "tnl_dd/t_dd_tritmp.h"
618 #define IND (RADEON_UNFILLED_BIT)
619 #define TAG(x) x##_unfilled
620 #include "tnl_dd/t_dd_tritmp.h"
622 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
623 #define TAG(x) x##_twoside_unfilled
624 #include "tnl_dd/t_dd_tritmp.h"
627 static void init_rast_tab( void )
632 init_twoside_unfilled();
635 /**********************************************************************/
636 /* Render unclipped begin/end objects */
637 /**********************************************************************/
639 #define RENDER_POINTS( start, count ) \
640 for ( ; start < count ; start++) \
641 radeon_point( rmesa, VERT(start) )
642 #define RENDER_LINE( v0, v1 ) \
643 radeon_line( rmesa, VERT(v0), VERT(v1) )
644 #define RENDER_TRI( v0, v1, v2 ) \
645 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
646 #define RENDER_QUAD( v0, v1, v2, v3 ) \
647 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
649 #define INIT(x) do { \
650 radeonRenderPrimitive( ctx, x ); \
654 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
655 const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
656 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; \
657 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
658 const GLboolean stipple = ctx->Line.StippleFlag; \
659 (void) elt; (void) stipple;
660 #define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx );
661 #define RESET_OCCLUSION
662 #define PRESERVE_VB_DEFS
664 #define TAG(x) radeon_##x##_verts
665 #include "tnl/t_vb_rendertmp.h"
668 #define TAG(x) radeon_##x##_elts
669 #define ELT(x) elt[x]
670 #include "tnl/t_vb_rendertmp.h"
674 /**********************************************************************/
675 /* Choose render functions */
676 /**********************************************************************/
678 void radeonChooseRenderState( GLcontext
*ctx
)
680 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
681 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
683 GLuint flags
= ctx
->_TriangleCaps
;
685 if (!rmesa
->radeon
.TclFallback
|| rmesa
->radeon
.Fallback
)
688 if (flags
& DD_TRI_LIGHT_TWOSIDE
) index
|= RADEON_TWOSIDE_BIT
;
689 if (flags
& DD_TRI_UNFILLED
) index
|= RADEON_UNFILLED_BIT
;
691 if (index
!= rmesa
->radeon
.swtcl
.RenderIndex
) {
692 tnl
->Driver
.Render
.Points
= rast_tab
[index
].points
;
693 tnl
->Driver
.Render
.Line
= rast_tab
[index
].line
;
694 tnl
->Driver
.Render
.ClippedLine
= rast_tab
[index
].line
;
695 tnl
->Driver
.Render
.Triangle
= rast_tab
[index
].triangle
;
696 tnl
->Driver
.Render
.Quad
= rast_tab
[index
].quad
;
699 tnl
->Driver
.Render
.PrimTabVerts
= radeon_render_tab_verts
;
700 tnl
->Driver
.Render
.PrimTabElts
= radeon_render_tab_elts
;
701 tnl
->Driver
.Render
.ClippedPolygon
= radeon_fast_clipped_poly
;
703 tnl
->Driver
.Render
.PrimTabVerts
= _tnl_render_tab_verts
;
704 tnl
->Driver
.Render
.PrimTabElts
= _tnl_render_tab_elts
;
705 tnl
->Driver
.Render
.ClippedPolygon
= _tnl_RenderClippedPolygon
;
708 rmesa
->radeon
.swtcl
.RenderIndex
= index
;
713 /**********************************************************************/
714 /* High level hooks for t_vb_render.c */
715 /**********************************************************************/
718 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
)
720 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
722 if (rmesa
->radeon
.swtcl
.hw_primitive
!= hwprim
) {
723 RADEON_NEWPRIM( rmesa
);
724 rmesa
->radeon
.swtcl
.hw_primitive
= hwprim
;
728 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
)
730 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
731 rmesa
->radeon
.swtcl
.render_primitive
= prim
;
732 if (prim
< GL_TRIANGLES
|| !(ctx
->_TriangleCaps
& DD_TRI_UNFILLED
))
733 radeonRasterPrimitive( ctx
, reduced_hw_prim
[prim
] );
736 static void radeonRenderFinish( GLcontext
*ctx
)
740 static void radeonResetLineStipple( GLcontext
*ctx
)
742 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
743 RADEON_STATECHANGE( rmesa
, lin
);
747 /**********************************************************************/
748 /* Transition to/from hardware rasterization. */
749 /**********************************************************************/
751 static const char * const fallbackStrings
[] = {
753 "glDrawBuffer(GL_FRONT_AND_BACK)",
754 "glEnable(GL_STENCIL) without hw stencil buffer",
755 "glRenderMode(selection or feedback)",
759 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
763 static const char *getFallbackString(GLuint bit
)
770 return fallbackStrings
[i
];
774 void radeonFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
776 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
777 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
778 GLuint oldfallback
= rmesa
->radeon
.Fallback
;
781 rmesa
->radeon
.Fallback
|= bit
;
782 if (oldfallback
== 0) {
783 radeon_firevertices(&rmesa
->radeon
);
784 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_TRUE
);
785 _swsetup_Wakeup( ctx
);
786 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
787 if (RADEON_DEBUG
& RADEON_FALLBACKS
) {
788 fprintf(stderr
, "Radeon begin rasterization fallback: 0x%x %s\n",
789 bit
, getFallbackString(bit
));
794 rmesa
->radeon
.Fallback
&= ~bit
;
795 if (oldfallback
== bit
) {
796 _swrast_flush( ctx
);
797 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
798 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
799 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
801 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
802 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
803 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
805 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
806 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_FALSE
);
807 if (rmesa
->radeon
.TclFallback
) {
808 /* These are already done if rmesa->radeon.TclFallback goes to
809 * zero above. But not if it doesn't (RADEON_NO_TCL for
812 _tnl_invalidate_vertex_state( ctx
, ~0 );
813 _tnl_invalidate_vertices( ctx
, ~0 );
814 RENDERINPUTS_ZERO( rmesa
->radeon
.tnl_index_bitset
);
815 radeonChooseVertexState( ctx
);
816 radeonChooseRenderState( ctx
);
818 if (RADEON_DEBUG
& RADEON_FALLBACKS
) {
819 fprintf(stderr
, "Radeon end rasterization fallback: 0x%x %s\n",
820 bit
, getFallbackString(bit
));
827 /**********************************************************************/
828 /* Initialization. */
829 /**********************************************************************/
831 void radeonInitSwtcl( GLcontext
*ctx
)
833 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
834 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
835 static int firsttime
= 1;
841 rmesa
->radeon
.swtcl
.emit_prediction
= 0;
843 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
844 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
845 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
846 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
847 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
848 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
849 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
851 _tnl_init_vertices( ctx
, ctx
->Const
.MaxArrayLockSize
+ 12,
852 RADEON_MAX_TNL_VERTEX_SIZE
);
854 rmesa
->radeon
.swtcl
.verts
= (GLubyte
*)tnl
->clipspace
.vertex_buf
;
855 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
856 rmesa
->radeon
.swtcl
.render_primitive
= GL_TRIANGLES
;
857 rmesa
->radeon
.swtcl
.hw_primitive
= 0;