src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keithw@vmware.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "util/simple_list.h"
  42
  43 #include "math/m_xform.h"
  44
  45 #include "swrast_setup/swrast_setup.h"
  46
  47 #include "tnl/tnl.h"
  48 #include "tnl/t_context.h"
  49 #include "tnl/t_pipeline.h"
  50
  51 #include "radeon_context.h"
  52 #include "radeon_ioctl.h"
  53 #include "radeon_state.h"
  54 #include "radeon_swtcl.h"
  55 #include "radeon_tcl.h"
  56 #include "radeon_debug.h"
  57
  58
  59 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  60 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  61 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  62
  63 /***********************************************************************
  64  *                         Initialization
  65  ***********************************************************************/
  66
  67 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  68 do {                                                                    \
  69    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  70    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  71    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  72    fmt_0 |= F0;                                                         \
  73 } while (0)
  74
  75 #define EMIT_PAD( N )                                                   \
  76 do {                                                                    \
  77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  78    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  79    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  80    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  81 } while (0)
  82
  83 static GLuint radeon_cp_vc_frmts[3][2] =
  84 {
  85    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  86    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  87    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  88 };
  89
  90 static void radeonSetVertexFormat( struct gl_context *ctx )
  91 {
  92    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  93    TNLcontext *tnl = TNL_CONTEXT(ctx);
  94    struct vertex_buffer *VB = &tnl->vb;
  95    GLbitfield64 index_bitset = tnl->render_inputs_bitset;
  96    int fmt_0 = 0;
  97    int offset = 0;
  98
  99    /* Important:
 100     */
 101    if ( VB->NdcPtr != NULL ) {
 102       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 103    }
 104    else {
 105       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 106    }
 107
 108    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 109    rmesa->radeon.swtcl.vertex_attr_count = 0;
 110
 111    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 112     * build up a hardware vertex.
 113     */
 114    if ( !rmesa->swtcl.needproj ||
 115         (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
 116       /* for projtex */
 117       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 118                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 119       offset = 4;
 120    }
 121    else {
 122       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 123                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 124       offset = 3;
 125    }
 126
 127    rmesa->swtcl.coloroffset = offset;
 128 #if MESA_LITTLE_ENDIAN
 129    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 130               RADEON_CP_VC_FRMT_PKCOLOR );
 131 #else
 132    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 133               RADEON_CP_VC_FRMT_PKCOLOR );
 134 #endif
 135    offset += 1;
 136
 137    rmesa->swtcl.specoffset = 0;
 138    if (index_bitset &
 139        (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
 140
 141 #if MESA_LITTLE_ENDIAN
 142       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 143          rmesa->swtcl.specoffset = offset;
 144          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 145                     RADEON_CP_VC_FRMT_PKSPEC );
 146       }
 147       else {
 148          EMIT_PAD( 3 );
 149       }
 150
 151       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 152          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 153                     RADEON_CP_VC_FRMT_PKSPEC );
 154       }
 155       else {
 156          EMIT_PAD( 1 );
 157       }
 158 #else
 159       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 160          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 161                     RADEON_CP_VC_FRMT_PKSPEC );
 162       }
 163       else {
 164          EMIT_PAD( 1 );
 165       }
 166
 167       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 168          rmesa->swtcl.specoffset = offset;
 169          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 170                     RADEON_CP_VC_FRMT_PKSPEC );
 171       }
 172       else {
 173          EMIT_PAD( 3 );
 174       }
 175 #endif
 176    }
 177
 178    if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
 179       int i;
 180
 181       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 182          if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
 183             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 184
 185             switch (sz) {
 186             case 1:
 187             case 2:
 188                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 189                           radeon_cp_vc_frmts[i][0] );
 190                break;
 191             case 3:
 192                if (ctx->Texture.Unit[i]._Current &&
 193                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
 194                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 195                               radeon_cp_vc_frmts[i][1] );
 196                } else {
 197                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 198                               radeon_cp_vc_frmts[i][0] );
 199                }
 200                break;
 201             case 4:
 202                if (ctx->Texture.Unit[i]._Current &&
 203                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
 204                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 205                              radeon_cp_vc_frmts[i][1] );
 206                } else {
 207                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 208                              radeon_cp_vc_frmts[i][1] );
 209                }
 210                break;
 211             default:
 212                continue;
 213             };
 214          }
 215       }
 216    }
 217
 218    if (rmesa->radeon.tnl_index_bitset != index_bitset ||
 219        fmt_0 != rmesa->swtcl.vertex_format) {
 220       RADEON_NEWPRIM(rmesa);
 221       rmesa->swtcl.vertex_format = fmt_0;
 222       rmesa->radeon.swtcl.vertex_size =
 223           _tnl_install_attrs( ctx,
 224                               rmesa->radeon.swtcl.vertex_attrs,
 225                               rmesa->radeon.swtcl.vertex_attr_count,
 226                               NULL, 0 );
 227       rmesa->radeon.swtcl.vertex_size /= 4;
 228       rmesa->radeon.tnl_index_bitset = index_bitset;
 229       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 230           "%s: vertex_size= %d floats\n",  __func__, rmesa->radeon.swtcl.vertex_size);
 231    }
 232 }
 233
 234 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 235 {
 236
 237     if (!rmesa->radeon.swtcl.emit_prediction) {
 238         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 239         const int scissor_size = 8;
 240         const int prims_size = 8;
 241         const int vertex_size = 7;
 242
 243         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 244                     state_size +
 245                     (scissor_size + prims_size + vertex_size),
 246                     __func__))
 247             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 248         else
 249             rmesa->radeon.swtcl.emit_prediction = state_size;
 250         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 251             + rmesa->radeon.cmdbuf.cs->cdw;
 252     }
 253 }
 254
 255 static void radeonRenderStart( struct gl_context *ctx )
 256 {
 257     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 258
 259     radeonSetVertexFormat( ctx );
 260
 261     if (rmesa->radeon.dma.flush != 0 &&
 262             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 263         rmesa->radeon.dma.flush( ctx );
 264 }
 265
 266
 267 /**
 268  * Set vertex state for SW TCL.  The primary purpose of this function is to
 269  * determine in advance whether or not the hardware can / should do the
 270  * projection divide or Mesa should do it.
 271  */
 272 void radeonChooseVertexState( struct gl_context *ctx )
 273 {
 274    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 275    TNLcontext *tnl = TNL_CONTEXT(ctx);
 276
 277    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 278    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 279                          ctx->Polygon.BackMode != GL_FILL);
 280    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 281
 282    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 283                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 284                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 285
 286    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 287     * rasterization fallback.  As this function will be called again when we
 288     * leave a rasterization fallback, we can just skip it for now.
 289     */
 290    if (rmesa->radeon.Fallback != 0)
 291       return;
 292
 293    /* HW perspective divide is a win, but tiny vertex formats are a
 294     * bigger one.
 295     */
 296
 297    if ((0 == (tnl->render_inputs_bitset &
 298         (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
 299          | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
 300        || twosided
 301        || unfilled) {
 302       rmesa->swtcl.needproj = GL_TRUE;
 303       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 304                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 305    }
 306    else {
 307       rmesa->swtcl.needproj = GL_FALSE;
 308       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 309    }
 310
 311    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 312
 313    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 314       RADEON_STATECHANGE( rmesa, set );
 315       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 316    }
 317 }
 318
 319 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
 320 {
 321    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 322
 323
 324
 325    radeonEmitState(&rmesa->radeon);
 326    radeonEmitVertexAOS( rmesa,
 327                         rmesa->radeon.swtcl.vertex_size,
 328                         rmesa->radeon.swtcl.bo,
 329                         current_offset);
 330
 331
 332    radeonEmitVbufPrim( rmesa,
 333                        rmesa->swtcl.vertex_format,
 334                        rmesa->radeon.swtcl.hw_primitive,
 335                        rmesa->radeon.swtcl.numverts);
 336    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 337      WARN_ONCE("Rendering was %d commands larger than predicted size."
 338          " We might overflow  command buffer.\n",
 339          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 340
 341
 342    rmesa->radeon.swtcl.emit_prediction = 0;
 343
 344 }
 345
 346 /*
 347  * Render unclipped vertex buffers by emitting vertices directly to
 348  * dma buffers.  Use strip/fan hardware primitives where possible.
 349  * Try to simulate missing primitives with indexed vertices.
 350  */
 351 #define HAVE_POINTS      1
 352 #define HAVE_LINES       1
 353 #define HAVE_LINE_STRIPS 1
 354 #define HAVE_TRIANGLES   1
 355 #define HAVE_TRI_STRIPS  1
 356 #define HAVE_TRI_FANS    1
 357 #define HAVE_POLYGONS    0
 358 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 359 #define HAVE_ELTS        0
 360
 361 static const GLuint hw_prim[GL_POLYGON+1] = {
 362    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 363    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 364    0,
 365    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 366    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 367    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 368    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 369    0,
 370    0,
 371    0
 372 };
 373
 374 static inline void
 375 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 376 {
 377    RADEON_NEWPRIM( rmesa );
 378    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 379    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 380 }
 381
 382 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 383 {
 384    void *rv;
 385    do {
 386      radeon_predict_emit_size( rmesa );
 387      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 388    } while (!rv);
 389    return rv;
 390 }
 391
 392 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 393 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 394 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 395 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 396 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 397 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 398   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 399 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 400 #define EMIT_VERTS( ctx, j, nr, buf ) \
 401   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 402
 403 #define TAG(x) radeon_dma_##x
 404 #include "tnl_dd/t_dd_dmatmp.h"
 405
 406
 407 /**********************************************************************/
 408 /*                          Render pipeline stage                     */
 409 /**********************************************************************/
 410
 411
 412 static GLboolean radeon_run_render( struct gl_context *ctx,
 413                                     struct tnl_pipeline_stage *stage )
 414 {
 415    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 416    TNLcontext *tnl = TNL_CONTEXT(ctx);
 417    struct vertex_buffer *VB = &tnl->vb;
 418    tnl_render_func *tab = TAG(render_tab_verts);
 419    GLuint i;
 420
 421    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 422        !radeon_dma_validate_render( ctx, VB ))
 423       return GL_TRUE;
 424
 425    radeon_prepare_render(&rmesa->radeon);
 426    if (rmesa->radeon.NewGLState)
 427       radeonValidateState( ctx );
 428
 429    tnl->Driver.Render.Start( ctx );
 430
 431    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 432    {
 433       GLuint prim = VB->Primitive[i].mode;
 434       GLuint start = VB->Primitive[i].start;
 435       GLuint length = VB->Primitive[i].count;
 436
 437       if (!length)
 438          continue;
 439
 440       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 441           "radeon_render.c: prim %s %d..%d\n",
 442                  _mesa_enum_to_string(prim & PRIM_MODE_MASK),
 443                  start, start+length);
 444
 445       if (length)
 446          tab[prim & PRIM_MODE_MASK](ctx, start, length, prim);
 447    }
 448
 449    tnl->Driver.Render.Finish( ctx );
 450
 451    return GL_FALSE;             /* finished the pipe */
 452 }
 453
 454
 455
 456 const struct tnl_pipeline_stage _radeon_render_stage =
 457 {
 458    "radeon render",
 459    NULL,
 460    NULL,
 461    NULL,
 462    NULL,
 463    radeon_run_render            /* run */
 464 };
 465
 466
 467 /**************************************************************************/
 468
 469
 470 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 471    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 472    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 473    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 474    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 475    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 476    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 477    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 478    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 479    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 480    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 481 };
 482
 483 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
 484 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
 485 static void radeonResetLineStipple( struct gl_context *ctx );
 486
 487
 488 /***********************************************************************
 489  *                    Emit primitives as inline vertices               *
 490  ***********************************************************************/
 491
 492 #undef LOCAL_VARS
 493 #undef ALLOC_VERTS
 494 #define CTX_ARG r100ContextPtr rmesa
 495 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 496 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 497 #undef LOCAL_VARS
 498 #define LOCAL_VARS                                              \
 499    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 500    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 501 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 502 #define VERTEX radeonVertex
 503 #undef TAG
 504 #define TAG(x) radeon_##x
 505 #include "tnl_dd/t_dd_triemit.h"
 506
 507
 508 /***********************************************************************
 509  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 510  ***********************************************************************/
 511
 512 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 513 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 514 #define LINE( a, b )       radeon_line( rmesa, a, b )
 515 #define POINT( a )         radeon_point( rmesa, a )
 516
 517 /***********************************************************************
 518  *              Build render functions from dd templates               *
 519  ***********************************************************************/
 520
 521 #define RADEON_TWOSIDE_BIT      0x01
 522 #define RADEON_UNFILLED_BIT     0x02
 523 #define RADEON_MAX_TRIFUNC      0x04
 524
 525
 526 static struct {
 527    tnl_points_func              points;
 528    tnl_line_func                line;
 529    tnl_triangle_func    triangle;
 530    tnl_quad_func                quad;
 531 } rast_tab[RADEON_MAX_TRIFUNC];
 532
 533
 534 #define DO_FALLBACK  0
 535 #define DO_OFFSET    0
 536 #define DO_UNFILLED ((IND & RADEON_UNFILLED_BIT) != 0)
 537 #define DO_TWOSIDE  ((IND & RADEON_TWOSIDE_BIT) != 0)
 538 #define DO_FLAT      0
 539 #define DO_TRI       1
 540 #define DO_QUAD      1
 541 #define DO_LINE      1
 542 #define DO_POINTS    1
 543 #define DO_FULL_QUAD 1
 544
 545 #define HAVE_SPEC   1
 546 #define HAVE_BACK_COLORS  0
 547 #define HAVE_HW_FLATSHADE 1
 548 #define TAB rast_tab
 549
 550 #define DEPTH_SCALE 1.0
 551 #define UNFILLED_TRI unfilled_tri
 552 #define UNFILLED_QUAD unfilled_quad
 553 #define VERT_X(_v) _v->v.x
 554 #define VERT_Y(_v) _v->v.y
 555 #define VERT_Z(_v) _v->v.z
 556 #define AREA_IS_CCW( a ) (a < 0)
 557 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 558
 559 #define VERT_SET_RGBA( v, c )                                   \
 560 do {                                                            \
 561    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 562    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 563    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 564    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 565    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 566 } while (0)
 567
 568 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 569
 570 #define VERT_SET_SPEC( v, c )                                   \
 571 do {                                                            \
 572    if (specoffset) {                                            \
 573       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 574       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 575       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 576       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 577    }                                                            \
 578 } while (0)
 579 #define VERT_COPY_SPEC( v0, v1 )                        \
 580 do {                                                    \
 581    if (specoffset) {                                    \
 582       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 583       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 584       spec0->red   = spec1->red;        \
 585       spec0->green = spec1->green;      \
 586       spec0->blue  = spec1->blue;       \
 587    }                                                    \
 588 } while (0)
 589
 590 /* These don't need LE32_TO_CPU() as they used to save and restore
 591  * colors which are already in the correct format.
 592  */
 593 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 594 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 595 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 596 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 597
 598 #undef LOCAL_VARS
 599 #undef TAG
 600 #undef INIT
 601
 602 #define LOCAL_VARS(n)                                                   \
 603    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 604    GLuint color[n] = {0}, spec[n] = {0};                                                \
 605    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 606    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 607    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 608
 609 /***********************************************************************
 610  *                Helpers for rendering unfilled primitives            *
 611  ***********************************************************************/
 612
 613 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 614 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 615 #undef TAG
 616 #define TAG(x) x
 617 #include "tnl_dd/t_dd_unfilled.h"
 618 #undef IND
 619
 620
 621 /***********************************************************************
 622  *                      Generate GL render functions                   *
 623  ***********************************************************************/
 624
 625
 626 #define IND (0)
 627 #define TAG(x) x
 628 #include "tnl_dd/t_dd_tritmp.h"
 629
 630 #define IND (RADEON_TWOSIDE_BIT)
 631 #define TAG(x) x##_twoside
 632 #include "tnl_dd/t_dd_tritmp.h"
 633
 634 #define IND (RADEON_UNFILLED_BIT)
 635 #define TAG(x) x##_unfilled
 636 #include "tnl_dd/t_dd_tritmp.h"
 637
 638 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 639 #define TAG(x) x##_twoside_unfilled
 640 #include "tnl_dd/t_dd_tritmp.h"
 641
 642
 643 static void init_rast_tab( void )
 644 {
 645    init();
 646    init_twoside();
 647    init_unfilled();
 648    init_twoside_unfilled();
 649 }
 650
 651 /**********************************************************************/
 652 /*               Render unclipped begin/end objects                   */
 653 /**********************************************************************/
 654
 655 #define RENDER_POINTS( start, count )           \
 656    for ( ; start < count ; start++)             \
 657       radeon_point( rmesa, VERT(start) )
 658 #define RENDER_LINE( v0, v1 ) \
 659    radeon_line( rmesa, VERT(v0), VERT(v1) )
 660 #define RENDER_TRI( v0, v1, v2 )  \
 661    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 662 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 663    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 664 #undef INIT
 665 #define INIT(x) do {                                    \
 666    radeonRenderPrimitive( ctx, x );                     \
 667 } while (0)
 668 #undef LOCAL_VARS
 669 #define LOCAL_VARS                                              \
 670    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 671    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 672    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 673    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 674    const GLboolean stipple = ctx->Line.StippleFlag;             \
 675    (void) elt; (void) stipple;
 676 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 677 #define RESET_OCCLUSION
 678 #define PRESERVE_VB_DEFS
 679 #define ELT(x) (x)
 680 #define TAG(x) radeon_##x##_verts
 681 #include "tnl/t_vb_rendertmp.h"
 682 #undef ELT
 683 #undef TAG
 684 #define TAG(x) radeon_##x##_elts
 685 #define ELT(x) elt[x]
 686 #include "tnl/t_vb_rendertmp.h"
 687
 688
 689
 690 /**********************************************************************/
 691 /*                    Choose render functions                         */
 692 /**********************************************************************/
 693
 694 void radeonChooseRenderState( struct gl_context *ctx )
 695 {
 696    TNLcontext *tnl = TNL_CONTEXT(ctx);
 697    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 698    GLuint index = 0;
 699    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 700                          ctx->Polygon.BackMode != GL_FILL);
 701    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 702
 703    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 704       return;
 705
 706    if (twosided)
 707       index |= RADEON_TWOSIDE_BIT;
 708    if (unfilled)
 709       index |= RADEON_UNFILLED_BIT;
 710
 711    if (index != rmesa->radeon.swtcl.RenderIndex) {
 712       tnl->Driver.Render.Points = rast_tab[index].points;
 713       tnl->Driver.Render.Line = rast_tab[index].line;
 714       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 715       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 716       tnl->Driver.Render.Quad = rast_tab[index].quad;
 717
 718       if (index == 0) {
 719          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 720          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 721          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 722       } else {
 723          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 724          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 725          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 726       }
 727
 728       rmesa->radeon.swtcl.RenderIndex = index;
 729    }
 730 }
 731
 732
 733 /**********************************************************************/
 734 /*                 High level hooks for t_vb_render.c                 */
 735 /**********************************************************************/
 736
 737
 738 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
 739 {
 740    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 741
 742    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 743       RADEON_NEWPRIM( rmesa );
 744       rmesa->radeon.swtcl.hw_primitive = hwprim;
 745    }
 746 }
 747
 748 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
 749 {
 750    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 751    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 752                          ctx->Polygon.BackMode != GL_FILL);
 753
 754    rmesa->radeon.swtcl.render_primitive = prim;
 755    if (prim < GL_TRIANGLES || !unfilled)
 756       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 757 }
 758
 759 static void radeonRenderFinish( struct gl_context *ctx )
 760 {
 761 }
 762
 763 static void radeonResetLineStipple( struct gl_context *ctx )
 764 {
 765    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 766    RADEON_STATECHANGE( rmesa, lin );
 767 }
 768
 769
 770 /**********************************************************************/
 771 /*           Transition to/from hardware rasterization.               */
 772 /**********************************************************************/
 773
 774 static const char * const fallbackStrings[] = {
 775    "Texture mode",
 776    "glDrawBuffer(GL_FRONT_AND_BACK)",
 777    "glEnable(GL_STENCIL) without hw stencil buffer",
 778    "glRenderMode(selection or feedback)",
 779    "glBlendEquation",
 780    "glBlendFunc",
 781    "RADEON_NO_RAST",
 782    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 783 };
 784
 785
 786 static const char *getFallbackString(GLuint bit)
 787 {
 788    int i = 0;
 789    while (bit > 1) {
 790       i++;
 791       bit >>= 1;
 792    }
 793    return fallbackStrings[i];
 794 }
 795
 796
 797 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
 798 {
 799    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 800    TNLcontext *tnl = TNL_CONTEXT(ctx);
 801    GLuint oldfallback = rmesa->radeon.Fallback;
 802
 803    if (mode) {
 804       rmesa->radeon.Fallback |= bit;
 805       if (oldfallback == 0) {
 806          radeon_firevertices(&rmesa->radeon);
 807          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 808          _swsetup_Wakeup( ctx );
 809          rmesa->radeon.swtcl.RenderIndex = ~0;
 810          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 811             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 812                     bit, getFallbackString(bit));
 813          }
 814       }
 815    }
 816    else {
 817       rmesa->radeon.Fallback &= ~bit;
 818       if (oldfallback == bit) {
 819          _swrast_flush( ctx );
 820          tnl->Driver.Render.Start = radeonRenderStart;
 821          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 822          tnl->Driver.Render.Finish = radeonRenderFinish;
 823
 824          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 825          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 826          tnl->Driver.Render.Interp = _tnl_interp;
 827
 828          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 829          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 830          if (rmesa->radeon.TclFallback) {
 831             /* These are already done if rmesa->radeon.TclFallback goes to
 832              * zero above. But not if it doesn't (RADEON_NO_TCL for
 833              * example?)
 834              */
 835             _tnl_invalidate_vertex_state( ctx, ~0 );
 836             _tnl_invalidate_vertices( ctx, ~0 );
 837             rmesa->radeon.tnl_index_bitset = 0;
 838             radeonChooseVertexState( ctx );
 839             radeonChooseRenderState( ctx );
 840          }
 841          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 842             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 843                     bit, getFallbackString(bit));
 844          }
 845       }
 846    }
 847 }
 848
 849
 850 /**********************************************************************/
 851 /*                            Initialization.                         */
 852 /**********************************************************************/
 853
 854 void radeonInitSwtcl( struct gl_context *ctx )
 855 {
 856    TNLcontext *tnl = TNL_CONTEXT(ctx);
 857    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 858    static int firsttime = 1;
 859
 860    if (firsttime) {
 861       init_rast_tab();
 862       firsttime = 0;
 863    }
 864    rmesa->radeon.swtcl.emit_prediction = 0;
 865
 866    tnl->Driver.Render.Start = radeonRenderStart;
 867    tnl->Driver.Render.Finish = radeonRenderFinish;
 868    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 869    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 870    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 871    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 872    tnl->Driver.Render.Interp = _tnl_interp;
 873
 874    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 875                        RADEON_MAX_TNL_VERTEX_SIZE);
 876
 877    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 878    rmesa->radeon.swtcl.RenderIndex = ~0;
 879    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 880    rmesa->radeon.swtcl.hw_primitive = 0;
 881 }
 882