1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/mtypes.h"
37 #include "main/colormac.h"
38 #include "main/enums.h"
39 #include "main/imports.h"
40 #include "main/macros.h"
42 #include "swrast_setup/swrast_setup.h"
43 #include "math/m_translate.h"
45 #include "tnl/t_context.h"
46 #include "tnl/t_pipeline.h"
48 #include "radeon_context.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_state.h"
51 #include "radeon_swtcl.h"
52 #include "radeon_tcl.h"
55 /* R100: xyzw, c0, c1/fog, stq[0..2] = 4+1+1+3*3 = 15 right? */
56 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
57 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat)) /* for mesa _tnl stage */
59 /***********************************************************************
61 ***********************************************************************/
63 #define EMIT_ATTR( ATTR, STYLE, F0 ) \
65 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR); \
66 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE); \
67 rmesa->radeon.swtcl.vertex_attr_count++; \
71 #define EMIT_PAD( N ) \
73 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0; \
74 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD; \
75 rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N); \
76 rmesa->radeon.swtcl.vertex_attr_count++; \
79 static GLuint radeon_cp_vc_frmts
[3][2] =
81 { RADEON_CP_VC_FRMT_ST0
, RADEON_CP_VC_FRMT_ST0
| RADEON_CP_VC_FRMT_Q0
},
82 { RADEON_CP_VC_FRMT_ST1
, RADEON_CP_VC_FRMT_ST1
| RADEON_CP_VC_FRMT_Q1
},
83 { RADEON_CP_VC_FRMT_ST2
, RADEON_CP_VC_FRMT_ST2
| RADEON_CP_VC_FRMT_Q2
},
86 static void radeonSetVertexFormat( GLcontext
*ctx
)
88 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
89 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
90 struct vertex_buffer
*VB
= &tnl
->vb
;
91 DECLARE_RENDERINPUTS(index_bitset
);
95 RENDERINPUTS_COPY( index_bitset
, tnl
->render_inputs_bitset
);
99 if ( VB
->NdcPtr
!= NULL
) {
100 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->NdcPtr
;
103 VB
->AttribPtr
[VERT_ATTRIB_POS
] = VB
->ClipPtr
;
106 assert( VB
->AttribPtr
[VERT_ATTRIB_POS
] != NULL
);
107 rmesa
->radeon
.swtcl
.vertex_attr_count
= 0;
109 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
110 * build up a hardware vertex.
112 if ( !rmesa
->swtcl
.needproj
||
113 RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) { /* for projtex */
114 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_4F
,
115 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
| RADEON_CP_VC_FRMT_W0
);
119 EMIT_ATTR( _TNL_ATTRIB_POS
, EMIT_3F
,
120 RADEON_CP_VC_FRMT_XY
| RADEON_CP_VC_FRMT_Z
);
124 rmesa
->swtcl
.coloroffset
= offset
;
125 #if MESA_LITTLE_ENDIAN
126 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_RGBA
,
127 RADEON_CP_VC_FRMT_PKCOLOR
);
129 EMIT_ATTR( _TNL_ATTRIB_COLOR0
, EMIT_4UB_4F_ABGR
,
130 RADEON_CP_VC_FRMT_PKCOLOR
);
134 rmesa
->swtcl
.specoffset
= 0;
135 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
) ||
136 RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
138 #if MESA_LITTLE_ENDIAN
139 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
140 rmesa
->swtcl
.specoffset
= offset
;
141 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_RGB
,
142 RADEON_CP_VC_FRMT_PKSPEC
);
148 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
149 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
150 RADEON_CP_VC_FRMT_PKSPEC
);
156 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_FOG
)) {
157 EMIT_ATTR( _TNL_ATTRIB_FOG
, EMIT_1UB_1F
,
158 RADEON_CP_VC_FRMT_PKSPEC
);
164 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_COLOR1
)) {
165 rmesa
->swtcl
.specoffset
= offset
;
166 EMIT_ATTR( _TNL_ATTRIB_COLOR1
, EMIT_3UB_3F_BGR
,
167 RADEON_CP_VC_FRMT_PKSPEC
);
175 if (RENDERINPUTS_TEST_RANGE( index_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
)) {
178 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
179 if (RENDERINPUTS_TEST( index_bitset
, _TNL_ATTRIB_TEX(i
) )) {
180 GLuint sz
= VB
->TexCoordPtr
[i
]->size
;
185 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_2F
,
186 radeon_cp_vc_frmts
[i
][0] );
190 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
& (TEXTURE_CUBE_BIT
) ) {
191 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F
,
192 radeon_cp_vc_frmts
[i
][1] );
194 EMIT_ATTR( _TNL_ATTRIB_TEX0
+i
, EMIT_3F_XYW
,
195 radeon_cp_vc_frmts
[i
][1] );
205 if (!RENDERINPUTS_EQUAL( rmesa
->radeon
.tnl_index_bitset
, index_bitset
) ||
206 fmt_0
!= rmesa
->swtcl
.vertex_format
) {
207 RADEON_NEWPRIM(rmesa
);
208 rmesa
->swtcl
.vertex_format
= fmt_0
;
209 rmesa
->radeon
.swtcl
.vertex_size
=
210 _tnl_install_attrs( ctx
,
211 rmesa
->radeon
.swtcl
.vertex_attrs
,
212 rmesa
->radeon
.swtcl
.vertex_attr_count
,
214 rmesa
->radeon
.swtcl
.vertex_size
/= 4;
215 RENDERINPUTS_COPY( rmesa
->radeon
.tnl_index_bitset
, index_bitset
);
216 if (RADEON_DEBUG
& DEBUG_VERTS
)
217 fprintf( stderr
, "%s: vertex_size= %d floats\n",
218 __FUNCTION__
, rmesa
->radeon
.swtcl
.vertex_size
);
223 static void radeonRenderStart( GLcontext
*ctx
)
225 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
227 radeonSetVertexFormat( ctx
);
229 if (rmesa
->radeon
.dma
.flush
!= 0 &&
230 rmesa
->radeon
.dma
.flush
!= rcommon_flush_last_swtcl_prim
)
231 rmesa
->radeon
.dma
.flush( ctx
);
236 * Set vertex state for SW TCL. The primary purpose of this function is to
237 * determine in advance whether or not the hardware can / should do the
238 * projection divide or Mesa should do it.
240 void radeonChooseVertexState( GLcontext
*ctx
)
242 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
243 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
245 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
247 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
248 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
249 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
251 /* We must ensure that we don't do _tnl_need_projected_coords while in a
252 * rasterization fallback. As this function will be called again when we
253 * leave a rasterization fallback, we can just skip it for now.
255 if (rmesa
->radeon
.Fallback
!= 0)
258 /* HW perspective divide is a win, but tiny vertex formats are a
262 if ((!RENDERINPUTS_TEST_RANGE( tnl
->render_inputs_bitset
, _TNL_FIRST_TEX
, _TNL_LAST_TEX
) &&
263 !RENDERINPUTS_TEST( tnl
->render_inputs_bitset
, _TNL_ATTRIB_COLOR1
))
264 || (ctx
->_TriangleCaps
& (DD_TRI_LIGHT_TWOSIDE
|DD_TRI_UNFILLED
))) {
265 rmesa
->swtcl
.needproj
= GL_TRUE
;
266 se_coord_fmt
|= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
267 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
);
270 rmesa
->swtcl
.needproj
= GL_FALSE
;
271 se_coord_fmt
|= (RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
274 _tnl_need_projected_coords( ctx
, rmesa
->swtcl
.needproj
);
276 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
277 RADEON_STATECHANGE( rmesa
, set
);
278 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
282 void r100_swtcl_flush(GLcontext
*ctx
, uint32_t current_offset
)
284 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
286 rcommonEnsureCmdBufSpace(&rmesa
->radeon
,
287 rmesa
->radeon
.hw
.max_state_size
+ (12*sizeof(int)),
291 radeonEmitState(&rmesa
->radeon
);
292 radeonEmitVertexAOS( rmesa
,
293 rmesa
->radeon
.swtcl
.vertex_size
,
294 rmesa
->radeon
.dma
.current
,
298 radeonEmitVbufPrim( rmesa
,
299 rmesa
->swtcl
.vertex_format
,
300 rmesa
->radeon
.swtcl
.hw_primitive
,
301 rmesa
->radeon
.swtcl
.numverts
);
306 * Render unclipped vertex buffers by emitting vertices directly to
307 * dma buffers. Use strip/fan hardware primitives where possible.
308 * Try to simulate missing primitives with indexed vertices.
310 #define HAVE_POINTS 1
312 #define HAVE_LINE_STRIPS 1
313 #define HAVE_TRIANGLES 1
314 #define HAVE_TRI_STRIPS 1
315 #define HAVE_TRI_STRIP_1 0
316 #define HAVE_TRI_FANS 1
318 #define HAVE_QUAD_STRIPS 0
319 #define HAVE_POLYGONS 0
320 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
323 static const GLuint hw_prim
[GL_POLYGON
+1] = {
324 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
325 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
327 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
,
328 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
329 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
,
330 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
,
337 radeonDmaPrimitive( r100ContextPtr rmesa
, GLenum prim
)
339 RADEON_NEWPRIM( rmesa
);
340 rmesa
->radeon
.swtcl
.hw_primitive
= hw_prim
[prim
];
341 // assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
344 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
345 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
346 #define FLUSH() RADEON_NEWPRIM( rmesa )
347 #define GET_CURRENT_VB_MAX_VERTS() 10\
348 // (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
349 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
350 ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
351 #define ALLOC_VERTS( nr ) \
352 rcommonAllocDmaLowVerts( &rmesa->radeon, nr, rmesa->radeon.swtcl.vertex_size * 4 )
353 #define EMIT_VERTS( ctx, j, nr, buf ) \
354 _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
356 #define TAG(x) radeon_dma_##x
357 #include "tnl_dd/t_dd_dmatmp.h"
360 /**********************************************************************/
361 /* Render pipeline stage */
362 /**********************************************************************/
365 static GLboolean
radeon_run_render( GLcontext
*ctx
,
366 struct tnl_pipeline_stage
*stage
)
368 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
369 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
370 struct vertex_buffer
*VB
= &tnl
->vb
;
371 tnl_render_func
*tab
= TAG(render_tab_verts
);
374 if (rmesa
->radeon
.swtcl
.RenderIndex
!= 0 ||
375 !radeon_dma_validate_render( ctx
, VB
))
378 tnl
->Driver
.Render
.Start( ctx
);
380 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
382 GLuint prim
= VB
->Primitive
[i
].mode
;
383 GLuint start
= VB
->Primitive
[i
].start
;
384 GLuint length
= VB
->Primitive
[i
].count
;
389 if (RADEON_DEBUG
& DEBUG_PRIMS
)
390 fprintf(stderr
, "radeon_render.c: prim %s %d..%d\n",
391 _mesa_lookup_enum_by_nr(prim
& PRIM_MODE_MASK
),
392 start
, start
+length
);
395 tab
[prim
& PRIM_MODE_MASK
]( ctx
, start
, start
+ length
, prim
);
398 tnl
->Driver
.Render
.Finish( ctx
);
400 return GL_FALSE
; /* finished the pipe */
405 const struct tnl_pipeline_stage _radeon_render_stage
=
412 radeon_run_render
/* run */
416 /**************************************************************************/
419 static const GLuint reduced_hw_prim
[GL_POLYGON
+1] = {
420 RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
,
421 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
422 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
423 RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
,
424 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
425 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
426 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
427 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
428 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
,
429 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
432 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
);
433 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
);
434 static void radeonResetLineStipple( GLcontext
*ctx
);
437 /***********************************************************************
438 * Emit primitives as inline vertices *
439 ***********************************************************************/
443 #define CTX_ARG r100ContextPtr rmesa
444 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
445 #define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, (size) * 4 )
448 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
449 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
450 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
451 #define VERTEX radeonVertex
453 #define TAG(x) radeon_##x
454 #include "tnl_dd/t_dd_triemit.h"
457 /***********************************************************************
458 * Macros for t_dd_tritmp.h to draw basic primitives *
459 ***********************************************************************/
461 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
462 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
463 #define LINE( a, b ) radeon_line( rmesa, a, b )
464 #define POINT( a ) radeon_point( rmesa, a )
466 /***********************************************************************
467 * Build render functions from dd templates *
468 ***********************************************************************/
470 #define RADEON_TWOSIDE_BIT 0x01
471 #define RADEON_UNFILLED_BIT 0x02
472 #define RADEON_MAX_TRIFUNC 0x04
476 tnl_points_func points
;
478 tnl_triangle_func triangle
;
480 } rast_tab
[RADEON_MAX_TRIFUNC
];
483 #define DO_FALLBACK 0
485 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
486 #define DO_TWOSIDE (IND & RADEON_TWOSIDE_BIT)
492 #define DO_FULL_QUAD 1
496 #define HAVE_BACK_COLORS 0
497 #define HAVE_HW_FLATSHADE 1
500 #define DEPTH_SCALE 1.0
501 #define UNFILLED_TRI unfilled_tri
502 #define UNFILLED_QUAD unfilled_quad
503 #define VERT_X(_v) _v->v.x
504 #define VERT_Y(_v) _v->v.y
505 #define VERT_Z(_v) _v->v.z
506 #define AREA_IS_CCW( a ) (a < 0)
507 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
509 #define VERT_SET_RGBA( v, c ) \
511 radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]); \
512 UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]); \
513 UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]); \
514 UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]); \
515 UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]); \
518 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
520 #define VERT_SET_SPEC( v, c ) \
523 radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]); \
524 UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]); \
525 UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]); \
526 UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]); \
529 #define VERT_COPY_SPEC( v0, v1 ) \
532 radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]); \
533 radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]); \
534 spec0->red = spec1->red; \
535 spec0->green = spec1->green; \
536 spec0->blue = spec1->blue; \
540 /* These don't need LE32_TO_CPU() as they used to save and restore
541 * colors which are already in the correct format.
543 #define VERT_SAVE_RGBA( idx ) color[idx] = v[idx]->ui[coloroffset]
544 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
545 #define VERT_SAVE_SPEC( idx ) if (specoffset) spec[idx] = v[idx]->ui[specoffset]
546 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
552 #define LOCAL_VARS(n) \
553 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
554 GLuint color[n], spec[n]; \
555 GLuint coloroffset = rmesa->swtcl.coloroffset; \
556 GLuint specoffset = rmesa->swtcl.specoffset; \
557 (void) color; (void) spec; (void) coloroffset; (void) specoffset;
559 /***********************************************************************
560 * Helpers for rendering unfilled primitives *
561 ***********************************************************************/
563 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
564 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
567 #include "tnl_dd/t_dd_unfilled.h"
571 /***********************************************************************
572 * Generate GL render functions *
573 ***********************************************************************/
578 #include "tnl_dd/t_dd_tritmp.h"
580 #define IND (RADEON_TWOSIDE_BIT)
581 #define TAG(x) x##_twoside
582 #include "tnl_dd/t_dd_tritmp.h"
584 #define IND (RADEON_UNFILLED_BIT)
585 #define TAG(x) x##_unfilled
586 #include "tnl_dd/t_dd_tritmp.h"
588 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
589 #define TAG(x) x##_twoside_unfilled
590 #include "tnl_dd/t_dd_tritmp.h"
593 static void init_rast_tab( void )
598 init_twoside_unfilled();
601 /**********************************************************************/
602 /* Render unclipped begin/end objects */
603 /**********************************************************************/
605 #define RENDER_POINTS( start, count ) \
606 for ( ; start < count ; start++) \
607 radeon_point( rmesa, VERT(start) )
608 #define RENDER_LINE( v0, v1 ) \
609 radeon_line( rmesa, VERT(v0), VERT(v1) )
610 #define RENDER_TRI( v0, v1, v2 ) \
611 radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
612 #define RENDER_QUAD( v0, v1, v2, v3 ) \
613 radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
615 #define INIT(x) do { \
616 radeonRenderPrimitive( ctx, x ); \
620 r100ContextPtr rmesa = R100_CONTEXT(ctx); \
621 const GLuint vertsize = rmesa->radeon.swtcl.vertex_size; \
622 const char *radeonverts = (char *)rmesa->radeon.swtcl.verts; \
623 const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts; \
624 const GLboolean stipple = ctx->Line.StippleFlag; \
625 (void) elt; (void) stipple;
626 #define RESET_STIPPLE if ( stipple ) radeonResetLineStipple( ctx );
627 #define RESET_OCCLUSION
628 #define PRESERVE_VB_DEFS
630 #define TAG(x) radeon_##x##_verts
631 #include "tnl/t_vb_rendertmp.h"
634 #define TAG(x) radeon_##x##_elts
635 #define ELT(x) elt[x]
636 #include "tnl/t_vb_rendertmp.h"
640 /**********************************************************************/
641 /* Choose render functions */
642 /**********************************************************************/
644 void radeonChooseRenderState( GLcontext
*ctx
)
646 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
647 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
649 GLuint flags
= ctx
->_TriangleCaps
;
651 if (!rmesa
->radeon
.TclFallback
|| rmesa
->radeon
.Fallback
)
654 if (flags
& DD_TRI_LIGHT_TWOSIDE
) index
|= RADEON_TWOSIDE_BIT
;
655 if (flags
& DD_TRI_UNFILLED
) index
|= RADEON_UNFILLED_BIT
;
657 if (index
!= rmesa
->radeon
.swtcl
.RenderIndex
) {
658 tnl
->Driver
.Render
.Points
= rast_tab
[index
].points
;
659 tnl
->Driver
.Render
.Line
= rast_tab
[index
].line
;
660 tnl
->Driver
.Render
.ClippedLine
= rast_tab
[index
].line
;
661 tnl
->Driver
.Render
.Triangle
= rast_tab
[index
].triangle
;
662 tnl
->Driver
.Render
.Quad
= rast_tab
[index
].quad
;
665 tnl
->Driver
.Render
.PrimTabVerts
= radeon_render_tab_verts
;
666 tnl
->Driver
.Render
.PrimTabElts
= radeon_render_tab_elts
;
667 tnl
->Driver
.Render
.ClippedPolygon
= radeon_fast_clipped_poly
;
669 tnl
->Driver
.Render
.PrimTabVerts
= _tnl_render_tab_verts
;
670 tnl
->Driver
.Render
.PrimTabElts
= _tnl_render_tab_elts
;
671 tnl
->Driver
.Render
.ClippedPolygon
= _tnl_RenderClippedPolygon
;
674 rmesa
->radeon
.swtcl
.RenderIndex
= index
;
679 /**********************************************************************/
680 /* High level hooks for t_vb_render.c */
681 /**********************************************************************/
684 static void radeonRasterPrimitive( GLcontext
*ctx
, GLuint hwprim
)
686 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
688 if (rmesa
->radeon
.swtcl
.hw_primitive
!= hwprim
) {
689 RADEON_NEWPRIM( rmesa
);
690 rmesa
->radeon
.swtcl
.hw_primitive
= hwprim
;
694 static void radeonRenderPrimitive( GLcontext
*ctx
, GLenum prim
)
696 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
697 rmesa
->radeon
.swtcl
.render_primitive
= prim
;
698 if (prim
< GL_TRIANGLES
|| !(ctx
->_TriangleCaps
& DD_TRI_UNFILLED
))
699 radeonRasterPrimitive( ctx
, reduced_hw_prim
[prim
] );
702 static void radeonRenderFinish( GLcontext
*ctx
)
706 static void radeonResetLineStipple( GLcontext
*ctx
)
708 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
709 RADEON_STATECHANGE( rmesa
, lin
);
713 /**********************************************************************/
714 /* Transition to/from hardware rasterization. */
715 /**********************************************************************/
717 static const char * const fallbackStrings
[] = {
719 "glDrawBuffer(GL_FRONT_AND_BACK)",
720 "glEnable(GL_STENCIL) without hw stencil buffer",
721 "glRenderMode(selection or feedback)",
725 "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
729 static const char *getFallbackString(GLuint bit
)
736 return fallbackStrings
[i
];
740 void radeonFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
742 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
743 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
744 GLuint oldfallback
= rmesa
->radeon
.Fallback
;
747 rmesa
->radeon
.Fallback
|= bit
;
748 if (oldfallback
== 0) {
749 radeon_firevertices(&rmesa
->radeon
);
750 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_TRUE
);
751 _swsetup_Wakeup( ctx
);
752 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
753 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
754 fprintf(stderr
, "Radeon begin rasterization fallback: 0x%x %s\n",
755 bit
, getFallbackString(bit
));
760 rmesa
->radeon
.Fallback
&= ~bit
;
761 if (oldfallback
== bit
) {
762 _swrast_flush( ctx
);
763 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
764 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
765 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
767 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
768 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
769 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
771 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
772 TCL_FALLBACK( ctx
, RADEON_TCL_FALLBACK_RASTER
, GL_FALSE
);
773 if (rmesa
->radeon
.TclFallback
) {
774 /* These are already done if rmesa->radeon.TclFallback goes to
775 * zero above. But not if it doesn't (RADEON_NO_TCL for
778 _tnl_invalidate_vertex_state( ctx
, ~0 );
779 _tnl_invalidate_vertices( ctx
, ~0 );
780 RENDERINPUTS_ZERO( rmesa
->radeon
.tnl_index_bitset
);
781 radeonChooseVertexState( ctx
);
782 radeonChooseRenderState( ctx
);
784 if (RADEON_DEBUG
& DEBUG_FALLBACKS
) {
785 fprintf(stderr
, "Radeon end rasterization fallback: 0x%x %s\n",
786 bit
, getFallbackString(bit
));
793 /**********************************************************************/
794 /* Initialization. */
795 /**********************************************************************/
797 void radeonInitSwtcl( GLcontext
*ctx
)
799 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
800 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
801 static int firsttime
= 1;
808 tnl
->Driver
.Render
.Start
= radeonRenderStart
;
809 tnl
->Driver
.Render
.Finish
= radeonRenderFinish
;
810 tnl
->Driver
.Render
.PrimitiveNotify
= radeonRenderPrimitive
;
811 tnl
->Driver
.Render
.ResetLineStipple
= radeonResetLineStipple
;
812 tnl
->Driver
.Render
.BuildVertices
= _tnl_build_vertices
;
813 tnl
->Driver
.Render
.CopyPV
= _tnl_copy_pv
;
814 tnl
->Driver
.Render
.Interp
= _tnl_interp
;
816 _tnl_init_vertices( ctx
, ctx
->Const
.MaxArrayLockSize
+ 12,
817 RADEON_MAX_TNL_VERTEX_SIZE
);
819 rmesa
->radeon
.swtcl
.verts
= (GLubyte
*)tnl
->clipspace
.vertex_buf
;
820 rmesa
->radeon
.swtcl
.RenderIndex
= ~0;
821 rmesa
->radeon
.swtcl
.render_primitive
= GL_TRIANGLES
;
822 rmesa
->radeon
.swtcl
.hw_primitive
= 0;