src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/colormac.h"
  38 #include "main/enums.h"
  39 #include "main/imports.h"
  40 #include "main/macros.h"
  41 #include "main/simple_list.h"
  42
  43 #include "swrast_setup/swrast_setup.h"
  44 #include "math/m_translate.h"
  45 #include "tnl/tnl.h"
  46 #include "tnl/t_context.h"
  47 #include "tnl/t_pipeline.h"
  48
  49 #include "radeon_context.h"
  50 #include "radeon_ioctl.h"
  51 #include "radeon_state.h"
  52 #include "radeon_swtcl.h"
  53 #include "radeon_tcl.h"
  54
  55
  56 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  57 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  58 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  59
  60 /***********************************************************************
  61  *                         Initialization
  62  ***********************************************************************/
  63
  64 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  65 do {                                                                    \
  66    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  67    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  68    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  69    fmt_0 |= F0;                                                         \
  70 } while (0)
  71
  72 #define EMIT_PAD( N )                                                   \
  73 do {                                                                    \
  74    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  75    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  76    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  77    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  78 } while (0)
  79
  80 static GLuint radeon_cp_vc_frmts[3][2] =
  81 {
  82    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  83    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  84    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  85 };
  86
  87 static void radeonSetVertexFormat( GLcontext *ctx )
  88 {
  89    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  90    TNLcontext *tnl = TNL_CONTEXT(ctx);
  91    struct vertex_buffer *VB = &tnl->vb;
  92    DECLARE_RENDERINPUTS(index_bitset);
  93    int fmt_0 = 0;
  94    int offset = 0;
  95
  96    RENDERINPUTS_COPY( index_bitset, tnl->render_inputs_bitset );
  97
  98    /* Important:
  99     */
 100    if ( VB->NdcPtr != NULL ) {
 101       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 102    }
 103    else {
 104       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 105    }
 106
 107    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 108    rmesa->radeon.swtcl.vertex_attr_count = 0;
 109
 110    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 111     * build up a hardware vertex.
 112     */
 113    if ( !rmesa->swtcl.needproj ||
 114         RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {       /* for projtex */
 115       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 116                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 117       offset = 4;
 118    }
 119    else {
 120       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 121                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 122       offset = 3;
 123    }
 124
 125    rmesa->swtcl.coloroffset = offset;
 126 #if MESA_LITTLE_ENDIAN
 127    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 128               RADEON_CP_VC_FRMT_PKCOLOR );
 129 #else
 130    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 131               RADEON_CP_VC_FRMT_PKCOLOR );
 132 #endif
 133    offset += 1;
 134
 135    rmesa->swtcl.specoffset = 0;
 136    if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 ) ||
 137        RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 138
 139 #if MESA_LITTLE_ENDIAN
 140       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 141          rmesa->swtcl.specoffset = offset;
 142          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 143                     RADEON_CP_VC_FRMT_PKSPEC );
 144       }
 145       else {
 146          EMIT_PAD( 3 );
 147       }
 148
 149       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 150          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 151                     RADEON_CP_VC_FRMT_PKSPEC );
 152       }
 153       else {
 154          EMIT_PAD( 1 );
 155       }
 156 #else
 157       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_FOG )) {
 158          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 159                     RADEON_CP_VC_FRMT_PKSPEC );
 160       }
 161       else {
 162          EMIT_PAD( 1 );
 163       }
 164
 165       if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_COLOR1 )) {
 166          rmesa->swtcl.specoffset = offset;
 167          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 168                     RADEON_CP_VC_FRMT_PKSPEC );
 169       }
 170       else {
 171          EMIT_PAD( 3 );
 172       }
 173 #endif
 174    }
 175
 176    if (RENDERINPUTS_TEST_RANGE( index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX )) {
 177       int i;
 178
 179       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 180          if (RENDERINPUTS_TEST( index_bitset, _TNL_ATTRIB_TEX(i) )) {
 181             GLuint sz = VB->TexCoordPtr[i]->size;
 182
 183             switch (sz) {
 184             case 1:
 185             case 2:
 186                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 187                           radeon_cp_vc_frmts[i][0] );
 188                break;
 189             case 3:
 190             case 4:
 191                if (ctx->Texture.Unit[i]._ReallyEnabled & (TEXTURE_CUBE_BIT) ) {
 192                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 193                              radeon_cp_vc_frmts[i][1] );
 194                } else {
 195                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 196                              radeon_cp_vc_frmts[i][1] );
 197                }
 198                break;
 199             default:
 200                continue;
 201             };
 202          }
 203       }
 204    }
 205
 206    if (!RENDERINPUTS_EQUAL( rmesa->radeon.tnl_index_bitset, index_bitset ) ||
 207         fmt_0 != rmesa->swtcl.vertex_format) {
 208       RADEON_NEWPRIM(rmesa);
 209       rmesa->swtcl.vertex_format = fmt_0;
 210       rmesa->radeon.swtcl.vertex_size =
 211           _tnl_install_attrs( ctx,
 212                               rmesa->radeon.swtcl.vertex_attrs,
 213                               rmesa->radeon.swtcl.vertex_attr_count,
 214                               NULL, 0 );
 215       rmesa->radeon.swtcl.vertex_size /= 4;
 216       RENDERINPUTS_COPY( rmesa->radeon.tnl_index_bitset, index_bitset );
 217       if (RADEON_DEBUG & DEBUG_VERTS)
 218          fprintf( stderr, "%s: vertex_size= %d floats\n",
 219                   __FUNCTION__, rmesa->radeon.swtcl.vertex_size);
 220    }
 221 }
 222
 223
 224 static void radeonRenderStart( GLcontext *ctx )
 225 {
 226    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 227
 228    radeonSetVertexFormat( ctx );
 229
 230    if (rmesa->radeon.dma.flush != 0 &&
 231        rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 232       rmesa->radeon.dma.flush( ctx );
 233 }
 234
 235
 236 /**
 237  * Set vertex state for SW TCL.  The primary purpose of this function is to
 238  * determine in advance whether or not the hardware can / should do the
 239  * projection divide or Mesa should do it.
 240  */
 241 void radeonChooseVertexState( GLcontext *ctx )
 242 {
 243    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 244    TNLcontext *tnl = TNL_CONTEXT(ctx);
 245
 246    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 247
 248    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 249                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 250                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 251
 252    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 253     * rasterization fallback.  As this function will be called again when we
 254     * leave a rasterization fallback, we can just skip it for now.
 255     */
 256    if (rmesa->radeon.Fallback != 0)
 257       return;
 258
 259    /* HW perspective divide is a win, but tiny vertex formats are a
 260     * bigger one.
 261     */
 262
 263    if ((!RENDERINPUTS_TEST_RANGE( tnl->render_inputs_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX ) &&
 264        !RENDERINPUTS_TEST( tnl->render_inputs_bitset, _TNL_ATTRIB_COLOR1 ))
 265        || (ctx->_TriangleCaps & (DD_TRI_LIGHT_TWOSIDE|DD_TRI_UNFILLED))) {
 266       rmesa->swtcl.needproj = GL_TRUE;
 267       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 268                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 269    }
 270    else {
 271       rmesa->swtcl.needproj = GL_FALSE;
 272       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 273    }
 274
 275    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 276
 277    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 278       RADEON_STATECHANGE( rmesa, set );
 279       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 280    }
 281 }
 282
 283 void r100_swtcl_flush(GLcontext *ctx, uint32_t current_offset)
 284 {
 285    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 286
 287    rcommonEnsureCmdBufSpace(&rmesa->radeon,
 288                             radeonCountEmitSize( &rmesa->radeon ) + (12*sizeof(int)),
 289                             __FUNCTION__);
 290
 291
 292    radeonEmitState(&rmesa->radeon);
 293    radeonEmitVertexAOS( rmesa,
 294                         rmesa->radeon.swtcl.vertex_size,
 295                         first_elem(&rmesa->radeon.dma.reserved)->bo,
 296                         current_offset);
 297
 298
 299    radeonEmitVbufPrim( rmesa,
 300                        rmesa->swtcl.vertex_format,
 301                        rmesa->radeon.swtcl.hw_primitive,
 302                        rmesa->radeon.swtcl.numverts);
 303
 304 }
 305
 306 /*
 307  * Render unclipped vertex buffers by emitting vertices directly to
 308  * dma buffers.  Use strip/fan hardware primitives where possible.
 309  * Try to simulate missing primitives with indexed vertices.
 310  */
 311 #define HAVE_POINTS      1
 312 #define HAVE_LINES       1
 313 #define HAVE_LINE_STRIPS 1
 314 #define HAVE_TRIANGLES   1
 315 #define HAVE_TRI_STRIPS  1
 316 #define HAVE_TRI_STRIP_1 0
 317 #define HAVE_TRI_FANS    1
 318 #define HAVE_QUADS       0
 319 #define HAVE_QUAD_STRIPS 0
 320 #define HAVE_POLYGONS    0
 321 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 322 #define HAVE_ELTS        0
 323
 324 static const GLuint hw_prim[GL_POLYGON+1] = {
 325    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 326    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 327    0,
 328    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 329    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 330    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 331    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 332    0,
 333    0,
 334    0
 335 };
 336
 337 static INLINE void
 338 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 339 {
 340    RADEON_NEWPRIM( rmesa );
 341    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 342    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 343 }
 344
 345 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 346 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 347 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 348 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 349 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 350 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 351   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 352 #define ALLOC_VERTS( nr ) \
 353   rcommonAllocDmaLowVerts( &rmesa->radeon, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 354 #define EMIT_VERTS( ctx, j, nr, buf ) \
 355   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 356
 357 #define TAG(x) radeon_dma_##x
 358 #include "tnl_dd/t_dd_dmatmp.h"
 359
 360
 361 /**********************************************************************/
 362 /*                          Render pipeline stage                     */
 363 /**********************************************************************/
 364
 365
 366 static GLboolean radeon_run_render( GLcontext *ctx,
 367                                     struct tnl_pipeline_stage *stage )
 368 {
 369    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 370    TNLcontext *tnl = TNL_CONTEXT(ctx);
 371    struct vertex_buffer *VB = &tnl->vb;
 372    tnl_render_func *tab = TAG(render_tab_verts);
 373    GLuint i;
 374
 375    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 376        !radeon_dma_validate_render( ctx, VB ))
 377       return GL_TRUE;
 378
 379    tnl->Driver.Render.Start( ctx );
 380
 381    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 382    {
 383       GLuint prim = VB->Primitive[i].mode;
 384       GLuint start = VB->Primitive[i].start;
 385       GLuint length = VB->Primitive[i].count;
 386
 387       if (!length)
 388          continue;
 389
 390       if (RADEON_DEBUG & DEBUG_PRIMS)
 391          fprintf(stderr, "radeon_render.c: prim %s %d..%d\n",
 392                  _mesa_lookup_enum_by_nr(prim & PRIM_MODE_MASK),
 393                  start, start+length);
 394
 395       if (length)
 396          tab[prim & PRIM_MODE_MASK]( ctx, start, start + length, prim );
 397    }
 398
 399    tnl->Driver.Render.Finish( ctx );
 400
 401    return GL_FALSE;             /* finished the pipe */
 402 }
 403
 404
 405
 406 const struct tnl_pipeline_stage _radeon_render_stage =
 407 {
 408    "radeon render",
 409    NULL,
 410    NULL,
 411    NULL,
 412    NULL,
 413    radeon_run_render            /* run */
 414 };
 415
 416
 417 /**************************************************************************/
 418
 419
 420 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 421    RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 422    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 423    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 424    RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 425    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 426    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 427    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 428    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 429    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 430    RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 431 };
 432
 433 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim );
 434 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim );
 435 static void radeonResetLineStipple( GLcontext *ctx );
 436
 437
 438 /***********************************************************************
 439  *                    Emit primitives as inline vertices               *
 440  ***********************************************************************/
 441
 442 #undef LOCAL_VARS
 443 #undef ALLOC_VERTS
 444 #define CTX_ARG r100ContextPtr rmesa
 445 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 446 #define ALLOC_VERTS( n, size ) rcommonAllocDmaLowVerts( &rmesa->radeon, n, (size) * 4 )
 447 #undef LOCAL_VARS
 448 #define LOCAL_VARS                                              \
 449    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 450    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 451 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 452 #define VERTEX radeonVertex
 453 #undef TAG
 454 #define TAG(x) radeon_##x
 455 #include "tnl_dd/t_dd_triemit.h"
 456
 457
 458 /***********************************************************************
 459  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 460  ***********************************************************************/
 461
 462 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 463 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 464 #define LINE( a, b )       radeon_line( rmesa, a, b )
 465 #define POINT( a )         radeon_point( rmesa, a )
 466
 467 /***********************************************************************
 468  *              Build render functions from dd templates               *
 469  ***********************************************************************/
 470
 471 #define RADEON_TWOSIDE_BIT      0x01
 472 #define RADEON_UNFILLED_BIT     0x02
 473 #define RADEON_MAX_TRIFUNC      0x04
 474
 475
 476 static struct {
 477    tnl_points_func              points;
 478    tnl_line_func                line;
 479    tnl_triangle_func    triangle;
 480    tnl_quad_func                quad;
 481 } rast_tab[RADEON_MAX_TRIFUNC];
 482
 483
 484 #define DO_FALLBACK  0
 485 #define DO_OFFSET    0
 486 #define DO_UNFILLED (IND & RADEON_UNFILLED_BIT)
 487 #define DO_TWOSIDE  (IND & RADEON_TWOSIDE_BIT)
 488 #define DO_FLAT      0
 489 #define DO_TRI       1
 490 #define DO_QUAD      1
 491 #define DO_LINE      1
 492 #define DO_POINTS    1
 493 #define DO_FULL_QUAD 1
 494
 495 #define HAVE_RGBA   1
 496 #define HAVE_SPEC   1
 497 #define HAVE_BACK_COLORS  0
 498 #define HAVE_HW_FLATSHADE 1
 499 #define TAB rast_tab
 500
 501 #define DEPTH_SCALE 1.0
 502 #define UNFILLED_TRI unfilled_tri
 503 #define UNFILLED_QUAD unfilled_quad
 504 #define VERT_X(_v) _v->v.x
 505 #define VERT_Y(_v) _v->v.y
 506 #define VERT_Z(_v) _v->v.z
 507 #define AREA_IS_CCW( a ) (a < 0)
 508 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 509
 510 #define VERT_SET_RGBA( v, c )                                   \
 511 do {                                                            \
 512    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 513    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 514    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 515    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 516    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 517 } while (0)
 518
 519 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 520
 521 #define VERT_SET_SPEC( v, c )                                   \
 522 do {                                                            \
 523    if (specoffset) {                                            \
 524       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 525       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 526       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 527       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 528    }                                                            \
 529 } while (0)
 530 #define VERT_COPY_SPEC( v0, v1 )                        \
 531 do {                                                    \
 532    if (specoffset) {                                    \
 533       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 534       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 535       spec0->red   = spec1->red;        \
 536       spec0->green = spec1->green;      \
 537       spec0->blue  = spec1->blue;       \
 538    }                                                    \
 539 } while (0)
 540
 541 /* These don't need LE32_TO_CPU() as they used to save and restore
 542  * colors which are already in the correct format.
 543  */
 544 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 545 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 546 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 547 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 548
 549 #undef LOCAL_VARS
 550 #undef TAG
 551 #undef INIT
 552
 553 #define LOCAL_VARS(n)                                                   \
 554    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 555    GLuint color[n], spec[n];                                            \
 556    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 557    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 558    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 559
 560 /***********************************************************************
 561  *                Helpers for rendering unfilled primitives            *
 562  ***********************************************************************/
 563
 564 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 565 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 566 #undef TAG
 567 #define TAG(x) x
 568 #include "tnl_dd/t_dd_unfilled.h"
 569 #undef IND
 570
 571
 572 /***********************************************************************
 573  *                      Generate GL render functions                   *
 574  ***********************************************************************/
 575
 576
 577 #define IND (0)
 578 #define TAG(x) x
 579 #include "tnl_dd/t_dd_tritmp.h"
 580
 581 #define IND (RADEON_TWOSIDE_BIT)
 582 #define TAG(x) x##_twoside
 583 #include "tnl_dd/t_dd_tritmp.h"
 584
 585 #define IND (RADEON_UNFILLED_BIT)
 586 #define TAG(x) x##_unfilled
 587 #include "tnl_dd/t_dd_tritmp.h"
 588
 589 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 590 #define TAG(x) x##_twoside_unfilled
 591 #include "tnl_dd/t_dd_tritmp.h"
 592
 593
 594 static void init_rast_tab( void )
 595 {
 596    init();
 597    init_twoside();
 598    init_unfilled();
 599    init_twoside_unfilled();
 600 }
 601
 602 /**********************************************************************/
 603 /*               Render unclipped begin/end objects                   */
 604 /**********************************************************************/
 605
 606 #define RENDER_POINTS( start, count )           \
 607    for ( ; start < count ; start++)             \
 608       radeon_point( rmesa, VERT(start) )
 609 #define RENDER_LINE( v0, v1 ) \
 610    radeon_line( rmesa, VERT(v0), VERT(v1) )
 611 #define RENDER_TRI( v0, v1, v2 )  \
 612    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 613 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 614    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 615 #undef INIT
 616 #define INIT(x) do {                                    \
 617    radeonRenderPrimitive( ctx, x );                     \
 618 } while (0)
 619 #undef LOCAL_VARS
 620 #define LOCAL_VARS                                              \
 621    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 622    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 623    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 624    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 625    const GLboolean stipple = ctx->Line.StippleFlag;             \
 626    (void) elt; (void) stipple;
 627 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 628 #define RESET_OCCLUSION
 629 #define PRESERVE_VB_DEFS
 630 #define ELT(x) (x)
 631 #define TAG(x) radeon_##x##_verts
 632 #include "tnl/t_vb_rendertmp.h"
 633 #undef ELT
 634 #undef TAG
 635 #define TAG(x) radeon_##x##_elts
 636 #define ELT(x) elt[x]
 637 #include "tnl/t_vb_rendertmp.h"
 638
 639
 640
 641 /**********************************************************************/
 642 /*                    Choose render functions                         */
 643 /**********************************************************************/
 644
 645 void radeonChooseRenderState( GLcontext *ctx )
 646 {
 647    TNLcontext *tnl = TNL_CONTEXT(ctx);
 648    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 649    GLuint index = 0;
 650    GLuint flags = ctx->_TriangleCaps;
 651
 652    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 653       return;
 654
 655    if (flags & DD_TRI_LIGHT_TWOSIDE) index |= RADEON_TWOSIDE_BIT;
 656    if (flags & DD_TRI_UNFILLED)      index |= RADEON_UNFILLED_BIT;
 657
 658    if (index != rmesa->radeon.swtcl.RenderIndex) {
 659       tnl->Driver.Render.Points = rast_tab[index].points;
 660       tnl->Driver.Render.Line = rast_tab[index].line;
 661       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 662       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 663       tnl->Driver.Render.Quad = rast_tab[index].quad;
 664
 665       if (index == 0) {
 666          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 667          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 668          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 669       } else {
 670          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 671          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 672          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 673       }
 674
 675       rmesa->radeon.swtcl.RenderIndex = index;
 676    }
 677 }
 678
 679
 680 /**********************************************************************/
 681 /*                 High level hooks for t_vb_render.c                 */
 682 /**********************************************************************/
 683
 684
 685 static void radeonRasterPrimitive( GLcontext *ctx, GLuint hwprim )
 686 {
 687    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 688
 689    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 690       RADEON_NEWPRIM( rmesa );
 691       rmesa->radeon.swtcl.hw_primitive = hwprim;
 692    }
 693 }
 694
 695 static void radeonRenderPrimitive( GLcontext *ctx, GLenum prim )
 696 {
 697    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 698    rmesa->radeon.swtcl.render_primitive = prim;
 699    if (prim < GL_TRIANGLES || !(ctx->_TriangleCaps & DD_TRI_UNFILLED))
 700       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 701 }
 702
 703 static void radeonRenderFinish( GLcontext *ctx )
 704 {
 705 }
 706
 707 static void radeonResetLineStipple( GLcontext *ctx )
 708 {
 709    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 710    RADEON_STATECHANGE( rmesa, lin );
 711 }
 712
 713
 714 /**********************************************************************/
 715 /*           Transition to/from hardware rasterization.               */
 716 /**********************************************************************/
 717
 718 static const char * const fallbackStrings[] = {
 719    "Texture mode",
 720    "glDrawBuffer(GL_FRONT_AND_BACK)",
 721    "glEnable(GL_STENCIL) without hw stencil buffer",
 722    "glRenderMode(selection or feedback)",
 723    "glBlendEquation",
 724    "glBlendFunc",
 725    "RADEON_NO_RAST",
 726    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 727 };
 728
 729
 730 static const char *getFallbackString(GLuint bit)
 731 {
 732    int i = 0;
 733    while (bit > 1) {
 734       i++;
 735       bit >>= 1;
 736    }
 737    return fallbackStrings[i];
 738 }
 739
 740
 741 void radeonFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 742 {
 743    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 744    TNLcontext *tnl = TNL_CONTEXT(ctx);
 745    GLuint oldfallback = rmesa->radeon.Fallback;
 746
 747    if (mode) {
 748       rmesa->radeon.Fallback |= bit;
 749       if (oldfallback == 0) {
 750          radeon_firevertices(&rmesa->radeon);
 751          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 752          _swsetup_Wakeup( ctx );
 753          rmesa->radeon.swtcl.RenderIndex = ~0;
 754          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 755             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 756                     bit, getFallbackString(bit));
 757          }
 758       }
 759    }
 760    else {
 761       rmesa->radeon.Fallback &= ~bit;
 762       if (oldfallback == bit) {
 763          _swrast_flush( ctx );
 764          tnl->Driver.Render.Start = radeonRenderStart;
 765          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 766          tnl->Driver.Render.Finish = radeonRenderFinish;
 767
 768          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 769          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 770          tnl->Driver.Render.Interp = _tnl_interp;
 771
 772          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 773          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 774          if (rmesa->radeon.TclFallback) {
 775             /* These are already done if rmesa->radeon.TclFallback goes to
 776              * zero above. But not if it doesn't (RADEON_NO_TCL for
 777              * example?)
 778              */
 779             _tnl_invalidate_vertex_state( ctx, ~0 );
 780             _tnl_invalidate_vertices( ctx, ~0 );
 781             RENDERINPUTS_ZERO( rmesa->radeon.tnl_index_bitset );
 782             radeonChooseVertexState( ctx );
 783             radeonChooseRenderState( ctx );
 784          }
 785          if (RADEON_DEBUG & DEBUG_FALLBACKS) {
 786             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 787                     bit, getFallbackString(bit));
 788          }
 789       }
 790    }
 791 }
 792
 793
 794 /**********************************************************************/
 795 /*                            Initialization.                         */
 796 /**********************************************************************/
 797
 798 void radeonInitSwtcl( GLcontext *ctx )
 799 {
 800    TNLcontext *tnl = TNL_CONTEXT(ctx);
 801    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 802    static int firsttime = 1;
 803
 804    if (firsttime) {
 805       init_rast_tab();
 806       firsttime = 0;
 807    }
 808
 809    tnl->Driver.Render.Start = radeonRenderStart;
 810    tnl->Driver.Render.Finish = radeonRenderFinish;
 811    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 812    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 813    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 814    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 815    tnl->Driver.Render.Interp = _tnl_interp;
 816
 817    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 818                        RADEON_MAX_TNL_VERTEX_SIZE);
 819
 820    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 821    rmesa->radeon.swtcl.RenderIndex = ~0;
 822    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 823    rmesa->radeon.swtcl.hw_primitive = 0;
 824 }
 825