src/mesa/drivers/dri/radeon/radeon_swtcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keithw@vmware.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/mtypes.h"
  37 #include "main/enums.h"
  38 #include "main/imports.h"
  39 #include "main/macros.h"
  40 #include "main/state.h"
  41
  42 #include "math/m_xform.h"
  43
  44 #include "swrast_setup/swrast_setup.h"
  45
  46 #include "tnl/tnl.h"
  47 #include "tnl/t_context.h"
  48 #include "tnl/t_pipeline.h"
  49
  50 #include "radeon_context.h"
  51 #include "radeon_ioctl.h"
  52 #include "radeon_state.h"
  53 #include "radeon_swtcl.h"
  54 #include "radeon_tcl.h"
  55 #include "radeon_debug.h"
  56
  57
  58 /* R100: xyzw, c0, c1/fog, stq[0..2]  = 4+1+1+3*3 = 15  right? */
  59 /* R200: xyzw, c0, c1/fog, strq[0..5] = 4+1+1+4*6 = 30 */
  60 #define RADEON_MAX_TNL_VERTEX_SIZE (15 * sizeof(GLfloat))       /* for mesa _tnl stage */
  61
  62 /***********************************************************************
  63  *                         Initialization
  64  ***********************************************************************/
  65
  66 #define EMIT_ATTR( ATTR, STYLE, F0 )                                    \
  67 do {                                                                    \
  68    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = (ATTR);     \
  69    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = (STYLE);    \
  70    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  71    fmt_0 |= F0;                                                         \
  72 } while (0)
  73
  74 #define EMIT_PAD( N )                                                   \
  75 do {                                                                    \
  76    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].attrib = 0;          \
  77    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].format = EMIT_PAD;   \
  78    rmesa->radeon.swtcl.vertex_attrs[rmesa->radeon.swtcl.vertex_attr_count].offset = (N);                \
  79    rmesa->radeon.swtcl.vertex_attr_count++;                                     \
  80 } while (0)
  81
  82 static GLuint radeon_cp_vc_frmts[3][2] =
  83 {
  84    { RADEON_CP_VC_FRMT_ST0, RADEON_CP_VC_FRMT_ST0 | RADEON_CP_VC_FRMT_Q0 },
  85    { RADEON_CP_VC_FRMT_ST1, RADEON_CP_VC_FRMT_ST1 | RADEON_CP_VC_FRMT_Q1 },
  86    { RADEON_CP_VC_FRMT_ST2, RADEON_CP_VC_FRMT_ST2 | RADEON_CP_VC_FRMT_Q2 },
  87 };
  88
  89 static void radeonSetVertexFormat( struct gl_context *ctx )
  90 {
  91    r100ContextPtr rmesa = R100_CONTEXT( ctx );
  92    TNLcontext *tnl = TNL_CONTEXT(ctx);
  93    struct vertex_buffer *VB = &tnl->vb;
  94    GLbitfield64 index_bitset = tnl->render_inputs_bitset;
  95    int fmt_0 = 0;
  96    int offset = 0;
  97
  98    /* Important:
  99     */
 100    if ( VB->NdcPtr != NULL ) {
 101       VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
 102    }
 103    else {
 104       VB->AttribPtr[VERT_ATTRIB_POS] = VB->ClipPtr;
 105    }
 106
 107    assert( VB->AttribPtr[VERT_ATTRIB_POS] != NULL );
 108    rmesa->radeon.swtcl.vertex_attr_count = 0;
 109
 110    /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
 111     * build up a hardware vertex.
 112     */
 113    if ( !rmesa->swtcl.needproj ||
 114         (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) {
 115       /* for projtex */
 116       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_4F,
 117                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z | RADEON_CP_VC_FRMT_W0 );
 118       offset = 4;
 119    }
 120    else {
 121       EMIT_ATTR( _TNL_ATTRIB_POS, EMIT_3F,
 122                  RADEON_CP_VC_FRMT_XY | RADEON_CP_VC_FRMT_Z );
 123       offset = 3;
 124    }
 125
 126    rmesa->swtcl.coloroffset = offset;
 127 #if MESA_LITTLE_ENDIAN
 128    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_RGBA,
 129               RADEON_CP_VC_FRMT_PKCOLOR );
 130 #else
 131    EMIT_ATTR( _TNL_ATTRIB_COLOR0, EMIT_4UB_4F_ABGR,
 132               RADEON_CP_VC_FRMT_PKCOLOR );
 133 #endif
 134    offset += 1;
 135
 136    rmesa->swtcl.specoffset = 0;
 137    if (index_bitset &
 138        (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | BITFIELD64_BIT(_TNL_ATTRIB_FOG))) {
 139
 140 #if MESA_LITTLE_ENDIAN
 141       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 142          rmesa->swtcl.specoffset = offset;
 143          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_RGB,
 144                     RADEON_CP_VC_FRMT_PKSPEC );
 145       }
 146       else {
 147          EMIT_PAD( 3 );
 148       }
 149
 150       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 151          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 152                     RADEON_CP_VC_FRMT_PKSPEC );
 153       }
 154       else {
 155          EMIT_PAD( 1 );
 156       }
 157 #else
 158       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) {
 159          EMIT_ATTR( _TNL_ATTRIB_FOG, EMIT_1UB_1F,
 160                     RADEON_CP_VC_FRMT_PKSPEC );
 161       }
 162       else {
 163          EMIT_PAD( 1 );
 164       }
 165
 166       if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) {
 167          rmesa->swtcl.specoffset = offset;
 168          EMIT_ATTR( _TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR,
 169                     RADEON_CP_VC_FRMT_PKSPEC );
 170       }
 171       else {
 172          EMIT_PAD( 3 );
 173       }
 174 #endif
 175    }
 176
 177    if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) {
 178       int i;
 179
 180       for (i = 0; i < ctx->Const.MaxTextureUnits; i++) {
 181          if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) {
 182             GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
 183
 184             switch (sz) {
 185             case 1:
 186             case 2:
 187                EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 188                           radeon_cp_vc_frmts[i][0] );
 189                break;
 190             case 3:
 191                if (ctx->Texture.Unit[i]._Current &&
 192                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
 193                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 194                               radeon_cp_vc_frmts[i][1] );
 195                } else {
 196                    EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_2F,
 197                               radeon_cp_vc_frmts[i][0] );
 198                }
 199                break;
 200             case 4:
 201                if (ctx->Texture.Unit[i]._Current &&
 202                    ctx->Texture.Unit[i]._Current->Target == GL_TEXTURE_CUBE_MAP) {
 203                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F,
 204                              radeon_cp_vc_frmts[i][1] );
 205                } else {
 206                   EMIT_ATTR( _TNL_ATTRIB_TEX0+i, EMIT_3F_XYW,
 207                              radeon_cp_vc_frmts[i][1] );
 208                }
 209                break;
 210             default:
 211                continue;
 212             };
 213          }
 214       }
 215    }
 216
 217    if (rmesa->radeon.tnl_index_bitset != index_bitset ||
 218        fmt_0 != rmesa->swtcl.vertex_format) {
 219       RADEON_NEWPRIM(rmesa);
 220       rmesa->swtcl.vertex_format = fmt_0;
 221       rmesa->radeon.swtcl.vertex_size =
 222           _tnl_install_attrs( ctx,
 223                               rmesa->radeon.swtcl.vertex_attrs,
 224                               rmesa->radeon.swtcl.vertex_attr_count,
 225                               NULL, 0 );
 226       rmesa->radeon.swtcl.vertex_size /= 4;
 227       rmesa->radeon.tnl_index_bitset = index_bitset;
 228       radeon_print(RADEON_SWRENDER, RADEON_VERBOSE,
 229           "%s: vertex_size= %d floats\n",  __func__, rmesa->radeon.swtcl.vertex_size);
 230    }
 231 }
 232
 233 static void radeon_predict_emit_size( r100ContextPtr rmesa )
 234 {
 235
 236     if (!rmesa->radeon.swtcl.emit_prediction) {
 237         const int state_size = radeonCountStateEmitSize( &rmesa->radeon );
 238         const int scissor_size = 8;
 239         const int prims_size = 8;
 240         const int vertex_size = 7;
 241
 242         if (rcommonEnsureCmdBufSpace(&rmesa->radeon,
 243                     state_size +
 244                     (scissor_size + prims_size + vertex_size),
 245                     __func__))
 246             rmesa->radeon.swtcl.emit_prediction = radeonCountStateEmitSize( &rmesa->radeon );
 247         else
 248             rmesa->radeon.swtcl.emit_prediction = state_size;
 249         rmesa->radeon.swtcl.emit_prediction += scissor_size + prims_size + vertex_size
 250             + rmesa->radeon.cmdbuf.cs->cdw;
 251     }
 252 }
 253
 254 static void radeonRenderStart( struct gl_context *ctx )
 255 {
 256     r100ContextPtr rmesa = R100_CONTEXT( ctx );
 257
 258     radeonSetVertexFormat( ctx );
 259
 260     if (rmesa->radeon.dma.flush != 0 &&
 261             rmesa->radeon.dma.flush != rcommon_flush_last_swtcl_prim)
 262         rmesa->radeon.dma.flush( ctx );
 263 }
 264
 265
 266 /**
 267  * Set vertex state for SW TCL.  The primary purpose of this function is to
 268  * determine in advance whether or not the hardware can / should do the
 269  * projection divide or Mesa should do it.
 270  */
 271 void radeonChooseVertexState( struct gl_context *ctx )
 272 {
 273    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 274    TNLcontext *tnl = TNL_CONTEXT(ctx);
 275
 276    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 277    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 278                          ctx->Polygon.BackMode != GL_FILL);
 279    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 280
 281    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 282                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 283                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 284
 285    /* We must ensure that we don't do _tnl_need_projected_coords while in a
 286     * rasterization fallback.  As this function will be called again when we
 287     * leave a rasterization fallback, we can just skip it for now.
 288     */
 289    if (rmesa->radeon.Fallback != 0)
 290       return;
 291
 292    /* HW perspective divide is a win, but tiny vertex formats are a
 293     * bigger one.
 294     */
 295
 296    if ((0 == (tnl->render_inputs_bitset &
 297         (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)
 298          | BITFIELD64_BIT(_TNL_ATTRIB_COLOR1))))
 299        || twosided
 300        || unfilled) {
 301       rmesa->swtcl.needproj = GL_TRUE;
 302       se_coord_fmt |= (RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 303                       RADEON_VTX_Z_PRE_MULT_1_OVER_W0);
 304    }
 305    else {
 306       rmesa->swtcl.needproj = GL_FALSE;
 307       se_coord_fmt |= (RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 308    }
 309
 310    _tnl_need_projected_coords( ctx, rmesa->swtcl.needproj );
 311
 312    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 313       RADEON_STATECHANGE( rmesa, set );
 314       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 315    }
 316 }
 317
 318 void r100_swtcl_flush(struct gl_context *ctx, uint32_t current_offset)
 319 {
 320    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 321
 322
 323
 324    radeonEmitState(&rmesa->radeon);
 325    radeonEmitVertexAOS( rmesa,
 326                         rmesa->radeon.swtcl.vertex_size,
 327                         rmesa->radeon.swtcl.bo,
 328                         current_offset);
 329
 330
 331    radeonEmitVbufPrim( rmesa,
 332                        rmesa->swtcl.vertex_format,
 333                        rmesa->radeon.swtcl.hw_primitive,
 334                        rmesa->radeon.swtcl.numverts);
 335    if ( rmesa->radeon.swtcl.emit_prediction < rmesa->radeon.cmdbuf.cs->cdw )
 336      WARN_ONCE("Rendering was %d commands larger than predicted size."
 337          " We might overflow  command buffer.\n",
 338          rmesa->radeon.cmdbuf.cs->cdw - rmesa->radeon.swtcl.emit_prediction );
 339
 340
 341    rmesa->radeon.swtcl.emit_prediction = 0;
 342
 343 }
 344
 345 /*
 346  * Render unclipped vertex buffers by emitting vertices directly to
 347  * dma buffers.  Use strip/fan hardware primitives where possible.
 348  * Try to simulate missing primitives with indexed vertices.
 349  */
 350 #define HAVE_POINTS      1
 351 #define HAVE_LINES       1
 352 #define HAVE_LINE_STRIPS 1
 353 #define HAVE_TRIANGLES   1
 354 #define HAVE_TRI_STRIPS  1
 355 #define HAVE_TRI_FANS    1
 356 #define HAVE_POLYGONS    0
 357 /* \todo: is it possible to make "ELTS" work with t_vertex code ? */
 358 #define HAVE_ELTS        0
 359
 360 static const GLuint hw_prim[GL_POLYGON+1] = {
 361    [GL_POINTS] = RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 362    [GL_LINES] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 363    [GL_LINE_LOOP] = 0,
 364    [GL_LINE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP,
 365    [GL_TRIANGLES] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 366    [GL_TRIANGLE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP,
 367    [GL_TRIANGLE_FAN] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN,
 368    [GL_QUADS] = 0,
 369    [GL_QUAD_STRIP] = 0,
 370    [GL_POLYGON] = 0
 371 };
 372
 373 static inline void
 374 radeonDmaPrimitive( r100ContextPtr rmesa, GLenum prim )
 375 {
 376    RADEON_NEWPRIM( rmesa );
 377    rmesa->radeon.swtcl.hw_primitive = hw_prim[prim];
 378    //   assert(rmesa->radeon.dma.current.ptr == rmesa->radeon.dma.current.start);
 379 }
 380
 381 static void* radeon_alloc_verts( r100ContextPtr rmesa , GLuint nr, GLuint size )
 382 {
 383    void *rv;
 384    do {
 385      radeon_predict_emit_size( rmesa );
 386      rv = rcommonAllocDmaLowVerts( &rmesa->radeon, nr, size );
 387    } while (!rv);
 388    return rv;
 389 }
 390
 391 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 392 #define INIT( prim ) radeonDmaPrimitive( rmesa, prim )
 393 #define FLUSH()  RADEON_NEWPRIM( rmesa )
 394 #define GET_CURRENT_VB_MAX_VERTS()                                      10\
 395 //  (((int)rmesa->radeon.dma.current.end - (int)rmesa->radeon.dma.current.ptr) / (rmesa->radeon.swtcl.vertex_size*4))
 396 #define GET_SUBSEQUENT_VB_MAX_VERTS() \
 397   ((RADEON_BUFFER_SIZE) / (rmesa->radeon.swtcl.vertex_size*4))
 398 #define ALLOC_VERTS( nr ) radeon_alloc_verts( rmesa, nr, rmesa->radeon.swtcl.vertex_size * 4 )
 399 #define EMIT_VERTS( ctx, j, nr, buf ) \
 400   _tnl_emit_vertices_to_buffer(ctx, j, (j)+(nr), buf)
 401
 402 #define TAG(x) radeon_dma_##x
 403 #include "tnl_dd/t_dd_dmatmp.h"
 404
 405
 406 /**********************************************************************/
 407 /*                          Render pipeline stage                     */
 408 /**********************************************************************/
 409
 410
 411 static GLboolean radeon_run_render( struct gl_context *ctx,
 412                                     struct tnl_pipeline_stage *stage )
 413 {
 414    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 415    TNLcontext *tnl = TNL_CONTEXT(ctx);
 416    struct vertex_buffer *VB = &tnl->vb;
 417    const tnl_render_func *tab = TAG(render_tab_verts);
 418    GLuint i;
 419
 420    if (rmesa->radeon.swtcl.RenderIndex != 0 ||
 421        !radeon_dma_validate_render( ctx, VB ))
 422       return GL_TRUE;
 423
 424    radeon_prepare_render(&rmesa->radeon);
 425    if (rmesa->radeon.NewGLState)
 426       radeonValidateState( ctx );
 427
 428    tnl->Driver.Render.Start( ctx );
 429
 430    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 431    {
 432       GLuint prim = VB->Primitive[i].mode;
 433       GLuint start = VB->Primitive[i].start;
 434       GLuint length = VB->Primitive[i].count;
 435
 436       if (!length)
 437          continue;
 438
 439       radeon_print(RADEON_SWRENDER, RADEON_NORMAL,
 440           "radeon_render.c: prim %s %d..%d\n",
 441                  _mesa_enum_to_string(prim & PRIM_MODE_MASK),
 442                  start, start+length);
 443
 444       if (length)
 445          tab[prim & PRIM_MODE_MASK](ctx, start, length, prim);
 446    }
 447
 448    tnl->Driver.Render.Finish( ctx );
 449
 450    return GL_FALSE;             /* finished the pipe */
 451 }
 452
 453
 454
 455 const struct tnl_pipeline_stage _radeon_render_stage =
 456 {
 457    "radeon render",
 458    NULL,
 459    NULL,
 460    NULL,
 461    NULL,
 462    radeon_run_render            /* run */
 463 };
 464
 465
 466 /**************************************************************************/
 467
 468
 469 static const GLuint reduced_hw_prim[GL_POLYGON+1] = {
 470    [GL_POINTS] = RADEON_CP_VC_CNTL_PRIM_TYPE_POINT,
 471    [GL_LINES] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 472    [GL_LINE_LOOP] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 473    [GL_LINE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_LINE,
 474    [GL_TRIANGLES] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 475    [GL_TRIANGLE_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 476    [GL_TRIANGLE_FAN] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 477    [GL_QUADS] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 478    [GL_QUAD_STRIP] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST,
 479    [GL_POLYGON] = RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
 480 };
 481
 482 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim );
 483 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim );
 484 static void radeonResetLineStipple( struct gl_context *ctx );
 485
 486
 487 /***********************************************************************
 488  *                    Emit primitives as inline vertices               *
 489  ***********************************************************************/
 490
 491 #undef LOCAL_VARS
 492 #undef ALLOC_VERTS
 493 #define CTX_ARG r100ContextPtr rmesa
 494 #define GET_VERTEX_DWORDS() rmesa->radeon.swtcl.vertex_size
 495 #define ALLOC_VERTS( n, size ) radeon_alloc_verts( rmesa, n, (size) * 4 )
 496 #undef LOCAL_VARS
 497 #define LOCAL_VARS                                              \
 498    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 499    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;
 500 #define VERT(x) (radeonVertex *)(radeonverts + ((x) * (vertsize) * sizeof(int)))
 501 #define VERTEX radeonVertex
 502 #undef TAG
 503 #define TAG(x) radeon_##x
 504 #include "tnl_dd/t_dd_triemit.h"
 505
 506
 507 /***********************************************************************
 508  *          Macros for t_dd_tritmp.h to draw basic primitives          *
 509  ***********************************************************************/
 510
 511 #define QUAD( a, b, c, d ) radeon_quad( rmesa, a, b, c, d )
 512 #define TRI( a, b, c )     radeon_triangle( rmesa, a, b, c )
 513 #define LINE( a, b )       radeon_line( rmesa, a, b )
 514 #define POINT( a )         radeon_point( rmesa, a )
 515
 516 /***********************************************************************
 517  *              Build render functions from dd templates               *
 518  ***********************************************************************/
 519
 520 #define RADEON_TWOSIDE_BIT      0x01
 521 #define RADEON_UNFILLED_BIT     0x02
 522 #define RADEON_MAX_TRIFUNC      0x04
 523
 524
 525 static struct {
 526    tnl_points_func              points;
 527    tnl_line_func                line;
 528    tnl_triangle_func    triangle;
 529    tnl_quad_func                quad;
 530 } rast_tab[RADEON_MAX_TRIFUNC];
 531
 532
 533 #define DO_FALLBACK  0
 534 #define DO_OFFSET    0
 535 #define DO_UNFILLED ((IND & RADEON_UNFILLED_BIT) != 0)
 536 #define DO_TWOSIDE  ((IND & RADEON_TWOSIDE_BIT) != 0)
 537 #define DO_FLAT      0
 538 #define DO_TRI       1
 539 #define DO_QUAD      1
 540 #define DO_LINE      1
 541 #define DO_POINTS    1
 542 #define DO_FULL_QUAD 1
 543
 544 #define HAVE_SPEC   1
 545 #define HAVE_BACK_COLORS  0
 546 #define HAVE_HW_FLATSHADE 1
 547 #define TAB rast_tab
 548
 549 #define DEPTH_SCALE 1.0
 550 #define UNFILLED_TRI unfilled_tri
 551 #define UNFILLED_QUAD unfilled_quad
 552 #define VERT_X(_v) _v->v.x
 553 #define VERT_Y(_v) _v->v.y
 554 #define VERT_Z(_v) _v->v.z
 555 #define AREA_IS_CCW( a ) (a < 0)
 556 #define GET_VERTEX(e) (rmesa->radeon.swtcl.verts + ((e) * rmesa->radeon.swtcl.vertex_size * sizeof(int)))
 557
 558 #define VERT_SET_RGBA( v, c )                                   \
 559 do {                                                            \
 560    radeon_color_t *color = (radeon_color_t *)&((v)->ui[coloroffset]);   \
 561    UNCLAMPED_FLOAT_TO_UBYTE(color->red, (c)[0]);                \
 562    UNCLAMPED_FLOAT_TO_UBYTE(color->green, (c)[1]);              \
 563    UNCLAMPED_FLOAT_TO_UBYTE(color->blue, (c)[2]);               \
 564    UNCLAMPED_FLOAT_TO_UBYTE(color->alpha, (c)[3]);              \
 565 } while (0)
 566
 567 #define VERT_COPY_RGBA( v0, v1 ) v0->ui[coloroffset] = v1->ui[coloroffset]
 568
 569 #define VERT_SET_SPEC( v, c )                                   \
 570 do {                                                            \
 571    if (specoffset) {                                            \
 572       radeon_color_t *spec = (radeon_color_t *)&((v)->ui[specoffset]);  \
 573       UNCLAMPED_FLOAT_TO_UBYTE(spec->red, (c)[0]);      \
 574       UNCLAMPED_FLOAT_TO_UBYTE(spec->green, (c)[1]);    \
 575       UNCLAMPED_FLOAT_TO_UBYTE(spec->blue, (c)[2]);     \
 576    }                                                            \
 577 } while (0)
 578 #define VERT_COPY_SPEC( v0, v1 )                        \
 579 do {                                                    \
 580    if (specoffset) {                                    \
 581       radeon_color_t *spec0 = (radeon_color_t *)&((v0)->ui[specoffset]);        \
 582       radeon_color_t *spec1 = (radeon_color_t *)&((v1)->ui[specoffset]);        \
 583       spec0->red   = spec1->red;        \
 584       spec0->green = spec1->green;      \
 585       spec0->blue  = spec1->blue;       \
 586    }                                                    \
 587 } while (0)
 588
 589 /* These don't need LE32_TO_CPU() as they used to save and restore
 590  * colors which are already in the correct format.
 591  */
 592 #define VERT_SAVE_RGBA( idx )    color[idx] = v[idx]->ui[coloroffset]
 593 #define VERT_RESTORE_RGBA( idx ) v[idx]->ui[coloroffset] = color[idx]
 594 #define VERT_SAVE_SPEC( idx )    if (specoffset) spec[idx] = v[idx]->ui[specoffset]
 595 #define VERT_RESTORE_SPEC( idx ) if (specoffset) v[idx]->ui[specoffset] = spec[idx]
 596
 597 #undef LOCAL_VARS
 598 #undef TAG
 599 #undef INIT
 600
 601 #define LOCAL_VARS(n)                                                   \
 602    r100ContextPtr rmesa = R100_CONTEXT(ctx);                    \
 603    GLuint color[n] = {0}, spec[n] = {0};                                                \
 604    GLuint coloroffset = rmesa->swtcl.coloroffset;       \
 605    GLuint specoffset = rmesa->swtcl.specoffset;                 \
 606    (void) color; (void) spec; (void) coloroffset; (void) specoffset;
 607
 608 /***********************************************************************
 609  *                Helpers for rendering unfilled primitives            *
 610  ***********************************************************************/
 611
 612 #define RASTERIZE(x) radeonRasterPrimitive( ctx, reduced_hw_prim[x] )
 613 #define RENDER_PRIMITIVE rmesa->radeon.swtcl.render_primitive
 614 #undef TAG
 615 #define TAG(x) x
 616 #include "tnl_dd/t_dd_unfilled.h"
 617 #undef IND
 618
 619
 620 /***********************************************************************
 621  *                      Generate GL render functions                   *
 622  ***********************************************************************/
 623
 624
 625 #define IND (0)
 626 #define TAG(x) x
 627 #include "tnl_dd/t_dd_tritmp.h"
 628
 629 #define IND (RADEON_TWOSIDE_BIT)
 630 #define TAG(x) x##_twoside
 631 #include "tnl_dd/t_dd_tritmp.h"
 632
 633 #define IND (RADEON_UNFILLED_BIT)
 634 #define TAG(x) x##_unfilled
 635 #include "tnl_dd/t_dd_tritmp.h"
 636
 637 #define IND (RADEON_TWOSIDE_BIT|RADEON_UNFILLED_BIT)
 638 #define TAG(x) x##_twoside_unfilled
 639 #include "tnl_dd/t_dd_tritmp.h"
 640
 641
 642 static void init_rast_tab( void )
 643 {
 644    init();
 645    init_twoside();
 646    init_unfilled();
 647    init_twoside_unfilled();
 648 }
 649
 650 /**********************************************************************/
 651 /*               Render unclipped begin/end objects                   */
 652 /**********************************************************************/
 653
 654 #define RENDER_POINTS( start, count )           \
 655    for ( ; start < count ; start++)             \
 656       radeon_point( rmesa, VERT(start) )
 657 #define RENDER_LINE( v0, v1 ) \
 658    radeon_line( rmesa, VERT(v0), VERT(v1) )
 659 #define RENDER_TRI( v0, v1, v2 )  \
 660    radeon_triangle( rmesa, VERT(v0), VERT(v1), VERT(v2) )
 661 #define RENDER_QUAD( v0, v1, v2, v3 ) \
 662    radeon_quad( rmesa, VERT(v0), VERT(v1), VERT(v2), VERT(v3) )
 663 #undef INIT
 664 #define INIT(x) do {                                    \
 665    radeonRenderPrimitive( ctx, x );                     \
 666 } while (0)
 667 #undef LOCAL_VARS
 668 #define LOCAL_VARS                                              \
 669    r100ContextPtr rmesa = R100_CONTEXT(ctx);            \
 670    const GLuint vertsize = rmesa->radeon.swtcl.vertex_size;             \
 671    const char *radeonverts = (char *)rmesa->radeon.swtcl.verts;         \
 672    const GLuint * const elt = TNL_CONTEXT(ctx)->vb.Elts;        \
 673    const GLboolean stipple = ctx->Line.StippleFlag;             \
 674    (void) elt; (void) stipple;
 675 #define RESET_STIPPLE   if ( stipple ) radeonResetLineStipple( ctx );
 676 #define RESET_OCCLUSION
 677 #define PRESERVE_VB_DEFS
 678 #define ELT(x) (x)
 679 #define TAG(x) radeon_##x##_verts
 680 #include "tnl/t_vb_rendertmp.h"
 681 #undef ELT
 682 #undef TAG
 683 #define TAG(x) radeon_##x##_elts
 684 #define ELT(x) elt[x]
 685 #include "tnl/t_vb_rendertmp.h"
 686
 687
 688
 689 /**********************************************************************/
 690 /*                    Choose render functions                         */
 691 /**********************************************************************/
 692
 693 void radeonChooseRenderState( struct gl_context *ctx )
 694 {
 695    TNLcontext *tnl = TNL_CONTEXT(ctx);
 696    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 697    GLuint index = 0;
 698    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 699                          ctx->Polygon.BackMode != GL_FILL);
 700    GLboolean twosided = ctx->Light.Enabled && ctx->Light.Model.TwoSide;
 701
 702    if (!rmesa->radeon.TclFallback || rmesa->radeon.Fallback)
 703       return;
 704
 705    if (twosided)
 706       index |= RADEON_TWOSIDE_BIT;
 707    if (unfilled)
 708       index |= RADEON_UNFILLED_BIT;
 709
 710    if (index != rmesa->radeon.swtcl.RenderIndex) {
 711       tnl->Driver.Render.Points = rast_tab[index].points;
 712       tnl->Driver.Render.Line = rast_tab[index].line;
 713       tnl->Driver.Render.ClippedLine = rast_tab[index].line;
 714       tnl->Driver.Render.Triangle = rast_tab[index].triangle;
 715       tnl->Driver.Render.Quad = rast_tab[index].quad;
 716
 717       if (index == 0) {
 718          tnl->Driver.Render.PrimTabVerts = radeon_render_tab_verts;
 719          tnl->Driver.Render.PrimTabElts = radeon_render_tab_elts;
 720          tnl->Driver.Render.ClippedPolygon = radeon_fast_clipped_poly;
 721       } else {
 722          tnl->Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
 723          tnl->Driver.Render.PrimTabElts = _tnl_render_tab_elts;
 724          tnl->Driver.Render.ClippedPolygon = _tnl_RenderClippedPolygon;
 725       }
 726
 727       rmesa->radeon.swtcl.RenderIndex = index;
 728    }
 729 }
 730
 731
 732 /**********************************************************************/
 733 /*                 High level hooks for t_vb_render.c                 */
 734 /**********************************************************************/
 735
 736
 737 static void radeonRasterPrimitive( struct gl_context *ctx, GLuint hwprim )
 738 {
 739    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 740
 741    if (rmesa->radeon.swtcl.hw_primitive != hwprim) {
 742       RADEON_NEWPRIM( rmesa );
 743       rmesa->radeon.swtcl.hw_primitive = hwprim;
 744    }
 745 }
 746
 747 static void radeonRenderPrimitive( struct gl_context *ctx, GLenum prim )
 748 {
 749    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 750    GLboolean unfilled = (ctx->Polygon.FrontMode != GL_FILL ||
 751                          ctx->Polygon.BackMode != GL_FILL);
 752
 753    rmesa->radeon.swtcl.render_primitive = prim;
 754    if (prim < GL_TRIANGLES || !unfilled)
 755       radeonRasterPrimitive( ctx, reduced_hw_prim[prim] );
 756 }
 757
 758 static void radeonRenderFinish( struct gl_context *ctx )
 759 {
 760 }
 761
 762 static void radeonResetLineStipple( struct gl_context *ctx )
 763 {
 764    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 765    RADEON_STATECHANGE( rmesa, lin );
 766 }
 767
 768
 769 /**********************************************************************/
 770 /*           Transition to/from hardware rasterization.               */
 771 /**********************************************************************/
 772
 773 static const char * const fallbackStrings[] = {
 774    "Texture mode",
 775    "glDrawBuffer(GL_FRONT_AND_BACK)",
 776    "glEnable(GL_STENCIL) without hw stencil buffer",
 777    "glRenderMode(selection or feedback)",
 778    "glBlendEquation",
 779    "glBlendFunc",
 780    "RADEON_NO_RAST",
 781    "Mixing GL_CLAMP_TO_BORDER and GL_CLAMP (or GL_MIRROR_CLAMP_ATI)"
 782 };
 783
 784
 785 static const char *getFallbackString(GLuint bit)
 786 {
 787    int i = 0;
 788    while (bit > 1) {
 789       i++;
 790       bit >>= 1;
 791    }
 792    return fallbackStrings[i];
 793 }
 794
 795
 796 void radeonFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
 797 {
 798    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 799    TNLcontext *tnl = TNL_CONTEXT(ctx);
 800    GLuint oldfallback = rmesa->radeon.Fallback;
 801
 802    if (mode) {
 803       rmesa->radeon.Fallback |= bit;
 804       if (oldfallback == 0) {
 805          radeon_firevertices(&rmesa->radeon);
 806          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_TRUE );
 807          _swsetup_Wakeup( ctx );
 808          rmesa->radeon.swtcl.RenderIndex = ~0;
 809          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 810             fprintf(stderr, "Radeon begin rasterization fallback: 0x%x %s\n",
 811                     bit, getFallbackString(bit));
 812          }
 813       }
 814    }
 815    else {
 816       rmesa->radeon.Fallback &= ~bit;
 817       if (oldfallback == bit) {
 818          _swrast_flush( ctx );
 819          tnl->Driver.Render.Start = radeonRenderStart;
 820          tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 821          tnl->Driver.Render.Finish = radeonRenderFinish;
 822
 823          tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 824          tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 825          tnl->Driver.Render.Interp = _tnl_interp;
 826
 827          tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 828          TCL_FALLBACK( ctx, RADEON_TCL_FALLBACK_RASTER, GL_FALSE );
 829          if (rmesa->radeon.TclFallback) {
 830             /* These are already done if rmesa->radeon.TclFallback goes to
 831              * zero above. But not if it doesn't (RADEON_NO_TCL for
 832              * example?)
 833              */
 834             _tnl_invalidate_vertex_state( ctx, ~0 );
 835             _tnl_invalidate_vertices( ctx, ~0 );
 836             rmesa->radeon.tnl_index_bitset = 0;
 837             radeonChooseVertexState( ctx );
 838             radeonChooseRenderState( ctx );
 839          }
 840          if (RADEON_DEBUG & RADEON_FALLBACKS) {
 841             fprintf(stderr, "Radeon end rasterization fallback: 0x%x %s\n",
 842                     bit, getFallbackString(bit));
 843          }
 844       }
 845    }
 846 }
 847
 848
 849 /**********************************************************************/
 850 /*                            Initialization.                         */
 851 /**********************************************************************/
 852
 853 void radeonInitSwtcl( struct gl_context *ctx )
 854 {
 855    TNLcontext *tnl = TNL_CONTEXT(ctx);
 856    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 857    static int firsttime = 1;
 858
 859    if (firsttime) {
 860       init_rast_tab();
 861       firsttime = 0;
 862    }
 863    rmesa->radeon.swtcl.emit_prediction = 0;
 864
 865    tnl->Driver.Render.Start = radeonRenderStart;
 866    tnl->Driver.Render.Finish = radeonRenderFinish;
 867    tnl->Driver.Render.PrimitiveNotify = radeonRenderPrimitive;
 868    tnl->Driver.Render.ResetLineStipple = radeonResetLineStipple;
 869    tnl->Driver.Render.BuildVertices = _tnl_build_vertices;
 870    tnl->Driver.Render.CopyPV = _tnl_copy_pv;
 871    tnl->Driver.Render.Interp = _tnl_interp;
 872
 873    _tnl_init_vertices( ctx, ctx->Const.MaxArrayLockSize + 12,
 874                        RADEON_MAX_TNL_VERTEX_SIZE);
 875
 876    rmesa->radeon.swtcl.verts = (GLubyte *)tnl->clipspace.vertex_buf;
 877    rmesa->radeon.swtcl.RenderIndex = ~0;
 878    rmesa->radeon.swtcl.render_primitive = GL_TRIANGLES;
 879    rmesa->radeon.swtcl.hw_primitive = 0;
 880 }
 881