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[mesa.git] / src / mesa / drivers / dri / radeon / radeon_tcl.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 Tungsten Graphics Inc., Austin, Texas.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keith@tungstengraphics.com>
33 */
34
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/light.h"
38 #include "main/mtypes.h"
39 #include "main/enums.h"
40
41 #include "vbo/vbo.h"
42 #include "tnl/tnl.h"
43 #include "tnl/t_pipeline.h"
44
45 #include "radeon_common.h"
46 #include "radeon_context.h"
47 #include "radeon_state.h"
48 #include "radeon_ioctl.h"
49 #include "radeon_tex.h"
50 #include "radeon_tcl.h"
51 #include "radeon_swtcl.h"
52 #include "radeon_maos.h"
53
54
55
56 /*
57 * Render unclipped vertex buffers by emitting vertices directly to
58 * dma buffers. Use strip/fan hardware primitives where possible.
59 * Try to simulate missing primitives with indexed vertices.
60 */
61 #define HAVE_POINTS 1
62 #define HAVE_LINES 1
63 #define HAVE_LINE_LOOP 0
64 #define HAVE_LINE_STRIPS 1
65 #define HAVE_TRIANGLES 1
66 #define HAVE_TRI_STRIPS 1
67 #define HAVE_TRI_STRIP_1 0
68 #define HAVE_TRI_FANS 1
69 #define HAVE_QUADS 0
70 #define HAVE_QUAD_STRIPS 0
71 #define HAVE_POLYGONS 1
72 #define HAVE_ELTS 1
73
74
75 #define HW_POINTS RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
76 #define HW_LINES RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
77 #define HW_LINE_LOOP 0
78 #define HW_LINE_STRIP RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
79 #define HW_TRIANGLES RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
80 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
81 #define HW_TRIANGLE_STRIP_1 0
82 #define HW_TRIANGLE_FAN RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
83 #define HW_QUADS 0
84 #define HW_QUAD_STRIP 0
85 #define HW_POLYGON RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
86
87
88 static GLboolean discrete_prim[0x10] = {
89 0, /* 0 none */
90 1, /* 1 points */
91 1, /* 2 lines */
92 0, /* 3 line_strip */
93 1, /* 4 tri_list */
94 0, /* 5 tri_fan */
95 0, /* 6 tri_type2 */
96 1, /* 7 rect list (unused) */
97 1, /* 8 3vert point */
98 1, /* 9 3vert line */
99 0,
100 0,
101 0,
102 0,
103 0,
104 0,
105 };
106
107
108 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
109 #define ELT_TYPE GLushort
110
111 #define ELT_INIT(prim, hw_prim) \
112 radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
113
114 #define GET_MESA_ELTS() rmesa->tcl.Elts
115
116
117 /* Don't really know how many elts will fit in what's left of cmdbuf,
118 * as there is state to emit, etc:
119 */
120
121 /* Testing on isosurf shows a maximum around here. Don't know if it's
122 * the card or driver or kernel module that is causing the behaviour.
123 */
124 #define GET_MAX_HW_ELTS() 300
125
126
127 #define RESET_STIPPLE() do { \
128 RADEON_STATECHANGE( rmesa, lin ); \
129 radeonEmitState(&rmesa->radeon); \
130 } while (0)
131
132 #define AUTO_STIPPLE( mode ) do { \
133 RADEON_STATECHANGE( rmesa, lin ); \
134 if (mode) \
135 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
136 RADEON_LINE_PATTERN_AUTO_RESET; \
137 else \
138 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
139 ~RADEON_LINE_PATTERN_AUTO_RESET; \
140 radeonEmitState(&rmesa->radeon); \
141 } while (0)
142
143
144
145 #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
146
147 static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr )
148 {
149 if (rmesa->radeon.dma.flush)
150 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
151
152 radeonEmitAOS( rmesa,
153 rmesa->radeon.tcl.aos_count, 0 );
154
155 return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
156 rmesa->tcl.hw_primitive, nr );
157 }
158
159 #define CLOSE_ELTS() if (0) RADEON_NEWPRIM( rmesa )
160
161
162
163 /* TODO: Try to extend existing primitive if both are identical,
164 * discrete and there are no intervening state changes. (Somewhat
165 * duplicates changes to DrawArrays code)
166 */
167 static void radeonEmitPrim( GLcontext *ctx,
168 GLenum prim,
169 GLuint hwprim,
170 GLuint start,
171 GLuint count)
172 {
173 r100ContextPtr rmesa = R100_CONTEXT( ctx );
174 radeonTclPrimitive( ctx, prim, hwprim );
175
176 radeonEmitAOS( rmesa,
177 rmesa->radeon.tcl.aos_count,
178 start );
179
180 /* Why couldn't this packet have taken an offset param?
181 */
182 radeonEmitVbufPrim( rmesa,
183 rmesa->tcl.vertex_format,
184 rmesa->tcl.hw_primitive,
185 count - start );
186 }
187
188 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do { \
189 radeonEmitPrim( ctx, prim, hwprim, start, count ); \
190 (void) rmesa; } while (0)
191
192 #define MAX_CONVERSION_SIZE 40
193
194 /* Try & join small primitives
195 */
196 #if 0
197 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
198 #else
199 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \
200 ((NR) < 20 || \
201 ((NR) < 40 && \
202 rmesa->tcl.hw_primitive == (PRIM| \
203 RADEON_CP_VC_CNTL_PRIM_WALK_IND| \
204 RADEON_CP_VC_CNTL_TCL_ENABLE)))
205 #endif
206
207 #ifdef MESA_BIG_ENDIAN
208 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
209 #define EMIT_ELT(dest, offset, x) do { \
210 int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \
211 GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \
212 (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \
213 (void)rmesa; } while (0)
214 #else
215 #define EMIT_ELT(dest, offset, x) do { \
216 (dest)[offset] = (GLushort) (x); \
217 (void)rmesa; } while (0)
218 #endif
219
220 #define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)(dest+offset) = ((y)<<16)|(x);
221
222
223
224 #define TAG(x) tcl_##x
225 #include "tnl_dd/t_dd_dmatmp2.h"
226
227 /**********************************************************************/
228 /* External entrypoints */
229 /**********************************************************************/
230
231 void radeonEmitPrimitive( GLcontext *ctx,
232 GLuint first,
233 GLuint last,
234 GLuint flags )
235 {
236 tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
237 }
238
239 void radeonEmitEltPrimitive( GLcontext *ctx,
240 GLuint first,
241 GLuint last,
242 GLuint flags )
243 {
244 tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
245 }
246
247 void radeonTclPrimitive( GLcontext *ctx,
248 GLenum prim,
249 int hw_prim )
250 {
251 r100ContextPtr rmesa = R100_CONTEXT(ctx);
252 GLuint se_cntl;
253 GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
254
255 if (newprim != rmesa->tcl.hw_primitive ||
256 !discrete_prim[hw_prim&0xf]) {
257 RADEON_NEWPRIM( rmesa );
258 rmesa->tcl.hw_primitive = newprim;
259 }
260
261 se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
262 se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST;
263
264 if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE))
265 se_cntl |= RADEON_FLAT_SHADE_VTX_0;
266 else
267 se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
268
269 if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
270 RADEON_STATECHANGE( rmesa, set );
271 rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
272 }
273 }
274
275 /**********************************************************************/
276 /* Fog blend factor computation for hw tcl */
277 /* same calculation used as in t_vb_fog.c */
278 /**********************************************************************/
279
280 #define FOG_EXP_TABLE_SIZE 256
281 #define FOG_MAX (10.0)
282 #define EXP_FOG_MAX .0006595
283 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
284 static GLfloat exp_table[FOG_EXP_TABLE_SIZE];
285
286 #if 1
287 #define NEG_EXP( result, narg ) \
288 do { \
289 GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR)); \
290 GLint k = (GLint) f; \
291 if (k > FOG_EXP_TABLE_SIZE-2) \
292 result = (GLfloat) EXP_FOG_MAX; \
293 else \
294 result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]); \
295 } while (0)
296 #else
297 #define NEG_EXP( result, narg ) \
298 do { \
299 result = exp(-narg); \
300 } while (0)
301 #endif
302
303
304 /**
305 * Initialize the exp_table[] lookup table for approximating exp().
306 */
307 void
308 radeonInitStaticFogData( void )
309 {
310 GLfloat f = 0.0F;
311 GLint i = 0;
312 for ( ; i < FOG_EXP_TABLE_SIZE ; i++, f += FOG_INCR) {
313 exp_table[i] = (GLfloat) exp(-f);
314 }
315 }
316
317
318 /**
319 * Compute per-vertex fog blend factors from fog coordinates by
320 * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
321 * Fog coordinates are distances from the eye (typically between the
322 * near and far clip plane distances).
323 * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
324 * Fog blend factors are in the range [0,1].
325 */
326 float
327 radeonComputeFogBlendFactor( GLcontext *ctx, GLfloat fogcoord )
328 {
329 GLfloat end = ctx->Fog.End;
330 GLfloat d, temp;
331 const GLfloat z = FABSF(fogcoord);
332
333 switch (ctx->Fog.Mode) {
334 case GL_LINEAR:
335 if (ctx->Fog.Start == ctx->Fog.End)
336 d = 1.0F;
337 else
338 d = 1.0F / (ctx->Fog.End - ctx->Fog.Start);
339 temp = (end - z) * d;
340 return CLAMP(temp, 0.0F, 1.0F);
341 break;
342 case GL_EXP:
343 d = ctx->Fog.Density;
344 NEG_EXP( temp, d * z );
345 return temp;
346 break;
347 case GL_EXP2:
348 d = ctx->Fog.Density*ctx->Fog.Density;
349 NEG_EXP( temp, d * z * z );
350 return temp;
351 break;
352 default:
353 _mesa_problem(ctx, "Bad fog mode in make_fog_coord");
354 return 0;
355 }
356 }
357
358 /**
359 * Predict total emit size for next rendering operation so there is no flush in middle of rendering
360 * Prediction has to aim towards the best possible value that is worse than worst case scenario
361 */
362 static void radeonEnsureEmitSize( GLcontext * ctx , GLuint inputs )
363 {
364 r100ContextPtr rmesa = R100_CONTEXT(ctx);
365 TNLcontext *tnl = TNL_CONTEXT(ctx);
366 struct vertex_buffer *VB = &tnl->vb;
367 GLuint space_required;
368 GLuint nr_aos = 1; /* radeonEmitArrays does always emit one */
369 int i;
370 /* list of flags that are allocating aos object */
371 const GLuint flags_to_check[] = {
372 VERT_BIT_NORMAL,
373 VERT_BIT_COLOR0,
374 VERT_BIT_COLOR1,
375 VERT_BIT_FOG
376 };
377 /* predict number of aos to emit */
378 for (i=0; i < sizeof(flags_to_check)/sizeof(flags_to_check[0]); ++i)
379 {
380 if (inputs & flags_to_check[i])
381 ++nr_aos;
382 }
383 for (i = 0; i < ctx->Const.MaxTextureUnits; ++i)
384 {
385 if (inputs & VERT_BIT_TEX(i))
386 ++nr_aos;
387 }
388
389 {
390 /* count the prediction for state size */
391 space_required = radeonCountStateEmitSize( &rmesa->radeon );
392 /* tcl may be changed in radeonEmitArrays so account for it if not dirty */
393 if (!rmesa->hw.tcl.dirty)
394 space_required += rmesa->hw.tcl.check( rmesa->radeon.glCtx, &rmesa->hw.tcl );
395 /* predict size for elements */
396 for (i = 0; i < VB->PrimitiveCount; ++i)
397 {
398 if (!VB->Primitive[i].count)
399 continue;
400 /* If primitive.count is less than MAX_CONVERSION_SIZE
401 rendering code may decide convert to elts.
402 In that case we have to make pessimistic prediction.
403 and use larger of 2 paths. */
404 const GLuint elts = ELTS_BUFSZ(nr_aos);
405 const GLuint index = INDEX_BUFSZ;
406 const GLuint vbuf = VBUF_BUFSZ;
407 if ( (!VB->Elts && VB->Primitive[i].count >= MAX_CONVERSION_SIZE)
408 || vbuf > index + elts)
409 space_required += vbuf;
410 else
411 space_required += index + elts;
412 space_required += AOS_BUFSZ(nr_aos);
413 }
414 space_required += SCISSOR_BUFSZ;
415 }
416 /* flush the buffer in case we need more than is left. */
417 rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __FUNCTION__);
418 }
419
420 /**********************************************************************/
421 /* Render pipeline stage */
422 /**********************************************************************/
423
424
425 /* TCL render.
426 */
427 static GLboolean radeon_run_tcl_render( GLcontext *ctx,
428 struct tnl_pipeline_stage *stage )
429 {
430 r100ContextPtr rmesa = R100_CONTEXT(ctx);
431 TNLcontext *tnl = TNL_CONTEXT(ctx);
432 struct vertex_buffer *VB = &tnl->vb;
433 GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
434 GLuint i;
435
436 /* TODO: separate this from the swtnl pipeline
437 */
438 if (rmesa->radeon.TclFallback)
439 return GL_TRUE; /* fallback to software t&l */
440
441 if (VB->Count == 0)
442 return GL_FALSE;
443
444 /* NOTE: inputs != tnl->render_inputs - these are the untransformed
445 * inputs.
446 */
447 if (ctx->Light.Enabled) {
448 inputs |= VERT_BIT_NORMAL;
449 }
450
451 if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
452 inputs |= VERT_BIT_COLOR1;
453 }
454
455 if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) {
456 inputs |= VERT_BIT_FOG;
457 }
458
459 for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
460 if (ctx->Texture.Unit[i]._ReallyEnabled) {
461 /* TODO: probably should not emit texture coords when texgen is enabled */
462 if (rmesa->TexGenNeedNormals[i]) {
463 inputs |= VERT_BIT_NORMAL;
464 }
465 inputs |= VERT_BIT_TEX(i);
466 }
467 }
468
469 radeonReleaseArrays( ctx, ~0 );
470 radeonEnsureEmitSize( ctx, inputs );
471 radeonEmitArrays( ctx, inputs );
472
473 rmesa->tcl.Elts = VB->Elts;
474
475 for (i = 0 ; i < VB->PrimitiveCount ; i++)
476 {
477 GLuint prim = _tnl_translate_prim(&VB->Primitive[i]);
478 GLuint start = VB->Primitive[i].start;
479 GLuint length = VB->Primitive[i].count;
480
481 if (!length)
482 continue;
483
484 if (rmesa->tcl.Elts)
485 radeonEmitEltPrimitive( ctx, start, start+length, prim );
486 else
487 radeonEmitPrimitive( ctx, start, start+length, prim );
488 }
489
490 return GL_FALSE; /* finished the pipe */
491 }
492
493
494
495 /* Initial state for tcl stage.
496 */
497 const struct tnl_pipeline_stage _radeon_tcl_stage =
498 {
499 "radeon render",
500 NULL,
501 NULL,
502 NULL,
503 NULL,
504 radeon_run_tcl_render /* run */
505 };
506
507
508
509 /**********************************************************************/
510 /* Validate state at pipeline start */
511 /**********************************************************************/
512
513
514 /*-----------------------------------------------------------------------
515 * Manage TCL fallbacks
516 */
517
518
519 static void transition_to_swtnl( GLcontext *ctx )
520 {
521 r100ContextPtr rmesa = R100_CONTEXT(ctx);
522 TNLcontext *tnl = TNL_CONTEXT(ctx);
523 GLuint se_cntl;
524
525 RADEON_NEWPRIM( rmesa );
526 rmesa->swtcl.vertex_format = 0;
527
528 radeonChooseVertexState( ctx );
529 radeonChooseRenderState( ctx );
530
531 _mesa_validate_all_lighting_tables( ctx );
532
533 tnl->Driver.NotifyMaterialChange =
534 _mesa_validate_all_lighting_tables;
535
536 radeonReleaseArrays( ctx, ~0 );
537
538 se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
539 se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
540
541 if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
542 RADEON_STATECHANGE( rmesa, set );
543 rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
544 }
545 }
546
547
548 static void transition_to_hwtnl( GLcontext *ctx )
549 {
550 r100ContextPtr rmesa = R100_CONTEXT(ctx);
551 TNLcontext *tnl = TNL_CONTEXT(ctx);
552 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
553
554 se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
555 RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
556 RADEON_VTX_W0_IS_NOT_1_OVER_W0);
557 se_coord_fmt |= RADEON_VTX_W0_IS_NOT_1_OVER_W0;
558
559 if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
560 RADEON_STATECHANGE( rmesa, set );
561 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
562 _tnl_need_projected_coords( ctx, GL_FALSE );
563 }
564
565 radeonUpdateMaterial( ctx );
566
567 tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
568
569 if ( rmesa->radeon.dma.flush )
570 rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
571
572 rmesa->radeon.dma.flush = NULL;
573 rmesa->swtcl.vertex_format = 0;
574
575 // if (rmesa->swtcl.indexed_verts.buf)
576 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
577 // __FUNCTION__ );
578
579 if (RADEON_DEBUG & DEBUG_FALLBACKS)
580 fprintf(stderr, "Radeon end tcl fallback\n");
581 }
582
583 static char *fallbackStrings[] = {
584 "Rasterization fallback",
585 "Unfilled triangles",
586 "Twosided lighting, differing materials",
587 "Materials in VB (maybe between begin/end)",
588 "Texgen unit 0",
589 "Texgen unit 1",
590 "Texgen unit 2",
591 "User disable",
592 "Fogcoord with separate specular lighting"
593 };
594
595
596 static char *getFallbackString(GLuint bit)
597 {
598 int i = 0;
599 while (bit > 1) {
600 i++;
601 bit >>= 1;
602 }
603 return fallbackStrings[i];
604 }
605
606
607
608 void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
609 {
610 r100ContextPtr rmesa = R100_CONTEXT(ctx);
611 GLuint oldfallback = rmesa->radeon.TclFallback;
612
613 if (mode) {
614 rmesa->radeon.TclFallback |= bit;
615 if (oldfallback == 0) {
616 if (RADEON_DEBUG & DEBUG_FALLBACKS)
617 fprintf(stderr, "Radeon begin tcl fallback %s\n",
618 getFallbackString( bit ));
619 transition_to_swtnl( ctx );
620 }
621 }
622 else {
623 rmesa->radeon.TclFallback &= ~bit;
624 if (oldfallback == bit) {
625 if (RADEON_DEBUG & DEBUG_FALLBACKS)
626 fprintf(stderr, "Radeon end tcl fallback %s\n",
627 getFallbackString( bit ));
628 transition_to_hwtnl( ctx );
629 }
630 }
631 }