1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 Tungsten Graphics Inc., Austin, Texas.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/light.h"
38 #include "main/mtypes.h"
39 #include "main/enums.h"
43 #include "tnl/t_pipeline.h"
45 #include "radeon_context.h"
46 #include "radeon_state.h"
47 #include "radeon_ioctl.h"
48 #include "radeon_tex.h"
49 #include "radeon_tcl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_maos.h"
56 * Render unclipped vertex buffers by emitting vertices directly to
57 * dma buffers. Use strip/fan hardware primitives where possible.
58 * Try to simulate missing primitives with indexed vertices.
62 #define HAVE_LINE_LOOP 0
63 #define HAVE_LINE_STRIPS 1
64 #define HAVE_TRIANGLES 1
65 #define HAVE_TRI_STRIPS 1
66 #define HAVE_TRI_STRIP_1 0
67 #define HAVE_TRI_FANS 1
69 #define HAVE_QUAD_STRIPS 0
70 #define HAVE_POLYGONS 1
74 #define HW_POINTS RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
75 #define HW_LINES RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
76 #define HW_LINE_LOOP 0
77 #define HW_LINE_STRIP RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
78 #define HW_TRIANGLES RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
79 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
80 #define HW_TRIANGLE_STRIP_1 0
81 #define HW_TRIANGLE_FAN RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
83 #define HW_QUAD_STRIP 0
84 #define HW_POLYGON RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
87 static GLboolean discrete_prim
[0x10] = {
95 1, /* 7 rect list (unused) */
96 1, /* 8 3vert point */
107 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
108 #define ELT_TYPE GLushort
110 #define ELT_INIT(prim, hw_prim) \
111 radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
113 #define GET_MESA_ELTS() rmesa->tcl.Elts
116 /* Don't really know how many elts will fit in what's left of cmdbuf,
117 * as there is state to emit, etc:
120 /* Testing on isosurf shows a maximum around here. Don't know if it's
121 * the card or driver or kernel module that is causing the behaviour.
123 #define GET_MAX_HW_ELTS() 300
126 #define RESET_STIPPLE() do { \
127 RADEON_STATECHANGE( rmesa, lin ); \
128 radeonEmitState( rmesa ); \
131 #define AUTO_STIPPLE( mode ) do { \
132 RADEON_STATECHANGE( rmesa, lin ); \
134 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
135 RADEON_LINE_PATTERN_AUTO_RESET; \
137 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
138 ~RADEON_LINE_PATTERN_AUTO_RESET; \
139 radeonEmitState( rmesa ); \
144 #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
146 static GLushort
*radeonAllocElts( r100ContextPtr rmesa
, GLuint nr
)
148 if (rmesa
->radeon
.dma
.flush
)
149 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
151 rcommonEnsureCmdBufSpace(&rmesa
->radeon
, AOS_BUFSZ(rmesa
->tcl
.nr_aos_components
) +
152 rmesa
->hw
.max_state_size
+ ELTS_BUFSZ(nr
));
154 radeonEmitAOS( rmesa
,
155 rmesa
->tcl
.aos_components
,
156 rmesa
->tcl
.nr_aos_components
, 0 );
158 return radeonAllocEltsOpenEnded( rmesa
,
159 rmesa
->tcl
.vertex_format
,
160 rmesa
->tcl
.hw_primitive
, nr
);
163 #define CLOSE_ELTS() RADEON_NEWPRIM( rmesa )
167 /* TODO: Try to extend existing primitive if both are identical,
168 * discrete and there are no intervening state changes. (Somewhat
169 * duplicates changes to DrawArrays code)
171 static void radeonEmitPrim( GLcontext
*ctx
,
177 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
178 radeonTclPrimitive( ctx
, prim
, hwprim
);
180 rcommonEnsureCmdBufSpace( &rmesa
->radeon
,
181 AOS_BUFSZ(rmesa
->tcl
.nr_aos_components
) +
182 rmesa
->hw
.max_state_size
+ VBUF_BUFSZ
);
184 radeonEmitAOS( rmesa
,
185 rmesa
->tcl
.aos_components
,
186 rmesa
->tcl
.nr_aos_components
,
189 /* Why couldn't this packet have taken an offset param?
191 radeonEmitVbufPrim( rmesa
,
193 rmesa
->tcl
.hw_primitive
,
197 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do { \
198 radeonEmitPrim( ctx, prim, hwprim, start, count ); \
199 (void) rmesa; } while (0)
201 /* Try & join small primitives
204 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
206 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \
209 rmesa->tcl.hw_primitive == (PRIM| \
210 RADEON_CP_VC_CNTL_PRIM_WALK_IND| \
211 RADEON_CP_VC_CNTL_TCL_ENABLE)))
214 #ifdef MESA_BIG_ENDIAN
215 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
216 #define EMIT_ELT(dest, offset, x) do { \
217 int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \
218 GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \
219 (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \
220 (void)rmesa; } while (0)
222 #define EMIT_ELT(dest, offset, x) do { \
223 (dest)[offset] = (GLushort) (x); \
224 (void)rmesa; } while (0)
227 #define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)(dest+offset) = ((y)<<16)|(x);
231 #define TAG(x) tcl_##x
232 #include "tnl_dd/t_dd_dmatmp2.h"
234 /**********************************************************************/
235 /* External entrypoints */
236 /**********************************************************************/
238 void radeonEmitPrimitive( GLcontext
*ctx
,
243 tcl_render_tab_verts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
246 void radeonEmitEltPrimitive( GLcontext
*ctx
,
251 tcl_render_tab_elts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
254 void radeonTclPrimitive( GLcontext
*ctx
,
258 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
260 GLuint newprim
= hw_prim
| RADEON_CP_VC_CNTL_TCL_ENABLE
;
262 if (newprim
!= rmesa
->tcl
.hw_primitive
||
263 !discrete_prim
[hw_prim
&0xf]) {
264 RADEON_NEWPRIM( rmesa
);
265 rmesa
->tcl
.hw_primitive
= newprim
;
268 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
269 se_cntl
&= ~RADEON_FLAT_SHADE_VTX_LAST
;
271 if (prim
== GL_POLYGON
&& (ctx
->_TriangleCaps
& DD_FLATSHADE
))
272 se_cntl
|= RADEON_FLAT_SHADE_VTX_0
;
274 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
276 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
277 RADEON_STATECHANGE( rmesa
, set
);
278 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
282 /**********************************************************************/
283 /* Fog blend factor computation for hw tcl */
284 /* same calculation used as in t_vb_fog.c */
285 /**********************************************************************/
287 #define FOG_EXP_TABLE_SIZE 256
288 #define FOG_MAX (10.0)
289 #define EXP_FOG_MAX .0006595
290 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
291 static GLfloat exp_table
[FOG_EXP_TABLE_SIZE
];
294 #define NEG_EXP( result, narg ) \
296 GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR)); \
297 GLint k = (GLint) f; \
298 if (k > FOG_EXP_TABLE_SIZE-2) \
299 result = (GLfloat) EXP_FOG_MAX; \
301 result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]); \
304 #define NEG_EXP( result, narg ) \
306 result = exp(-narg); \
312 * Initialize the exp_table[] lookup table for approximating exp().
315 radeonInitStaticFogData( void )
319 for ( ; i
< FOG_EXP_TABLE_SIZE
; i
++, f
+= FOG_INCR
) {
320 exp_table
[i
] = (GLfloat
) exp(-f
);
326 * Compute per-vertex fog blend factors from fog coordinates by
327 * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
328 * Fog coordinates are distances from the eye (typically between the
329 * near and far clip plane distances).
330 * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
331 * Fog blend factors are in the range [0,1].
334 radeonComputeFogBlendFactor( GLcontext
*ctx
, GLfloat fogcoord
)
336 GLfloat end
= ctx
->Fog
.End
;
338 const GLfloat z
= FABSF(fogcoord
);
340 switch (ctx
->Fog
.Mode
) {
342 if (ctx
->Fog
.Start
== ctx
->Fog
.End
)
345 d
= 1.0F
/ (ctx
->Fog
.End
- ctx
->Fog
.Start
);
346 temp
= (end
- z
) * d
;
347 return CLAMP(temp
, 0.0F
, 1.0F
);
350 d
= ctx
->Fog
.Density
;
351 NEG_EXP( temp
, d
* z
);
355 d
= ctx
->Fog
.Density
*ctx
->Fog
.Density
;
356 NEG_EXP( temp
, d
* z
* z
);
360 _mesa_problem(ctx
, "Bad fog mode in make_fog_coord");
365 /**********************************************************************/
366 /* Render pipeline stage */
367 /**********************************************************************/
372 static GLboolean
radeon_run_tcl_render( GLcontext
*ctx
,
373 struct tnl_pipeline_stage
*stage
)
375 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
376 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
377 struct vertex_buffer
*VB
= &tnl
->vb
;
378 GLuint inputs
= VERT_BIT_POS
| VERT_BIT_COLOR0
;
381 /* TODO: separate this from the swtnl pipeline
383 if (rmesa
->radeon
.TclFallback
)
384 return GL_TRUE
; /* fallback to software t&l */
389 /* NOTE: inputs != tnl->render_inputs - these are the untransformed
392 if (ctx
->Light
.Enabled
) {
393 inputs
|= VERT_BIT_NORMAL
;
396 if (ctx
->_TriangleCaps
& DD_SEPARATE_SPECULAR
) {
397 inputs
|= VERT_BIT_COLOR1
;
400 if ( (ctx
->Fog
.FogCoordinateSource
== GL_FOG_COORD
) && ctx
->Fog
.Enabled
) {
401 inputs
|= VERT_BIT_FOG
;
404 for (i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
405 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
406 /* TODO: probably should not emit texture coords when texgen is enabled */
407 if (rmesa
->TexGenNeedNormals
[i
]) {
408 inputs
|= VERT_BIT_NORMAL
;
410 inputs
|= VERT_BIT_TEX(i
);
414 radeonReleaseArrays( ctx
, ~0 );
415 radeonEmitArrays( ctx
, inputs
);
417 rmesa
->tcl
.Elts
= VB
->Elts
;
419 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
421 GLuint prim
= _tnl_translate_prim(&VB
->Primitive
[i
]);
422 GLuint start
= VB
->Primitive
[i
].start
;
423 GLuint length
= VB
->Primitive
[i
].count
;
429 radeonEmitEltPrimitive( ctx
, start
, start
+length
, prim
);
431 radeonEmitPrimitive( ctx
, start
, start
+length
, prim
);
434 return GL_FALSE
; /* finished the pipe */
439 /* Initial state for tcl stage.
441 const struct tnl_pipeline_stage _radeon_tcl_stage
=
448 radeon_run_tcl_render
/* run */
453 /**********************************************************************/
454 /* Validate state at pipeline start */
455 /**********************************************************************/
458 /*-----------------------------------------------------------------------
459 * Manage TCL fallbacks
463 static void transition_to_swtnl( GLcontext
*ctx
)
465 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
466 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
469 RADEON_NEWPRIM( rmesa
);
470 rmesa
->swtcl
.vertex_format
= 0;
472 radeonChooseVertexState( ctx
);
473 radeonChooseRenderState( ctx
);
475 _mesa_validate_all_lighting_tables( ctx
);
477 tnl
->Driver
.NotifyMaterialChange
=
478 _mesa_validate_all_lighting_tables
;
480 radeonReleaseArrays( ctx
, ~0 );
482 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
483 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
485 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
486 RADEON_STATECHANGE( rmesa
, set
);
487 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
492 static void transition_to_hwtnl( GLcontext
*ctx
)
494 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
495 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
496 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
498 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
499 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
500 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
501 se_coord_fmt
|= RADEON_VTX_W0_IS_NOT_1_OVER_W0
;
503 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
504 RADEON_STATECHANGE( rmesa
, set
);
505 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
506 _tnl_need_projected_coords( ctx
, GL_FALSE
);
509 radeonUpdateMaterial( ctx
);
511 tnl
->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
513 if ( rmesa
->radeon
.dma
.flush
)
514 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
516 rmesa
->radeon
.dma
.flush
= NULL
;
517 rmesa
->swtcl
.vertex_format
= 0;
519 // if (rmesa->swtcl.indexed_verts.buf)
520 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
523 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
524 fprintf(stderr
, "Radeon end tcl fallback\n");
527 static char *fallbackStrings
[] = {
528 "Rasterization fallback",
529 "Unfilled triangles",
530 "Twosided lighting, differing materials",
531 "Materials in VB (maybe between begin/end)",
536 "Fogcoord with separate specular lighting"
540 static char *getFallbackString(GLuint bit
)
547 return fallbackStrings
[i
];
552 void radeonTclFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
554 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
555 GLuint oldfallback
= rmesa
->radeon
.TclFallback
;
558 rmesa
->radeon
.TclFallback
|= bit
;
559 if (oldfallback
== 0) {
560 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
561 fprintf(stderr
, "Radeon begin tcl fallback %s\n",
562 getFallbackString( bit
));
563 transition_to_swtnl( ctx
);
567 rmesa
->radeon
.TclFallback
&= ~bit
;
568 if (oldfallback
== bit
) {
569 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
570 fprintf(stderr
, "Radeon end tcl fallback %s\n",
571 getFallbackString( bit
));
572 transition_to_hwtnl( ctx
);