src/mesa/drivers/dri/radeon/radeon_tcl.c

   1 /* $XFree86$ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc., Austin, Texas.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Keith Whitwell <keith@tungstengraphics.com>
  34  */
  35
  36 #include "glheader.h"
  37 #include "imports.h"
  38 #include "light.h"
  39 #include "mtypes.h"
  40 #include "enums.h"
  41
  42 #include "array_cache/acache.h"
  43 #include "tnl/tnl.h"
  44 #include "tnl/t_pipeline.h"
  45
  46 #include "radeon_context.h"
  47 #include "radeon_state.h"
  48 #include "radeon_ioctl.h"
  49 #include "radeon_tex.h"
  50 #include "radeon_tcl.h"
  51 #include "radeon_swtcl.h"
  52 #include "radeon_maos.h"
  53
  54
  55
  56 /*
  57  * Render unclipped vertex buffers by emitting vertices directly to
  58  * dma buffers.  Use strip/fan hardware primitives where possible.
  59  * Try to simulate missing primitives with indexed vertices.
  60  */
  61 #define HAVE_POINTS      1
  62 #define HAVE_LINES       1
  63 #define HAVE_LINE_LOOP   0
  64 #define HAVE_LINE_STRIPS 1
  65 #define HAVE_TRIANGLES   1
  66 #define HAVE_TRI_STRIPS  1
  67 #define HAVE_TRI_STRIP_1 0
  68 #define HAVE_TRI_FANS    1
  69 #define HAVE_QUADS       1
  70 #define HAVE_QUAD_STRIPS 0
  71 #define HAVE_POLYGONS    1
  72 #define HAVE_ELTS        1
  73
  74
  75 #define HW_POINTS           RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
  76 #define HW_LINES            RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
  77 #define HW_LINE_LOOP        0
  78 #define HW_LINE_STRIP       RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
  79 #define HW_TRIANGLES        RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
  80 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
  81 #define HW_TRIANGLE_STRIP_1 0
  82 #define HW_TRIANGLE_FAN     RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  83 #define HW_QUADS            0
  84 #define HW_QUAD_STRIP       0
  85 #define HW_POLYGON          RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  86
  87
  88 static GLboolean discrete_prim[0x10] = {
  89    0,                           /* 0 none */
  90    1,                           /* 1 points */
  91    1,                           /* 2 lines */
  92    0,                           /* 3 line_strip */
  93    1,                           /* 4 tri_list */
  94    0,                           /* 5 tri_fan */
  95    0,                           /* 6 tri_type2 */
  96    1,                           /* 7 rect list (unused) */
  97    1,                           /* 8 3vert point */
  98    1,                           /* 9 3vert line */
  99    0,
 100    0,
 101    0,
 102    0,
 103    0,
 104    0,
 105 };
 106
 107
 108 #define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx); (void)rmesa
 109 #define ELT_TYPE  GLushort
 110
 111 #define ELT_INIT(prim, hw_prim) \
 112    radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
 113
 114 #define GET_MESA_ELTS() rmesa->tcl.Elts
 115
 116
 117 /* Don't really know how many elts will fit in what's left of cmdbuf,
 118  * as there is state to emit, etc:
 119  */
 120
 121 /* Testing on isosurf shows a maximum around here.  Don't know if it's
 122  * the card or driver or kernel module that is causing the behaviour.
 123  */
 124 #define GET_MAX_HW_ELTS() 300
 125
 126
 127 #define RESET_STIPPLE() do {                    \
 128    RADEON_STATECHANGE( rmesa, lin );            \
 129    radeonEmitState( rmesa );                    \
 130 } while (0)
 131
 132 #define AUTO_STIPPLE( mode )  do {              \
 133    RADEON_STATECHANGE( rmesa, lin );            \
 134    if (mode)                                    \
 135       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
 136          RADEON_LINE_PATTERN_AUTO_RESET;        \
 137    else                                         \
 138       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
 139          ~RADEON_LINE_PATTERN_AUTO_RESET;       \
 140    radeonEmitState( rmesa );                    \
 141 } while (0)
 142
 143
 144
 145 #define ALLOC_ELTS(nr)  radeonAllocElts( rmesa, nr )
 146
 147 static GLushort *radeonAllocElts( radeonContextPtr rmesa, GLuint nr )
 148 {
 149    if (rmesa->dma.flush)
 150       rmesa->dma.flush( rmesa );
 151
 152    radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
 153                            rmesa->hw.max_state_size + ELTS_BUFSZ(nr));
 154
 155    radeonEmitAOS( rmesa,
 156                 rmesa->tcl.aos_components,
 157                 rmesa->tcl.nr_aos_components, 0 );
 158
 159    return radeonAllocEltsOpenEnded( rmesa,
 160                                     rmesa->tcl.vertex_format,
 161                                     rmesa->tcl.hw_primitive, nr );
 162 }
 163
 164 #define CLOSE_ELTS()  RADEON_NEWPRIM( rmesa )
 165
 166
 167
 168 /* TODO: Try to extend existing primitive if both are identical,
 169  * discrete and there are no intervening state changes.  (Somewhat
 170  * duplicates changes to DrawArrays code)
 171  */
 172 static void EMIT_PRIM( GLcontext *ctx,
 173                        GLenum prim,
 174                        GLuint hwprim,
 175                        GLuint start,
 176                        GLuint count)
 177 {
 178    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 179    radeonTclPrimitive( ctx, prim, hwprim );
 180
 181    radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
 182                             rmesa->hw.max_state_size + VBUF_BUFSZ );
 183
 184    radeonEmitAOS( rmesa,
 185                   rmesa->tcl.aos_components,
 186                   rmesa->tcl.nr_aos_components,
 187                   start );
 188
 189    /* Why couldn't this packet have taken an offset param?
 190     */
 191    radeonEmitVbufPrim( rmesa,
 192                        rmesa->tcl.vertex_format,
 193                        rmesa->tcl.hw_primitive,
 194                        count - start );
 195 }
 196
 197
 198
 199 /* Try & join small primitives
 200  */
 201 #if 0
 202 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
 203 #else
 204 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM )                    \
 205   ((NR) < 20 ||                                                 \
 206    ((NR) < 40 &&                                                \
 207     rmesa->tcl.hw_primitive == (PRIM|                           \
 208                             RADEON_CP_VC_CNTL_PRIM_WALK_IND|    \
 209                             RADEON_CP_VC_CNTL_TCL_ENABLE)))
 210 #endif
 211
 212 #ifdef MESA_BIG_ENDIAN
 213 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
 214 #define EMIT_ELT(dest, offset, x) do {                          \
 215         int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 );     \
 216         GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 );    \
 217         (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); } while (0)
 218 #else
 219 #define EMIT_ELT(dest, offset, x) (dest)[offset] = (GLushort) (x)
 220 #endif
 221
 222 #define EMIT_TWO_ELTS(dest, offset, x, y)  *(GLuint *)(dest+offset) = ((y)<<16)|(x);
 223
 224
 225
 226 #define TAG(x) tcl_##x
 227 #include "tnl_dd/t_dd_dmatmp2.h"
 228
 229 /**********************************************************************/
 230 /*                          External entrypoints                     */
 231 /**********************************************************************/
 232
 233 void radeonEmitPrimitive( GLcontext *ctx,
 234                           GLuint first,
 235                           GLuint last,
 236                           GLuint flags )
 237 {
 238    tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 239 }
 240
 241 void radeonEmitEltPrimitive( GLcontext *ctx,
 242                              GLuint first,
 243                              GLuint last,
 244                              GLuint flags )
 245 {
 246    tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 247 }
 248
 249 void radeonTclPrimitive( GLcontext *ctx,
 250                          GLenum prim,
 251                          int hw_prim )
 252 {
 253    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 254    GLuint se_cntl;
 255    GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
 256
 257    if (newprim != rmesa->tcl.hw_primitive ||
 258        !discrete_prim[hw_prim&0xf]) {
 259       RADEON_NEWPRIM( rmesa );
 260       rmesa->tcl.hw_primitive = newprim;
 261    }
 262
 263    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 264    se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST;
 265
 266    if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE))
 267       se_cntl |= RADEON_FLAT_SHADE_VTX_0;
 268    else
 269       se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 270
 271    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 272       RADEON_STATECHANGE( rmesa, set );
 273       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 274    }
 275 }
 276
 277
 278 /**********************************************************************/
 279 /*                          Render pipeline stage                     */
 280 /**********************************************************************/
 281
 282
 283 /* TCL render.
 284  */
 285 static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 286                                         struct tnl_pipeline_stage *stage )
 287 {
 288    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 289    TNLcontext *tnl = TNL_CONTEXT(ctx);
 290    struct vertex_buffer *VB = &tnl->vb;
 291    GLuint i;
 292
 293    /* TODO: separate this from the swtnl pipeline
 294     */
 295    if (rmesa->TclFallback)
 296       return GL_TRUE;   /* fallback to software t&l */
 297
 298    if (VB->Count == 0)
 299       return GL_FALSE;
 300
 301    radeonReleaseArrays( ctx, stage->changed_inputs );
 302    radeonEmitArrays( ctx, stage->inputs );
 303
 304    rmesa->tcl.Elts = VB->Elts;
 305
 306    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 307    {
 308       GLuint prim = VB->Primitive[i].mode;
 309       GLuint start = VB->Primitive[i].start;
 310       GLuint length = VB->Primitive[i].count;
 311
 312       if (!length)
 313          continue;
 314
 315       if (rmesa->tcl.Elts)
 316          radeonEmitEltPrimitive( ctx, start, start+length, prim );
 317       else
 318          radeonEmitPrimitive( ctx, start, start+length, prim );
 319    }
 320
 321    return GL_FALSE;             /* finished the pipe */
 322 }
 323
 324
 325
 326 static void radeon_check_tcl_render( GLcontext *ctx,
 327                                      struct tnl_pipeline_stage *stage )
 328 {
 329    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 330    GLuint inputs = VERT_BIT_POS;
 331
 332    if (ctx->RenderMode == GL_RENDER) {
 333       /* Make all this event-driven:
 334        */
 335       if (ctx->Light.Enabled) {
 336          inputs |= VERT_BIT_NORMAL;
 337
 338          if (1 || ctx->Light.ColorMaterialEnabled) {
 339             inputs |= VERT_BIT_COLOR0;
 340          }
 341       }
 342       else {
 343          inputs |= VERT_BIT_COLOR0;
 344
 345          if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
 346             inputs |= VERT_BIT_COLOR1;
 347          }
 348       }
 349
 350       if (ctx->Texture.Unit[0]._ReallyEnabled) {
 351          if (ctx->Texture.Unit[0].TexGenEnabled) {
 352             if (rmesa->TexGenNeedNormals[0]) {
 353                inputs |= VERT_BIT_NORMAL;
 354             }
 355          } else {
 356             inputs |= VERT_BIT_TEX0;
 357          }
 358       }
 359
 360       if (ctx->Texture.Unit[1]._ReallyEnabled) {
 361          if (ctx->Texture.Unit[1].TexGenEnabled) {
 362             if (rmesa->TexGenNeedNormals[1]) {
 363                inputs |= VERT_BIT_NORMAL;
 364             }
 365          } else {
 366             inputs |= VERT_BIT_TEX1;
 367          }
 368       }
 369
 370       stage->inputs = inputs;
 371       stage->active = 1;
 372    }
 373    else
 374       stage->active = 0;
 375 }
 376
 377 static void radeon_init_tcl_render( GLcontext *ctx,
 378                                     struct tnl_pipeline_stage *stage )
 379 {
 380    stage->check = radeon_check_tcl_render;
 381    stage->check( ctx, stage );
 382 }
 383
 384 static void dtr( struct tnl_pipeline_stage *stage )
 385 {
 386    (void)stage;
 387 }
 388
 389
 390 /* Initial state for tcl stage.
 391  */
 392 const struct tnl_pipeline_stage _radeon_tcl_stage =
 393 {
 394    "radeon render",
 395    (_DD_NEW_SEPARATE_SPECULAR |
 396     _NEW_LIGHT|
 397     _NEW_TEXTURE|
 398     _NEW_FOG|
 399     _NEW_RENDERMODE),           /* re-check (new inputs) */
 400    0,                           /* re-run (always runs) */
 401    GL_TRUE,                     /* active */
 402    0, 0,                        /* inputs (set in check_render), outputs */
 403    0, 0,                        /* changed_inputs, private */
 404    dtr,                         /* destructor */
 405    radeon_init_tcl_render,      /* check - initially set to alloc data */
 406    radeon_run_tcl_render        /* run */
 407 };
 408
 409
 410
 411 /**********************************************************************/
 412 /*                 Validate state at pipeline start                   */
 413 /**********************************************************************/
 414
 415
 416 /*-----------------------------------------------------------------------
 417  * Manage TCL fallbacks
 418  */
 419
 420
 421 static void transition_to_swtnl( GLcontext *ctx )
 422 {
 423    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 424    TNLcontext *tnl = TNL_CONTEXT(ctx);
 425    GLuint se_cntl;
 426
 427    RADEON_NEWPRIM( rmesa );
 428    rmesa->swtcl.vertex_format = 0;
 429
 430    radeonChooseVertexState( ctx );
 431    radeonChooseRenderState( ctx );
 432
 433    _mesa_validate_all_lighting_tables( ctx );
 434
 435    tnl->Driver.NotifyMaterialChange =
 436       _mesa_validate_all_lighting_tables;
 437
 438    radeonReleaseArrays( ctx, ~0 );
 439
 440    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 441    se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 442
 443    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 444       RADEON_STATECHANGE( rmesa, set );
 445       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 446    }
 447 }
 448
 449
 450 static void transition_to_hwtnl( GLcontext *ctx )
 451 {
 452    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 453    TNLcontext *tnl = TNL_CONTEXT(ctx);
 454    GLuint se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
 455                           RADEON_TEX1_W_ROUTING_USE_Q1);
 456
 457    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 458       RADEON_STATECHANGE( rmesa, set );
 459       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 460       _tnl_need_projected_coords( ctx, GL_FALSE );
 461    }
 462
 463    radeonUpdateMaterial( ctx );
 464
 465    tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
 466
 467    if ( rmesa->dma.flush )
 468       rmesa->dma.flush( rmesa );
 469
 470    rmesa->dma.flush = 0;
 471    rmesa->swtcl.vertex_format = 0;
 472
 473    if (rmesa->swtcl.indexed_verts.buf)
 474       radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 475                               __FUNCTION__ );
 476
 477    if (RADEON_DEBUG & DEBUG_FALLBACKS)
 478       fprintf(stderr, "Radeon end tcl fallback\n");
 479 }
 480
 481 static char *fallbackStrings[] = {
 482    "Rasterization fallback",
 483    "Unfilled triangles",
 484    "Twosided lighting, differing materials",
 485    "Materials in VB (maybe between begin/end)",
 486    "Texgen unit 0",
 487    "Texgen unit 1",
 488    "Texgen unit 2",
 489    "User disable"
 490 };
 491
 492
 493 static char *getFallbackString(GLuint bit)
 494 {
 495    int i = 0;
 496    while (bit > 1) {
 497       i++;
 498       bit >>= 1;
 499    }
 500    return fallbackStrings[i];
 501 }
 502
 503
 504
 505 void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 506 {
 507    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 508    GLuint oldfallback = rmesa->TclFallback;
 509
 510    if (mode) {
 511       rmesa->TclFallback |= bit;
 512       if (oldfallback == 0) {
 513          if (RADEON_DEBUG & DEBUG_FALLBACKS)
 514             fprintf(stderr, "Radeon begin tcl fallback %s\n",
 515                     getFallbackString( bit ));
 516          transition_to_swtnl( ctx );
 517       }
 518    }
 519    else {
 520       rmesa->TclFallback &= ~bit;
 521       if (oldfallback == bit) {
 522          if (RADEON_DEBUG & DEBUG_FALLBACKS)
 523             fprintf(stderr, "Radeon end tcl fallback %s\n",
 524                     getFallbackString( bit ));
 525          transition_to_hwtnl( ctx );
 526       }
 527    }
 528 }