1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 Tungsten Graphics Inc., Austin, Texas.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/light.h"
38 #include "main/mtypes.h"
39 #include "main/enums.h"
43 #include "tnl/t_pipeline.h"
45 #include "radeon_common.h"
46 #include "radeon_context.h"
47 #include "radeon_state.h"
48 #include "radeon_ioctl.h"
49 #include "radeon_tex.h"
50 #include "radeon_tcl.h"
51 #include "radeon_swtcl.h"
52 #include "radeon_maos.h"
53 #include "radeon_common_context.h"
58 * Render unclipped vertex buffers by emitting vertices directly to
59 * dma buffers. Use strip/fan hardware primitives where possible.
60 * Try to simulate missing primitives with indexed vertices.
64 #define HAVE_LINE_LOOP 0
65 #define HAVE_LINE_STRIPS 1
66 #define HAVE_TRIANGLES 1
67 #define HAVE_TRI_STRIPS 1
68 #define HAVE_TRI_STRIP_1 0
69 #define HAVE_TRI_FANS 1
71 #define HAVE_QUAD_STRIPS 0
72 #define HAVE_POLYGONS 1
76 #define HW_POINTS RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
77 #define HW_LINES RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
78 #define HW_LINE_LOOP 0
79 #define HW_LINE_STRIP RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
80 #define HW_TRIANGLES RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
81 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
82 #define HW_TRIANGLE_STRIP_1 0
83 #define HW_TRIANGLE_FAN RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
85 #define HW_QUAD_STRIP 0
86 #define HW_POLYGON RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
89 static GLboolean discrete_prim
[0x10] = {
97 1, /* 7 rect list (unused) */
98 1, /* 8 3vert point */
109 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
110 #define ELT_TYPE GLushort
112 #define ELT_INIT(prim, hw_prim) \
113 radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
115 #define GET_MESA_ELTS() rmesa->tcl.Elts
118 /* Don't really know how many elts will fit in what's left of cmdbuf,
119 * as there is state to emit, etc:
122 /* Testing on isosurf shows a maximum around here. Don't know if it's
123 * the card or driver or kernel module that is causing the behaviour.
125 #define GET_MAX_HW_ELTS() 300
128 #define RESET_STIPPLE() do { \
129 RADEON_STATECHANGE( rmesa, lin ); \
130 radeonEmitState(&rmesa->radeon); \
133 #define AUTO_STIPPLE( mode ) do { \
134 RADEON_STATECHANGE( rmesa, lin ); \
136 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
137 RADEON_LINE_PATTERN_AUTO_RESET; \
139 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
140 ~RADEON_LINE_PATTERN_AUTO_RESET; \
141 radeonEmitState(&rmesa->radeon); \
146 #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
148 static GLushort
*radeonAllocElts( r100ContextPtr rmesa
, GLuint nr
)
150 if (rmesa
->radeon
.dma
.flush
)
151 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
153 radeonEmitAOS( rmesa
,
154 rmesa
->radeon
.tcl
.aos_count
, 0 );
156 return radeonAllocEltsOpenEnded( rmesa
, rmesa
->tcl
.vertex_format
,
157 rmesa
->tcl
.hw_primitive
, nr
);
160 #define CLOSE_ELTS() if (0) RADEON_NEWPRIM( rmesa )
164 /* TODO: Try to extend existing primitive if both are identical,
165 * discrete and there are no intervening state changes. (Somewhat
166 * duplicates changes to DrawArrays code)
168 static void radeonEmitPrim( GLcontext
*ctx
,
174 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
175 radeonTclPrimitive( ctx
, prim
, hwprim
);
177 radeonEmitAOS( rmesa
,
178 rmesa
->radeon
.tcl
.aos_count
,
181 /* Why couldn't this packet have taken an offset param?
183 radeonEmitVbufPrim( rmesa
,
184 rmesa
->tcl
.vertex_format
,
185 rmesa
->tcl
.hw_primitive
,
189 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do { \
190 radeonEmitPrim( ctx, prim, hwprim, start, count ); \
191 (void) rmesa; } while (0)
193 #define MAX_CONVERSION_SIZE 40
195 /* Try & join small primitives
198 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
200 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \
203 rmesa->tcl.hw_primitive == (PRIM| \
204 RADEON_CP_VC_CNTL_PRIM_WALK_IND| \
205 RADEON_CP_VC_CNTL_TCL_ENABLE)))
208 #ifdef MESA_BIG_ENDIAN
209 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
210 #define EMIT_ELT(dest, offset, x) do { \
211 int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \
212 GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \
213 (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \
214 (void)rmesa; } while (0)
216 #define EMIT_ELT(dest, offset, x) do { \
217 (dest)[offset] = (GLushort) (x); \
218 (void)rmesa; } while (0)
221 #define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)(dest+offset) = ((y)<<16)|(x);
225 #define TAG(x) tcl_##x
226 #include "tnl_dd/t_dd_dmatmp2.h"
228 /**********************************************************************/
229 /* External entrypoints */
230 /**********************************************************************/
232 void radeonEmitPrimitive( GLcontext
*ctx
,
237 tcl_render_tab_verts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
240 void radeonEmitEltPrimitive( GLcontext
*ctx
,
245 tcl_render_tab_elts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
248 void radeonTclPrimitive( GLcontext
*ctx
,
252 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
254 GLuint newprim
= hw_prim
| RADEON_CP_VC_CNTL_TCL_ENABLE
;
256 if (newprim
!= rmesa
->tcl
.hw_primitive
||
257 !discrete_prim
[hw_prim
&0xf]) {
258 RADEON_NEWPRIM( rmesa
);
259 rmesa
->tcl
.hw_primitive
= newprim
;
262 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
263 se_cntl
&= ~RADEON_FLAT_SHADE_VTX_LAST
;
265 if (prim
== GL_POLYGON
&& (ctx
->_TriangleCaps
& DD_FLATSHADE
))
266 se_cntl
|= RADEON_FLAT_SHADE_VTX_0
;
268 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
270 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
271 RADEON_STATECHANGE( rmesa
, set
);
272 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
276 /**********************************************************************/
277 /* Fog blend factor computation for hw tcl */
278 /* same calculation used as in t_vb_fog.c */
279 /**********************************************************************/
281 #define FOG_EXP_TABLE_SIZE 256
282 #define FOG_MAX (10.0)
283 #define EXP_FOG_MAX .0006595
284 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
285 static GLfloat exp_table
[FOG_EXP_TABLE_SIZE
];
288 #define NEG_EXP( result, narg ) \
290 GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR)); \
291 GLint k = (GLint) f; \
292 if (k > FOG_EXP_TABLE_SIZE-2) \
293 result = (GLfloat) EXP_FOG_MAX; \
295 result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]); \
298 #define NEG_EXP( result, narg ) \
300 result = exp(-narg); \
306 * Initialize the exp_table[] lookup table for approximating exp().
309 radeonInitStaticFogData( void )
313 for ( ; i
< FOG_EXP_TABLE_SIZE
; i
++, f
+= FOG_INCR
) {
314 exp_table
[i
] = (GLfloat
) exp(-f
);
320 * Compute per-vertex fog blend factors from fog coordinates by
321 * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
322 * Fog coordinates are distances from the eye (typically between the
323 * near and far clip plane distances).
324 * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
325 * Fog blend factors are in the range [0,1].
328 radeonComputeFogBlendFactor( GLcontext
*ctx
, GLfloat fogcoord
)
330 GLfloat end
= ctx
->Fog
.End
;
332 const GLfloat z
= FABSF(fogcoord
);
334 switch (ctx
->Fog
.Mode
) {
336 if (ctx
->Fog
.Start
== ctx
->Fog
.End
)
339 d
= 1.0F
/ (ctx
->Fog
.End
- ctx
->Fog
.Start
);
340 temp
= (end
- z
) * d
;
341 return CLAMP(temp
, 0.0F
, 1.0F
);
344 d
= ctx
->Fog
.Density
;
345 NEG_EXP( temp
, d
* z
);
349 d
= ctx
->Fog
.Density
*ctx
->Fog
.Density
;
350 NEG_EXP( temp
, d
* z
* z
);
354 _mesa_problem(ctx
, "Bad fog mode in make_fog_coord");
360 * Predict total emit size for next rendering operation so there is no flush in middle of rendering
361 * Prediction has to aim towards the best possible value that is worse than worst case scenario
363 static GLuint
radeonEnsureEmitSize( GLcontext
* ctx
, GLuint inputs
)
365 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
366 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
367 struct vertex_buffer
*VB
= &tnl
->vb
;
368 GLuint space_required
;
370 GLuint nr_aos
= 1; /* radeonEmitArrays does always emit one */
372 /* list of flags that are allocating aos object */
373 const GLuint flags_to_check
[] = {
379 /* predict number of aos to emit */
380 for (i
=0; i
< sizeof(flags_to_check
)/sizeof(flags_to_check
[0]); ++i
)
382 if (inputs
& flags_to_check
[i
])
385 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; ++i
)
387 if (inputs
& VERT_BIT_TEX(i
))
392 /* count the prediction for state size */
394 state_size
= radeonCountStateEmitSize( &rmesa
->radeon
);
395 /* tcl may be changed in radeonEmitArrays so account for it if not dirty */
396 if (!rmesa
->hw
.tcl
.dirty
)
397 state_size
+= rmesa
->hw
.tcl
.check( rmesa
->radeon
.glCtx
, &rmesa
->hw
.tcl
);
398 /* predict size for elements */
399 for (i
= 0; i
< VB
->PrimitiveCount
; ++i
)
401 if (!VB
->Primitive
[i
].count
)
403 /* If primitive.count is less than MAX_CONVERSION_SIZE
404 rendering code may decide convert to elts.
405 In that case we have to make pessimistic prediction.
406 and use larger of 2 paths. */
407 const GLuint elts
= ELTS_BUFSZ(nr_aos
);
408 const GLuint index
= INDEX_BUFSZ
;
409 const GLuint vbuf
= VBUF_BUFSZ
;
410 if ( (!VB
->Elts
&& VB
->Primitive
[i
].count
>= MAX_CONVERSION_SIZE
)
411 || vbuf
> index
+ elts
)
412 space_required
+= vbuf
;
414 space_required
+= index
+ elts
;
415 space_required
+= VB
->Primitive
[i
].count
* 3;
416 space_required
+= AOS_BUFSZ(nr_aos
);
418 space_required
+= SCISSOR_BUFSZ
;
420 /* flush the buffer in case we need more than is left. */
421 if (rcommonEnsureCmdBufSpace(&rmesa
->radeon
, space_required
, __FUNCTION__
))
422 return space_required
+ radeonCountStateEmitSize( &rmesa
->radeon
);
424 return space_required
+ state_size
;
427 /**********************************************************************/
428 /* Render pipeline stage */
429 /**********************************************************************/
434 static GLboolean
radeon_run_tcl_render( GLcontext
*ctx
,
435 struct tnl_pipeline_stage
*stage
)
437 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
438 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
439 struct vertex_buffer
*VB
= &tnl
->vb
;
440 GLuint inputs
= VERT_BIT_POS
| VERT_BIT_COLOR0
;
443 /* TODO: separate this from the swtnl pipeline
445 if (rmesa
->radeon
.TclFallback
)
446 return GL_TRUE
; /* fallback to software t&l */
451 /* NOTE: inputs != tnl->render_inputs - these are the untransformed
454 if (ctx
->Light
.Enabled
) {
455 inputs
|= VERT_BIT_NORMAL
;
458 if (ctx
->_TriangleCaps
& DD_SEPARATE_SPECULAR
) {
459 inputs
|= VERT_BIT_COLOR1
;
462 if ( (ctx
->Fog
.FogCoordinateSource
== GL_FOG_COORD
) && ctx
->Fog
.Enabled
) {
463 inputs
|= VERT_BIT_FOG
;
466 for (i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
467 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
468 /* TODO: probably should not emit texture coords when texgen is enabled */
469 if (rmesa
->TexGenNeedNormals
[i
]) {
470 inputs
|= VERT_BIT_NORMAL
;
472 inputs
|= VERT_BIT_TEX(i
);
476 radeonReleaseArrays( ctx
, ~0 );
477 GLuint emit_end
= radeonEnsureEmitSize( ctx
, inputs
)
478 + rmesa
->radeon
.cmdbuf
.cs
->cdw
;
479 radeonEmitArrays( ctx
, inputs
);
481 rmesa
->tcl
.Elts
= VB
->Elts
;
483 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
485 GLuint prim
= _tnl_translate_prim(&VB
->Primitive
[i
]);
486 GLuint start
= VB
->Primitive
[i
].start
;
487 GLuint length
= VB
->Primitive
[i
].count
;
493 radeonEmitEltPrimitive( ctx
, start
, start
+length
, prim
);
495 radeonEmitPrimitive( ctx
, start
, start
+length
, prim
);
498 if (emit_end
< rmesa
->radeon
.cmdbuf
.cs
->cdw
)
499 WARN_ONCE("Rendering was %d commands larger than predicted size."
500 " We might overflow command buffer.\n", rmesa
->radeon
.cmdbuf
.cs
->cdw
- emit_end
);
502 return GL_FALSE
; /* finished the pipe */
507 /* Initial state for tcl stage.
509 const struct tnl_pipeline_stage _radeon_tcl_stage
=
516 radeon_run_tcl_render
/* run */
521 /**********************************************************************/
522 /* Validate state at pipeline start */
523 /**********************************************************************/
526 /*-----------------------------------------------------------------------
527 * Manage TCL fallbacks
531 static void transition_to_swtnl( GLcontext
*ctx
)
533 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
534 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
537 RADEON_NEWPRIM( rmesa
);
538 rmesa
->swtcl
.vertex_format
= 0;
540 radeonChooseVertexState( ctx
);
541 radeonChooseRenderState( ctx
);
543 _mesa_validate_all_lighting_tables( ctx
);
545 tnl
->Driver
.NotifyMaterialChange
=
546 _mesa_validate_all_lighting_tables
;
548 radeonReleaseArrays( ctx
, ~0 );
550 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
551 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
553 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
554 RADEON_STATECHANGE( rmesa
, set
);
555 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
560 static void transition_to_hwtnl( GLcontext
*ctx
)
562 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
563 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
564 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
566 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
567 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
568 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
569 se_coord_fmt
|= RADEON_VTX_W0_IS_NOT_1_OVER_W0
;
571 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
572 RADEON_STATECHANGE( rmesa
, set
);
573 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
574 _tnl_need_projected_coords( ctx
, GL_FALSE
);
577 radeonUpdateMaterial( ctx
);
579 tnl
->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
581 if ( rmesa
->radeon
.dma
.flush
)
582 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
584 rmesa
->radeon
.dma
.flush
= NULL
;
585 rmesa
->swtcl
.vertex_format
= 0;
587 // if (rmesa->swtcl.indexed_verts.buf)
588 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
591 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
592 fprintf(stderr
, "Radeon end tcl fallback\n");
595 static char *fallbackStrings
[] = {
596 "Rasterization fallback",
597 "Unfilled triangles",
598 "Twosided lighting, differing materials",
599 "Materials in VB (maybe between begin/end)",
604 "Fogcoord with separate specular lighting"
608 static char *getFallbackString(GLuint bit
)
615 return fallbackStrings
[i
];
620 void radeonTclFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
622 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
623 GLuint oldfallback
= rmesa
->radeon
.TclFallback
;
626 rmesa
->radeon
.TclFallback
|= bit
;
627 if (oldfallback
== 0) {
628 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
629 fprintf(stderr
, "Radeon begin tcl fallback %s\n",
630 getFallbackString( bit
));
631 transition_to_swtnl( ctx
);
635 rmesa
->radeon
.TclFallback
&= ~bit
;
636 if (oldfallback
== bit
) {
637 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
638 fprintf(stderr
, "Radeon end tcl fallback %s\n",
639 getFallbackString( bit
));
640 transition_to_hwtnl( ctx
);