src/mesa/drivers/dri/radeon/radeon_tcl.c

   1 /* $XFree86$ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc., Austin, Texas.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Keith Whitwell <keith@tungstengraphics.com>
  34  */
  35
  36 #include "glheader.h"
  37 #include "imports.h"
  38 #include "light.h"
  39 #include "mtypes.h"
  40 #include "enums.h"
  41
  42 #include "array_cache/acache.h"
  43 #include "tnl/tnl.h"
  44 #include "tnl/t_pipeline.h"
  45
  46 #include "radeon_context.h"
  47 #include "radeon_state.h"
  48 #include "radeon_ioctl.h"
  49 #include "radeon_tex.h"
  50 #include "radeon_tcl.h"
  51 #include "radeon_swtcl.h"
  52 #include "radeon_maos.h"
  53
  54
  55
  56 /*
  57  * Render unclipped vertex buffers by emitting vertices directly to
  58  * dma buffers.  Use strip/fan hardware primitives where possible.
  59  * Try to simulate missing primitives with indexed vertices.
  60  */
  61 #define HAVE_POINTS      1
  62 #define HAVE_LINES       1
  63 #define HAVE_LINE_LOOP   0
  64 #define HAVE_LINE_STRIPS 1
  65 #define HAVE_TRIANGLES   1
  66 #define HAVE_TRI_STRIPS  1
  67 #define HAVE_TRI_STRIP_1 0
  68 #define HAVE_TRI_FANS    1
  69 #define HAVE_QUADS       0
  70 #define HAVE_QUAD_STRIPS 0
  71 #define HAVE_POLYGONS    1
  72 #define HAVE_ELTS        1
  73
  74
  75 #define HW_POINTS           RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
  76 #define HW_LINES            RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
  77 #define HW_LINE_LOOP        0
  78 #define HW_LINE_STRIP       RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
  79 #define HW_TRIANGLES        RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
  80 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
  81 #define HW_TRIANGLE_STRIP_1 0
  82 #define HW_TRIANGLE_FAN     RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  83 #define HW_QUADS            0
  84 #define HW_QUAD_STRIP       0
  85 #define HW_POLYGON          RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  86
  87
  88 static GLboolean discrete_prim[0x10] = {
  89    0,                           /* 0 none */
  90    1,                           /* 1 points */
  91    1,                           /* 2 lines */
  92    0,                           /* 3 line_strip */
  93    1,                           /* 4 tri_list */
  94    0,                           /* 5 tri_fan */
  95    0,                           /* 6 tri_type2 */
  96    1,                           /* 7 rect list (unused) */
  97    1,                           /* 8 3vert point */
  98    1,                           /* 9 3vert line */
  99    0,
 100    0,
 101    0,
 102    0,
 103    0,
 104    0,
 105 };
 106
 107
 108 #define LOCAL_VARS radeonContextPtr rmesa = RADEON_CONTEXT(ctx)
 109 #define ELT_TYPE  GLushort
 110
 111 #define ELT_INIT(prim, hw_prim) \
 112    radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
 113
 114 #define GET_MESA_ELTS() rmesa->tcl.Elts
 115
 116
 117 /* Don't really know how many elts will fit in what's left of cmdbuf,
 118  * as there is state to emit, etc:
 119  */
 120
 121 /* Testing on isosurf shows a maximum around here.  Don't know if it's
 122  * the card or driver or kernel module that is causing the behaviour.
 123  */
 124 #define GET_MAX_HW_ELTS() 300
 125
 126
 127 #define RESET_STIPPLE() do {                    \
 128    RADEON_STATECHANGE( rmesa, lin );            \
 129    radeonEmitState( rmesa );                    \
 130 } while (0)
 131
 132 #define AUTO_STIPPLE( mode )  do {              \
 133    RADEON_STATECHANGE( rmesa, lin );            \
 134    if (mode)                                    \
 135       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
 136          RADEON_LINE_PATTERN_AUTO_RESET;        \
 137    else                                         \
 138       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
 139          ~RADEON_LINE_PATTERN_AUTO_RESET;       \
 140    radeonEmitState( rmesa );                    \
 141 } while (0)
 142
 143
 144
 145 #define ALLOC_ELTS(nr)  radeonAllocElts( rmesa, nr )
 146
 147 static GLushort *radeonAllocElts( radeonContextPtr rmesa, GLuint nr )
 148 {
 149    if (rmesa->dma.flush)
 150       rmesa->dma.flush( rmesa );
 151
 152    radeonEmitAOS( rmesa,
 153                 rmesa->tcl.aos_components,
 154                 rmesa->tcl.nr_aos_components, 0 );
 155
 156    return radeonAllocEltsOpenEnded( rmesa,
 157                                     rmesa->tcl.vertex_format,
 158                                     rmesa->tcl.hw_primitive, nr );
 159 }
 160
 161 #define CLOSE_ELTS()  RADEON_NEWPRIM( rmesa )
 162
 163
 164
 165 /* TODO: Try to extend existing primitive if both are identical,
 166  * discrete and there are no intervening state changes.  (Somewhat
 167  * duplicates changes to DrawArrays code)
 168  */
 169 static void EMIT_PRIM( GLcontext *ctx,
 170                        GLenum prim,
 171                        GLuint hwprim,
 172                        GLuint start,
 173                        GLuint count)
 174 {
 175    radeonContextPtr rmesa = RADEON_CONTEXT( ctx );
 176    radeonTclPrimitive( ctx, prim, hwprim );
 177
 178    radeonEmitAOS( rmesa,
 179                   rmesa->tcl.aos_components,
 180                   rmesa->tcl.nr_aos_components,
 181                   start );
 182
 183    /* Why couldn't this packet have taken an offset param?
 184     */
 185    radeonEmitVbufPrim( rmesa,
 186                        rmesa->tcl.vertex_format,
 187                        rmesa->tcl.hw_primitive,
 188                        count - start );
 189 }
 190
 191
 192
 193 /* Try & join small primitives
 194  */
 195 #if 0
 196 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
 197 #else
 198 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM )                    \
 199   ((NR) < 20 ||                                                 \
 200    ((NR) < 40 &&                                                \
 201     rmesa->tcl.hw_primitive == (PRIM|                           \
 202                             RADEON_CP_VC_CNTL_PRIM_WALK_IND|    \
 203                             RADEON_CP_VC_CNTL_TCL_ENABLE)))
 204 #endif
 205
 206 #ifdef MESA_BIG_ENDIAN
 207 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
 208 #define EMIT_ELT(dest, offset, x) do {                          \
 209         int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 );     \
 210         GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 );    \
 211         (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); } while (0)
 212 #else
 213 #define EMIT_ELT(dest, offset, x) (dest)[offset] = (GLushort) (x)
 214 #endif
 215
 216 #define EMIT_TWO_ELTS(dest, offset, x, y)  *(GLuint *)(dest+offset) = ((y)<<16)|(x);
 217
 218
 219
 220 #define TAG(x) tcl_##x
 221 #include "tnl_dd/t_dd_dmatmp2.h"
 222
 223 /**********************************************************************/
 224 /*                          External entrypoints                     */
 225 /**********************************************************************/
 226
 227 void radeonEmitPrimitive( GLcontext *ctx,
 228                           GLuint first,
 229                           GLuint last,
 230                           GLuint flags )
 231 {
 232    tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 233 }
 234
 235 void radeonEmitEltPrimitive( GLcontext *ctx,
 236                              GLuint first,
 237                              GLuint last,
 238                              GLuint flags )
 239 {
 240    tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 241 }
 242
 243 void radeonTclPrimitive( GLcontext *ctx,
 244                          GLenum prim,
 245                          int hw_prim )
 246 {
 247    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 248    GLuint se_cntl;
 249    GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
 250
 251    if (newprim != rmesa->tcl.hw_primitive ||
 252        !discrete_prim[hw_prim&0xf]) {
 253       RADEON_NEWPRIM( rmesa );
 254       rmesa->tcl.hw_primitive = newprim;
 255    }
 256
 257    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 258    se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST;
 259
 260    if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE))
 261       se_cntl |= RADEON_FLAT_SHADE_VTX_0;
 262    else
 263       se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 264
 265    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 266       RADEON_STATECHANGE( rmesa, set );
 267       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 268    }
 269 }
 270
 271
 272 /**********************************************************************/
 273 /*                          Render pipeline stage                     */
 274 /**********************************************************************/
 275
 276
 277 /* TCL render.
 278  */
 279 static GLboolean radeon_run_tcl_render( GLcontext *ctx,
 280                                         struct tnl_pipeline_stage *stage )
 281 {
 282    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 283    TNLcontext *tnl = TNL_CONTEXT(ctx);
 284    struct vertex_buffer *VB = &tnl->vb;
 285    GLuint i,flags = 0,length;
 286
 287    /* TODO: separate this from the swtnl pipeline
 288     */
 289    if (rmesa->TclFallback)
 290       return GL_TRUE;   /* fallback to software t&l */
 291
 292    if (VB->Count == 0)
 293       return GL_FALSE;
 294
 295    radeonReleaseArrays( ctx, stage->changed_inputs );
 296    radeonEmitArrays( ctx, stage->inputs );
 297
 298    rmesa->tcl.Elts = VB->Elts;
 299
 300    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 301    {
 302       GLuint prim = VB->Primitive[i].mode;
 303       GLuint start = VB->Primitive[i].start;
 304       GLuint length = VB->Primitive[i].count;
 305
 306       if (!length)
 307          continue;
 308
 309       if (rmesa->tcl.Elts)
 310          radeonEmitEltPrimitive( ctx, start, start+length, prim );
 311       else
 312          radeonEmitPrimitive( ctx, start, start+length, prim );
 313    }
 314
 315    return GL_FALSE;             /* finished the pipe */
 316 }
 317
 318
 319
 320 static void radeon_check_tcl_render( GLcontext *ctx,
 321                                      struct tnl_pipeline_stage *stage )
 322 {
 323    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 324    GLuint inputs = VERT_BIT_POS;
 325
 326    if (ctx->RenderMode == GL_RENDER) {
 327       /* Make all this event-driven:
 328        */
 329       if (ctx->Light.Enabled) {
 330          inputs |= VERT_BIT_NORMAL;
 331
 332          if (1 || ctx->Light.ColorMaterialEnabled) {
 333             inputs |= VERT_BIT_COLOR0;
 334          }
 335       }
 336       else {
 337          inputs |= VERT_BIT_COLOR0;
 338
 339          if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
 340             inputs |= VERT_BIT_COLOR1;
 341          }
 342       }
 343
 344       if (ctx->Texture.Unit[0]._ReallyEnabled) {
 345          if (ctx->Texture.Unit[0].TexGenEnabled) {
 346             if (rmesa->TexGenNeedNormals[0]) {
 347                inputs |= VERT_BIT_NORMAL;
 348             }
 349          } else {
 350             inputs |= VERT_BIT_TEX0;
 351          }
 352       }
 353
 354       if (ctx->Texture.Unit[1]._ReallyEnabled) {
 355          if (ctx->Texture.Unit[1].TexGenEnabled) {
 356             if (rmesa->TexGenNeedNormals[1]) {
 357                inputs |= VERT_BIT_NORMAL;
 358             }
 359          } else {
 360             inputs |= VERT_BIT_TEX1;
 361          }
 362       }
 363
 364       stage->inputs = inputs;
 365       stage->active = 1;
 366    }
 367    else
 368       stage->active = 0;
 369 }
 370
 371 static void radeon_init_tcl_render( GLcontext *ctx,
 372                                     struct tnl_pipeline_stage *stage )
 373 {
 374    stage->check = radeon_check_tcl_render;
 375    stage->check( ctx, stage );
 376 }
 377
 378 static void dtr( struct tnl_pipeline_stage *stage )
 379 {
 380    (void)stage;
 381 }
 382
 383
 384 /* Initial state for tcl stage.
 385  */
 386 const struct tnl_pipeline_stage _radeon_tcl_stage =
 387 {
 388    "radeon render",
 389    (_DD_NEW_SEPARATE_SPECULAR |
 390     _NEW_LIGHT|
 391     _NEW_TEXTURE|
 392     _NEW_FOG|
 393     _NEW_RENDERMODE),           /* re-check (new inputs) */
 394    0,                           /* re-run (always runs) */
 395    GL_TRUE,                     /* active */
 396    0, 0,                        /* inputs (set in check_render), outputs */
 397    0, 0,                        /* changed_inputs, private */
 398    dtr,                         /* destructor */
 399    radeon_init_tcl_render,      /* check - initially set to alloc data */
 400    radeon_run_tcl_render        /* run */
 401 };
 402
 403
 404
 405 /**********************************************************************/
 406 /*                 Validate state at pipeline start                   */
 407 /**********************************************************************/
 408
 409
 410 /*-----------------------------------------------------------------------
 411  * Manage TCL fallbacks
 412  */
 413
 414
 415 static void transition_to_swtnl( GLcontext *ctx )
 416 {
 417    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 418    TNLcontext *tnl = TNL_CONTEXT(ctx);
 419    GLuint se_cntl;
 420
 421    RADEON_NEWPRIM( rmesa );
 422    rmesa->swtcl.vertex_format = 0;
 423
 424    radeonChooseVertexState( ctx );
 425    radeonChooseRenderState( ctx );
 426
 427    _mesa_validate_all_lighting_tables( ctx );
 428
 429    tnl->Driver.NotifyMaterialChange =
 430       _mesa_validate_all_lighting_tables;
 431
 432    radeonReleaseArrays( ctx, ~0 );
 433
 434    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 435    se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 436
 437    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 438       RADEON_STATECHANGE( rmesa, set );
 439       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 440    }
 441 }
 442
 443
 444 static void transition_to_hwtnl( GLcontext *ctx )
 445 {
 446    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 447    TNLcontext *tnl = TNL_CONTEXT(ctx);
 448    GLuint se_coord_fmt = (RADEON_VTX_W0_IS_NOT_1_OVER_W0 |
 449                           RADEON_TEX1_W_ROUTING_USE_Q1);
 450
 451    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 452       RADEON_STATECHANGE( rmesa, set );
 453       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 454       _tnl_need_projected_coords( ctx, GL_FALSE );
 455    }
 456
 457    radeonUpdateMaterial( ctx );
 458
 459    tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
 460
 461    if ( rmesa->dma.flush )
 462       rmesa->dma.flush( rmesa );
 463
 464    rmesa->dma.flush = 0;
 465    rmesa->swtcl.vertex_format = 0;
 466
 467    if (rmesa->swtcl.indexed_verts.buf)
 468       radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 469                               __FUNCTION__ );
 470
 471    if (RADEON_DEBUG & DEBUG_FALLBACKS)
 472       fprintf(stderr, "Radeon end tcl fallback\n");
 473 }
 474
 475 static char *fallbackStrings[] = {
 476    "Rasterization fallback",
 477    "Unfilled triangles",
 478    "Twosided lighting, differing materials",
 479    "Materials in VB (maybe between begin/end)",
 480    "Texgen unit 0",
 481    "Texgen unit 1",
 482    "Texgen unit 2",
 483    "User disable"
 484 };
 485
 486
 487 static char *getFallbackString(GLuint bit)
 488 {
 489    int i = 0;
 490    while (bit > 1) {
 491       i++;
 492       bit >>= 1;
 493    }
 494    return fallbackStrings[i];
 495 }
 496
 497
 498
 499 void radeonTclFallback( GLcontext *ctx, GLuint bit, GLboolean mode )
 500 {
 501    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 502    GLuint oldfallback = rmesa->TclFallback;
 503
 504    if (mode) {
 505       rmesa->TclFallback |= bit;
 506       if (oldfallback == 0) {
 507          if (RADEON_DEBUG & DEBUG_FALLBACKS)
 508             fprintf(stderr, "Radeon begin tcl fallback %s\n",
 509                     getFallbackString( bit ));
 510          transition_to_swtnl( ctx );
 511       }
 512    }
 513    else {
 514       rmesa->TclFallback &= ~bit;
 515       if (oldfallback == bit) {
 516          if (RADEON_DEBUG & DEBUG_FALLBACKS)
 517             fprintf(stderr, "Radeon end tcl fallback %s\n",
 518                     getFallbackString( bit ));
 519          transition_to_hwtnl( ctx );
 520       }
 521    }
 522 }