src/mesa/drivers/dri/radeon/radeon_tcl.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      Tungsten Graphics Inc., Austin, Texas.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation the rights to use, copy, modify, merge, publish,
  12 distribute, sublicense, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27
  28 **************************************************************************/
  29
  30 /*
  31  * Authors:
  32  *   Keith Whitwell <keith@tungstengraphics.com>
  33  */
  34
  35 #include "main/glheader.h"
  36 #include "main/imports.h"
  37 #include "main/light.h"
  38 #include "main/mtypes.h"
  39 #include "main/enums.h"
  40
  41 #include "vbo/vbo.h"
  42 #include "tnl/tnl.h"
  43 #include "tnl/t_pipeline.h"
  44
  45 #include "radeon_common.h"
  46 #include "radeon_context.h"
  47 #include "radeon_state.h"
  48 #include "radeon_ioctl.h"
  49 #include "radeon_tcl.h"
  50 #include "radeon_swtcl.h"
  51 #include "radeon_maos.h"
  52 #include "radeon_common_context.h"
  53
  54
  55
  56 /*
  57  * Render unclipped vertex buffers by emitting vertices directly to
  58  * dma buffers.  Use strip/fan hardware primitives where possible.
  59  * Try to simulate missing primitives with indexed vertices.
  60  */
  61 #define HAVE_POINTS      1
  62 #define HAVE_LINES       1
  63 #define HAVE_LINE_LOOP   0
  64 #define HAVE_LINE_STRIPS 1
  65 #define HAVE_TRIANGLES   1
  66 #define HAVE_TRI_STRIPS  1
  67 #define HAVE_TRI_STRIP_1 0
  68 #define HAVE_TRI_FANS    1
  69 #define HAVE_QUADS       0
  70 #define HAVE_QUAD_STRIPS 0
  71 #define HAVE_POLYGONS    1
  72 #define HAVE_ELTS        1
  73
  74
  75 #define HW_POINTS           RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
  76 #define HW_LINES            RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
  77 #define HW_LINE_LOOP        0
  78 #define HW_LINE_STRIP       RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
  79 #define HW_TRIANGLES        RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
  80 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
  81 #define HW_TRIANGLE_STRIP_1 0
  82 #define HW_TRIANGLE_FAN     RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  83 #define HW_QUADS            0
  84 #define HW_QUAD_STRIP       0
  85 #define HW_POLYGON          RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
  86
  87
  88 static GLboolean discrete_prim[0x10] = {
  89    0,                           /* 0 none */
  90    1,                           /* 1 points */
  91    1,                           /* 2 lines */
  92    0,                           /* 3 line_strip */
  93    1,                           /* 4 tri_list */
  94    0,                           /* 5 tri_fan */
  95    0,                           /* 6 tri_type2 */
  96    1,                           /* 7 rect list (unused) */
  97    1,                           /* 8 3vert point */
  98    1,                           /* 9 3vert line */
  99    0,
 100    0,
 101    0,
 102    0,
 103    0,
 104    0,
 105 };
 106
 107
 108 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
 109 #define ELT_TYPE  GLushort
 110
 111 #define ELT_INIT(prim, hw_prim) \
 112    radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
 113
 114 #define GET_MESA_ELTS() rmesa->tcl.Elts
 115
 116
 117 /* Don't really know how many elts will fit in what's left of cmdbuf,
 118  * as there is state to emit, etc:
 119  */
 120
 121 /* Testing on isosurf shows a maximum around here.  Don't know if it's
 122  * the card or driver or kernel module that is causing the behaviour.
 123  */
 124 #define GET_MAX_HW_ELTS() 300
 125
 126
 127 #define RESET_STIPPLE() do {                    \
 128    RADEON_STATECHANGE( rmesa, lin );            \
 129    radeonEmitState(&rmesa->radeon);                     \
 130 } while (0)
 131
 132 #define AUTO_STIPPLE( mode )  do {              \
 133    RADEON_STATECHANGE( rmesa, lin );            \
 134    if (mode)                                    \
 135       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
 136          RADEON_LINE_PATTERN_AUTO_RESET;        \
 137    else                                         \
 138       rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
 139          ~RADEON_LINE_PATTERN_AUTO_RESET;       \
 140    radeonEmitState(&rmesa->radeon);             \
 141 } while (0)
 142
 143
 144
 145 #define ALLOC_ELTS(nr)  radeonAllocElts( rmesa, nr )
 146
 147 static GLushort *radeonAllocElts( r100ContextPtr rmesa, GLuint nr )
 148 {
 149       if (rmesa->radeon.dma.flush)
 150          rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 151
 152       radeonEmitAOS( rmesa,
 153                      rmesa->radeon.tcl.aos_count, 0 );
 154
 155       return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
 156                                        rmesa->tcl.hw_primitive, nr );
 157 }
 158
 159 #define CLOSE_ELTS() if (0)  RADEON_NEWPRIM( rmesa )
 160
 161
 162
 163 /* TODO: Try to extend existing primitive if both are identical,
 164  * discrete and there are no intervening state changes.  (Somewhat
 165  * duplicates changes to DrawArrays code)
 166  */
 167 static void radeonEmitPrim( struct gl_context *ctx,
 168                        GLenum prim,
 169                        GLuint hwprim,
 170                        GLuint start,
 171                        GLuint count)
 172 {
 173    r100ContextPtr rmesa = R100_CONTEXT( ctx );
 174    radeonTclPrimitive( ctx, prim, hwprim );
 175
 176    radeonEmitAOS( rmesa,
 177                   rmesa->radeon.tcl.aos_count,
 178                   start );
 179
 180    /* Why couldn't this packet have taken an offset param?
 181     */
 182    radeonEmitVbufPrim( rmesa,
 183                        rmesa->tcl.vertex_format,
 184                        rmesa->tcl.hw_primitive,
 185                        count - start );
 186 }
 187
 188 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do {       \
 189    radeonEmitPrim( ctx, prim, hwprim, start, count );           \
 190    (void) rmesa; } while (0)
 191
 192 #define MAX_CONVERSION_SIZE 40
 193
 194 /* Try & join small primitives
 195  */
 196 #if 0
 197 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
 198 #else
 199 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM )                    \
 200   ((NR) < 20 ||                                                 \
 201    ((NR) < 40 &&                                                \
 202     rmesa->tcl.hw_primitive == (PRIM|                           \
 203                             RADEON_CP_VC_CNTL_PRIM_WALK_IND|    \
 204                             RADEON_CP_VC_CNTL_TCL_ENABLE)))
 205 #endif
 206
 207 #ifdef MESA_BIG_ENDIAN
 208 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
 209 #define EMIT_ELT(dest, offset, x) do {                          \
 210         int off = offset + ( ( (uintptr_t)dest & 0x2 ) >> 1 );  \
 211         GLushort *des = (GLushort *)( (uintptr_t)dest & ~0x2 ); \
 212         (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x);     \
 213         (void)rmesa; } while (0)
 214 #else
 215 #define EMIT_ELT(dest, offset, x) do {                          \
 216         (dest)[offset] = (GLushort) (x);                        \
 217         (void)rmesa; } while (0)
 218 #endif
 219
 220 #define EMIT_TWO_ELTS(dest, offset, x, y)  *(GLuint *)(dest+offset) = ((y)<<16)|(x);
 221
 222
 223
 224 #define TAG(x) tcl_##x
 225 #include "tnl_dd/t_dd_dmatmp2.h"
 226
 227 /**********************************************************************/
 228 /*                          External entrypoints                     */
 229 /**********************************************************************/
 230
 231 void radeonEmitPrimitive( struct gl_context *ctx,
 232                           GLuint first,
 233                           GLuint last,
 234                           GLuint flags )
 235 {
 236    tcl_render_tab_verts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 237 }
 238
 239 void radeonEmitEltPrimitive( struct gl_context *ctx,
 240                              GLuint first,
 241                              GLuint last,
 242                              GLuint flags )
 243 {
 244    tcl_render_tab_elts[flags&PRIM_MODE_MASK]( ctx, first, last, flags );
 245 }
 246
 247 void radeonTclPrimitive( struct gl_context *ctx,
 248                          GLenum prim,
 249                          int hw_prim )
 250 {
 251    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 252    GLuint se_cntl;
 253    GLuint newprim = hw_prim | RADEON_CP_VC_CNTL_TCL_ENABLE;
 254
 255    radeon_prepare_render(&rmesa->radeon);
 256    if (rmesa->radeon.NewGLState)
 257       radeonValidateState( ctx );
 258
 259    if (newprim != rmesa->tcl.hw_primitive ||
 260        !discrete_prim[hw_prim&0xf]) {
 261       RADEON_NEWPRIM( rmesa );
 262       rmesa->tcl.hw_primitive = newprim;
 263    }
 264
 265    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 266    se_cntl &= ~RADEON_FLAT_SHADE_VTX_LAST;
 267
 268    if (prim == GL_POLYGON && (ctx->_TriangleCaps & DD_FLATSHADE))
 269       se_cntl |= RADEON_FLAT_SHADE_VTX_0;
 270    else
 271       se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 272
 273    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 274       RADEON_STATECHANGE( rmesa, set );
 275       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 276    }
 277 }
 278
 279 /**********************************************************************/
 280 /*             Fog blend factor computation for hw tcl                */
 281 /*             same calculation used as in t_vb_fog.c                 */
 282 /**********************************************************************/
 283
 284 #define FOG_EXP_TABLE_SIZE 256
 285 #define FOG_MAX (10.0)
 286 #define EXP_FOG_MAX .0006595
 287 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
 288 static GLfloat exp_table[FOG_EXP_TABLE_SIZE];
 289
 290 #if 1
 291 #define NEG_EXP( result, narg )                                         \
 292 do {                                                                    \
 293    GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR));                       \
 294    GLint k = (GLint) f;                                                 \
 295    if (k > FOG_EXP_TABLE_SIZE-2)                                        \
 296       result = (GLfloat) EXP_FOG_MAX;                                   \
 297    else                                                                 \
 298       result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]);      \
 299 } while (0)
 300 #else
 301 #define NEG_EXP( result, narg )                                 \
 302 do {                                                            \
 303    result = exp(-narg);                                         \
 304 } while (0)
 305 #endif
 306
 307
 308 /**
 309  * Initialize the exp_table[] lookup table for approximating exp().
 310  */
 311 void
 312 radeonInitStaticFogData( void )
 313 {
 314    GLfloat f = 0.0F;
 315    GLint i = 0;
 316    for ( ; i < FOG_EXP_TABLE_SIZE ; i++, f += FOG_INCR) {
 317       exp_table[i] = (GLfloat) exp(-f);
 318    }
 319 }
 320
 321
 322 /**
 323  * Compute per-vertex fog blend factors from fog coordinates by
 324  * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
 325  * Fog coordinates are distances from the eye (typically between the
 326  * near and far clip plane distances).
 327  * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
 328  * Fog blend factors are in the range [0,1].
 329  */
 330 float
 331 radeonComputeFogBlendFactor( struct gl_context *ctx, GLfloat fogcoord )
 332 {
 333    GLfloat end  = ctx->Fog.End;
 334    GLfloat d, temp;
 335    const GLfloat z = FABSF(fogcoord);
 336
 337    switch (ctx->Fog.Mode) {
 338    case GL_LINEAR:
 339       if (ctx->Fog.Start == ctx->Fog.End)
 340          d = 1.0F;
 341       else
 342          d = 1.0F / (ctx->Fog.End - ctx->Fog.Start);
 343       temp = (end - z) * d;
 344       return CLAMP(temp, 0.0F, 1.0F);
 345       break;
 346    case GL_EXP:
 347       d = ctx->Fog.Density;
 348       NEG_EXP( temp, d * z );
 349       return temp;
 350       break;
 351    case GL_EXP2:
 352       d = ctx->Fog.Density*ctx->Fog.Density;
 353       NEG_EXP( temp, d * z * z );
 354       return temp;
 355       break;
 356    default:
 357       _mesa_problem(ctx, "Bad fog mode in make_fog_coord");
 358       return 0;
 359    }
 360 }
 361
 362 /**
 363  * Predict total emit size for next rendering operation so there is no flush in middle of rendering
 364  * Prediction has to aim towards the best possible value that is worse than worst case scenario
 365  */
 366 static GLuint radeonEnsureEmitSize( struct gl_context * ctx , GLuint inputs )
 367 {
 368   r100ContextPtr rmesa = R100_CONTEXT(ctx);
 369   TNLcontext *tnl = TNL_CONTEXT(ctx);
 370   struct vertex_buffer *VB = &tnl->vb;
 371   GLuint space_required;
 372   GLuint state_size;
 373   GLuint nr_aos = 1; /* radeonEmitArrays does always emit one */
 374   int i;
 375   /* list of flags that are allocating aos object */
 376   const GLuint flags_to_check[] = {
 377     VERT_BIT_NORMAL,
 378     VERT_BIT_COLOR0,
 379     VERT_BIT_COLOR1,
 380     VERT_BIT_FOG
 381   };
 382   /* predict number of aos to emit */
 383   for (i=0; i < sizeof(flags_to_check)/sizeof(flags_to_check[0]); ++i)
 384   {
 385     if (inputs & flags_to_check[i])
 386       ++nr_aos;
 387   }
 388   for (i = 0; i < ctx->Const.MaxTextureUnits; ++i)
 389   {
 390     if (inputs & VERT_BIT_TEX(i))
 391       ++nr_aos;
 392   }
 393
 394   {
 395     /* count the prediction for state size */
 396     space_required = 0;
 397     state_size = radeonCountStateEmitSize( &rmesa->radeon );
 398     /* tcl may be changed in radeonEmitArrays so account for it if not dirty */
 399     if (!rmesa->hw.tcl.dirty)
 400       state_size += rmesa->hw.tcl.check( rmesa->radeon.glCtx, &rmesa->hw.tcl );
 401     /* predict size for elements */
 402     for (i = 0; i < VB->PrimitiveCount; ++i)
 403     {
 404       if (!VB->Primitive[i].count)
 405         continue;
 406       /* If primitive.count is less than MAX_CONVERSION_SIZE
 407          rendering code may decide convert to elts.
 408          In that case we have to make pessimistic prediction.
 409          and use larger of 2 paths. */
 410       const GLuint elts = ELTS_BUFSZ(nr_aos);
 411       const GLuint index = INDEX_BUFSZ;
 412       const GLuint vbuf = VBUF_BUFSZ;
 413       if ( (!VB->Elts && VB->Primitive[i].count >= MAX_CONVERSION_SIZE)
 414           || vbuf > index + elts)
 415         space_required += vbuf;
 416       else
 417         space_required += index + elts;
 418       space_required += VB->Primitive[i].count * 3;
 419       space_required += AOS_BUFSZ(nr_aos);
 420     }
 421     space_required += SCISSOR_BUFSZ;
 422   }
 423   /* flush the buffer in case we need more than is left. */
 424   if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required, __FUNCTION__))
 425     return space_required + radeonCountStateEmitSize( &rmesa->radeon );
 426   else
 427     return space_required + state_size;
 428 }
 429
 430 /**********************************************************************/
 431 /*                          Render pipeline stage                     */
 432 /**********************************************************************/
 433
 434
 435 /* TCL render.
 436  */
 437 static GLboolean radeon_run_tcl_render( struct gl_context *ctx,
 438                                         struct tnl_pipeline_stage *stage )
 439 {
 440    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 441    TNLcontext *tnl = TNL_CONTEXT(ctx);
 442    struct vertex_buffer *VB = &tnl->vb;
 443    GLuint inputs = VERT_BIT_POS | VERT_BIT_COLOR0;
 444    GLuint i;
 445
 446    /* TODO: separate this from the swtnl pipeline
 447     */
 448    if (rmesa->radeon.TclFallback)
 449       return GL_TRUE;   /* fallback to software t&l */
 450
 451    if (VB->Count == 0)
 452       return GL_FALSE;
 453
 454    /* NOTE: inputs != tnl->render_inputs - these are the untransformed
 455     * inputs.
 456     */
 457    if (ctx->Light.Enabled) {
 458       inputs |= VERT_BIT_NORMAL;
 459    }
 460
 461    if (ctx->_TriangleCaps & DD_SEPARATE_SPECULAR) {
 462       inputs |= VERT_BIT_COLOR1;
 463    }
 464
 465    if ( (ctx->Fog.FogCoordinateSource == GL_FOG_COORD) && ctx->Fog.Enabled ) {
 466       inputs |= VERT_BIT_FOG;
 467    }
 468
 469    for (i = 0 ; i < ctx->Const.MaxTextureUnits; i++) {
 470       if (ctx->Texture.Unit[i]._ReallyEnabled) {
 471       /* TODO: probably should not emit texture coords when texgen is enabled */
 472          if (rmesa->TexGenNeedNormals[i]) {
 473             inputs |= VERT_BIT_NORMAL;
 474          }
 475          inputs |= VERT_BIT_TEX(i);
 476       }
 477    }
 478
 479    radeonReleaseArrays( ctx, ~0 );
 480    GLuint emit_end = radeonEnsureEmitSize( ctx, inputs )
 481      + rmesa->radeon.cmdbuf.cs->cdw;
 482    radeonEmitArrays( ctx, inputs );
 483
 484    rmesa->tcl.Elts = VB->Elts;
 485
 486    for (i = 0 ; i < VB->PrimitiveCount ; i++)
 487    {
 488       GLuint prim = _tnl_translate_prim(&VB->Primitive[i]);
 489       GLuint start = VB->Primitive[i].start;
 490       GLuint length = VB->Primitive[i].count;
 491
 492       if (!length)
 493          continue;
 494
 495       if (rmesa->tcl.Elts)
 496          radeonEmitEltPrimitive( ctx, start, start+length, prim );
 497       else
 498          radeonEmitPrimitive( ctx, start, start+length, prim );
 499    }
 500
 501    if (emit_end < rmesa->radeon.cmdbuf.cs->cdw)
 502       WARN_ONCE("Rendering was %d commands larger than predicted size."
 503           " We might overflow  command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end);
 504
 505    return GL_FALSE;             /* finished the pipe */
 506 }
 507
 508
 509
 510 /* Initial state for tcl stage.
 511  */
 512 const struct tnl_pipeline_stage _radeon_tcl_stage =
 513 {
 514    "radeon render",
 515    NULL,
 516    NULL,
 517    NULL,
 518    NULL,
 519    radeon_run_tcl_render        /* run */
 520 };
 521
 522
 523
 524 /**********************************************************************/
 525 /*                 Validate state at pipeline start                   */
 526 /**********************************************************************/
 527
 528
 529 /*-----------------------------------------------------------------------
 530  * Manage TCL fallbacks
 531  */
 532
 533
 534 static void transition_to_swtnl( struct gl_context *ctx )
 535 {
 536    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 537    TNLcontext *tnl = TNL_CONTEXT(ctx);
 538    GLuint se_cntl;
 539
 540    RADEON_NEWPRIM( rmesa );
 541    rmesa->swtcl.vertex_format = 0;
 542
 543    radeonChooseVertexState( ctx );
 544    radeonChooseRenderState( ctx );
 545
 546    _mesa_validate_all_lighting_tables( ctx );
 547
 548    tnl->Driver.NotifyMaterialChange =
 549       _mesa_validate_all_lighting_tables;
 550
 551    radeonReleaseArrays( ctx, ~0 );
 552
 553    se_cntl = rmesa->hw.set.cmd[SET_SE_CNTL];
 554    se_cntl |= RADEON_FLAT_SHADE_VTX_LAST;
 555
 556    if (se_cntl != rmesa->hw.set.cmd[SET_SE_CNTL]) {
 557       RADEON_STATECHANGE( rmesa, set );
 558       rmesa->hw.set.cmd[SET_SE_CNTL] = se_cntl;
 559    }
 560 }
 561
 562
 563 static void transition_to_hwtnl( struct gl_context *ctx )
 564 {
 565    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 566    TNLcontext *tnl = TNL_CONTEXT(ctx);
 567    GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
 568
 569    se_coord_fmt &= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0 |
 570                      RADEON_VTX_Z_PRE_MULT_1_OVER_W0 |
 571                      RADEON_VTX_W0_IS_NOT_1_OVER_W0);
 572    se_coord_fmt |= RADEON_VTX_W0_IS_NOT_1_OVER_W0;
 573
 574    if ( se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT] ) {
 575       RADEON_STATECHANGE( rmesa, set );
 576       rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
 577       _tnl_need_projected_coords( ctx, GL_FALSE );
 578    }
 579
 580    radeonUpdateMaterial( ctx );
 581
 582    tnl->Driver.NotifyMaterialChange = radeonUpdateMaterial;
 583
 584    if ( rmesa->radeon.dma.flush )
 585       rmesa->radeon.dma.flush( rmesa->radeon.glCtx );
 586
 587    rmesa->radeon.dma.flush = NULL;
 588    rmesa->swtcl.vertex_format = 0;
 589
 590    //   if (rmesa->swtcl.indexed_verts.buf)
 591    //      radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
 592    //                         __FUNCTION__ );
 593
 594    if (RADEON_DEBUG & RADEON_FALLBACKS)
 595       fprintf(stderr, "Radeon end tcl fallback\n");
 596 }
 597
 598 static char *fallbackStrings[] = {
 599    "Rasterization fallback",
 600    "Unfilled triangles",
 601    "Twosided lighting, differing materials",
 602    "Materials in VB (maybe between begin/end)",
 603    "Texgen unit 0",
 604    "Texgen unit 1",
 605    "Texgen unit 2",
 606    "User disable",
 607    "Fogcoord with separate specular lighting"
 608 };
 609
 610
 611 static char *getFallbackString(GLuint bit)
 612 {
 613    int i = 0;
 614    while (bit > 1) {
 615       i++;
 616       bit >>= 1;
 617    }
 618    return fallbackStrings[i];
 619 }
 620
 621
 622
 623 void radeonTclFallback( struct gl_context *ctx, GLuint bit, GLboolean mode )
 624 {
 625    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 626    GLuint oldfallback = rmesa->radeon.TclFallback;
 627
 628    if (mode) {
 629       rmesa->radeon.TclFallback |= bit;
 630       if (oldfallback == 0) {
 631          if (RADEON_DEBUG & RADEON_FALLBACKS)
 632             fprintf(stderr, "Radeon begin tcl fallback %s\n",
 633                     getFallbackString( bit ));
 634          transition_to_swtnl( ctx );
 635       }
 636    }
 637    else {
 638       rmesa->radeon.TclFallback &= ~bit;
 639       if (oldfallback == bit) {
 640          if (RADEON_DEBUG & RADEON_FALLBACKS)
 641             fprintf(stderr, "Radeon end tcl fallback %s\n",
 642                     getFallbackString( bit ));
 643          transition_to_hwtnl( ctx );
 644       }
 645    }
 646 }