1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 Tungsten Graphics Inc., Austin, Texas.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/light.h"
38 #include "main/mtypes.h"
39 #include "main/enums.h"
43 #include "tnl/t_pipeline.h"
45 #include "radeon_common.h"
46 #include "radeon_context.h"
47 #include "radeon_state.h"
48 #include "radeon_ioctl.h"
49 #include "radeon_tex.h"
50 #include "radeon_tcl.h"
51 #include "radeon_swtcl.h"
52 #include "radeon_maos.h"
57 * Render unclipped vertex buffers by emitting vertices directly to
58 * dma buffers. Use strip/fan hardware primitives where possible.
59 * Try to simulate missing primitives with indexed vertices.
63 #define HAVE_LINE_LOOP 0
64 #define HAVE_LINE_STRIPS 1
65 #define HAVE_TRIANGLES 1
66 #define HAVE_TRI_STRIPS 1
67 #define HAVE_TRI_STRIP_1 0
68 #define HAVE_TRI_FANS 1
70 #define HAVE_QUAD_STRIPS 0
71 #define HAVE_POLYGONS 1
75 #define HW_POINTS RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
76 #define HW_LINES RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
77 #define HW_LINE_LOOP 0
78 #define HW_LINE_STRIP RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
79 #define HW_TRIANGLES RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
80 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
81 #define HW_TRIANGLE_STRIP_1 0
82 #define HW_TRIANGLE_FAN RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
84 #define HW_QUAD_STRIP 0
85 #define HW_POLYGON RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
88 static GLboolean discrete_prim
[0x10] = {
96 1, /* 7 rect list (unused) */
97 1, /* 8 3vert point */
108 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
109 #define ELT_TYPE GLushort
111 #define ELT_INIT(prim, hw_prim) \
112 radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
114 #define GET_MESA_ELTS() rmesa->tcl.Elts
117 /* Don't really know how many elts will fit in what's left of cmdbuf,
118 * as there is state to emit, etc:
121 /* Testing on isosurf shows a maximum around here. Don't know if it's
122 * the card or driver or kernel module that is causing the behaviour.
124 #define GET_MAX_HW_ELTS() 300
127 #define RESET_STIPPLE() do { \
128 RADEON_STATECHANGE( rmesa, lin ); \
129 radeonEmitState(&rmesa->radeon); \
132 #define AUTO_STIPPLE( mode ) do { \
133 RADEON_STATECHANGE( rmesa, lin ); \
135 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
136 RADEON_LINE_PATTERN_AUTO_RESET; \
138 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
139 ~RADEON_LINE_PATTERN_AUTO_RESET; \
140 radeonEmitState(&rmesa->radeon); \
145 #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
147 static GLushort
*radeonAllocElts( r100ContextPtr rmesa
, GLuint nr
)
149 if (rmesa
->radeon
.dma
.flush
)
150 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
152 rcommonEnsureCmdBufSpace(&rmesa
->radeon
, rmesa
->radeon
.hw
.max_state_size
+ ELTS_BUFSZ(nr
) +
153 AOS_BUFSZ(rmesa
->radeon
.tcl
.aos_count
), __FUNCTION__
);
155 radeonEmitAOS( rmesa
,
156 rmesa
->radeon
.tcl
.aos_count
, 0 );
158 return radeonAllocEltsOpenEnded( rmesa
, rmesa
->tcl
.vertex_format
,
159 rmesa
->tcl
.hw_primitive
, nr
);
162 #define CLOSE_ELTS() if (0) RADEON_NEWPRIM( rmesa )
166 /* TODO: Try to extend existing primitive if both are identical,
167 * discrete and there are no intervening state changes. (Somewhat
168 * duplicates changes to DrawArrays code)
170 static void radeonEmitPrim( GLcontext
*ctx
,
176 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
177 radeonTclPrimitive( ctx
, prim
, hwprim
);
179 rcommonEnsureCmdBufSpace( &rmesa
->radeon
,
180 AOS_BUFSZ(rmesa
->radeon
.tcl
.aos_count
) +
181 rmesa
->radeon
.hw
.max_state_size
+ VBUF_BUFSZ
, __FUNCTION__
);
183 radeonEmitAOS( rmesa
,
184 rmesa
->radeon
.tcl
.aos_count
,
187 /* Why couldn't this packet have taken an offset param?
189 radeonEmitVbufPrim( rmesa
,
190 rmesa
->tcl
.vertex_format
,
191 rmesa
->tcl
.hw_primitive
,
195 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do { \
196 radeonEmitPrim( ctx, prim, hwprim, start, count ); \
197 (void) rmesa; } while (0)
199 /* Try & join small primitives
202 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
204 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \
207 rmesa->tcl.hw_primitive == (PRIM| \
208 RADEON_CP_VC_CNTL_PRIM_WALK_IND| \
209 RADEON_CP_VC_CNTL_TCL_ENABLE)))
212 #ifdef MESA_BIG_ENDIAN
213 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
214 #define EMIT_ELT(dest, offset, x) do { \
215 int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \
216 GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \
217 (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \
218 (void)rmesa; } while (0)
220 #define EMIT_ELT(dest, offset, x) do { \
221 (dest)[offset] = (GLushort) (x); \
222 (void)rmesa; } while (0)
225 #define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)(dest+offset) = ((y)<<16)|(x);
229 #define TAG(x) tcl_##x
230 #include "tnl_dd/t_dd_dmatmp2.h"
232 /**********************************************************************/
233 /* External entrypoints */
234 /**********************************************************************/
236 void radeonEmitPrimitive( GLcontext
*ctx
,
241 tcl_render_tab_verts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
244 void radeonEmitEltPrimitive( GLcontext
*ctx
,
249 tcl_render_tab_elts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
252 void radeonTclPrimitive( GLcontext
*ctx
,
256 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
258 GLuint newprim
= hw_prim
| RADEON_CP_VC_CNTL_TCL_ENABLE
;
260 if (newprim
!= rmesa
->tcl
.hw_primitive
||
261 !discrete_prim
[hw_prim
&0xf]) {
262 RADEON_NEWPRIM( rmesa
);
263 rmesa
->tcl
.hw_primitive
= newprim
;
266 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
267 se_cntl
&= ~RADEON_FLAT_SHADE_VTX_LAST
;
269 if (prim
== GL_POLYGON
&& (ctx
->_TriangleCaps
& DD_FLATSHADE
))
270 se_cntl
|= RADEON_FLAT_SHADE_VTX_0
;
272 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
274 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
275 RADEON_STATECHANGE( rmesa
, set
);
276 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
280 /**********************************************************************/
281 /* Fog blend factor computation for hw tcl */
282 /* same calculation used as in t_vb_fog.c */
283 /**********************************************************************/
285 #define FOG_EXP_TABLE_SIZE 256
286 #define FOG_MAX (10.0)
287 #define EXP_FOG_MAX .0006595
288 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
289 static GLfloat exp_table
[FOG_EXP_TABLE_SIZE
];
292 #define NEG_EXP( result, narg ) \
294 GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR)); \
295 GLint k = (GLint) f; \
296 if (k > FOG_EXP_TABLE_SIZE-2) \
297 result = (GLfloat) EXP_FOG_MAX; \
299 result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]); \
302 #define NEG_EXP( result, narg ) \
304 result = exp(-narg); \
310 * Initialize the exp_table[] lookup table for approximating exp().
313 radeonInitStaticFogData( void )
317 for ( ; i
< FOG_EXP_TABLE_SIZE
; i
++, f
+= FOG_INCR
) {
318 exp_table
[i
] = (GLfloat
) exp(-f
);
324 * Compute per-vertex fog blend factors from fog coordinates by
325 * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
326 * Fog coordinates are distances from the eye (typically between the
327 * near and far clip plane distances).
328 * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
329 * Fog blend factors are in the range [0,1].
332 radeonComputeFogBlendFactor( GLcontext
*ctx
, GLfloat fogcoord
)
334 GLfloat end
= ctx
->Fog
.End
;
336 const GLfloat z
= FABSF(fogcoord
);
338 switch (ctx
->Fog
.Mode
) {
340 if (ctx
->Fog
.Start
== ctx
->Fog
.End
)
343 d
= 1.0F
/ (ctx
->Fog
.End
- ctx
->Fog
.Start
);
344 temp
= (end
- z
) * d
;
345 return CLAMP(temp
, 0.0F
, 1.0F
);
348 d
= ctx
->Fog
.Density
;
349 NEG_EXP( temp
, d
* z
);
353 d
= ctx
->Fog
.Density
*ctx
->Fog
.Density
;
354 NEG_EXP( temp
, d
* z
* z
);
358 _mesa_problem(ctx
, "Bad fog mode in make_fog_coord");
363 /**********************************************************************/
364 /* Render pipeline stage */
365 /**********************************************************************/
370 static GLboolean
radeon_run_tcl_render( GLcontext
*ctx
,
371 struct tnl_pipeline_stage
*stage
)
373 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
374 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
375 struct vertex_buffer
*VB
= &tnl
->vb
;
376 GLuint inputs
= VERT_BIT_POS
| VERT_BIT_COLOR0
;
379 /* TODO: separate this from the swtnl pipeline
381 if (rmesa
->radeon
.TclFallback
)
382 return GL_TRUE
; /* fallback to software t&l */
387 /* NOTE: inputs != tnl->render_inputs - these are the untransformed
390 if (ctx
->Light
.Enabled
) {
391 inputs
|= VERT_BIT_NORMAL
;
394 if (ctx
->_TriangleCaps
& DD_SEPARATE_SPECULAR
) {
395 inputs
|= VERT_BIT_COLOR1
;
398 if ( (ctx
->Fog
.FogCoordinateSource
== GL_FOG_COORD
) && ctx
->Fog
.Enabled
) {
399 inputs
|= VERT_BIT_FOG
;
402 for (i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
403 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
404 /* TODO: probably should not emit texture coords when texgen is enabled */
405 if (rmesa
->TexGenNeedNormals
[i
]) {
406 inputs
|= VERT_BIT_NORMAL
;
408 inputs
|= VERT_BIT_TEX(i
);
412 radeonReleaseArrays( ctx
, ~0 );
413 radeonEmitArrays( ctx
, inputs
);
415 rmesa
->tcl
.Elts
= VB
->Elts
;
417 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
419 GLuint prim
= _tnl_translate_prim(&VB
->Primitive
[i
]);
420 GLuint start
= VB
->Primitive
[i
].start
;
421 GLuint length
= VB
->Primitive
[i
].count
;
427 radeonEmitEltPrimitive( ctx
, start
, start
+length
, prim
);
429 radeonEmitPrimitive( ctx
, start
, start
+length
, prim
);
432 return GL_FALSE
; /* finished the pipe */
437 /* Initial state for tcl stage.
439 const struct tnl_pipeline_stage _radeon_tcl_stage
=
446 radeon_run_tcl_render
/* run */
451 /**********************************************************************/
452 /* Validate state at pipeline start */
453 /**********************************************************************/
456 /*-----------------------------------------------------------------------
457 * Manage TCL fallbacks
461 static void transition_to_swtnl( GLcontext
*ctx
)
463 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
464 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
467 RADEON_NEWPRIM( rmesa
);
468 rmesa
->swtcl
.vertex_format
= 0;
470 radeonChooseVertexState( ctx
);
471 radeonChooseRenderState( ctx
);
473 _mesa_validate_all_lighting_tables( ctx
);
475 tnl
->Driver
.NotifyMaterialChange
=
476 _mesa_validate_all_lighting_tables
;
478 radeonReleaseArrays( ctx
, ~0 );
480 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
481 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
483 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
484 RADEON_STATECHANGE( rmesa
, set
);
485 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
490 static void transition_to_hwtnl( GLcontext
*ctx
)
492 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
493 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
494 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
496 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
497 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
498 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
499 se_coord_fmt
|= RADEON_VTX_W0_IS_NOT_1_OVER_W0
;
501 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
502 RADEON_STATECHANGE( rmesa
, set
);
503 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
504 _tnl_need_projected_coords( ctx
, GL_FALSE
);
507 radeonUpdateMaterial( ctx
);
509 tnl
->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
511 if ( rmesa
->radeon
.dma
.flush
)
512 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
514 rmesa
->radeon
.dma
.flush
= NULL
;
515 rmesa
->swtcl
.vertex_format
= 0;
517 // if (rmesa->swtcl.indexed_verts.buf)
518 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
521 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
522 fprintf(stderr
, "Radeon end tcl fallback\n");
525 static char *fallbackStrings
[] = {
526 "Rasterization fallback",
527 "Unfilled triangles",
528 "Twosided lighting, differing materials",
529 "Materials in VB (maybe between begin/end)",
534 "Fogcoord with separate specular lighting"
538 static char *getFallbackString(GLuint bit
)
545 return fallbackStrings
[i
];
550 void radeonTclFallback( GLcontext
*ctx
, GLuint bit
, GLboolean mode
)
552 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
553 GLuint oldfallback
= rmesa
->radeon
.TclFallback
;
556 rmesa
->radeon
.TclFallback
|= bit
;
557 if (oldfallback
== 0) {
558 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
559 fprintf(stderr
, "Radeon begin tcl fallback %s\n",
560 getFallbackString( bit
));
561 transition_to_swtnl( ctx
);
565 rmesa
->radeon
.TclFallback
&= ~bit
;
566 if (oldfallback
== bit
) {
567 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
568 fprintf(stderr
, "Radeon end tcl fallback %s\n",
569 getFallbackString( bit
));
570 transition_to_hwtnl( ctx
);