1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 Tungsten Graphics Inc., Austin, Texas.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "main/glheader.h"
36 #include "main/imports.h"
37 #include "main/light.h"
38 #include "main/mtypes.h"
39 #include "main/enums.h"
43 #include "tnl/t_pipeline.h"
45 #include "radeon_common.h"
46 #include "radeon_context.h"
47 #include "radeon_state.h"
48 #include "radeon_ioctl.h"
49 #include "radeon_tcl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_maos.h"
52 #include "radeon_common_context.h"
57 * Render unclipped vertex buffers by emitting vertices directly to
58 * dma buffers. Use strip/fan hardware primitives where possible.
59 * Try to simulate missing primitives with indexed vertices.
63 #define HAVE_LINE_LOOP 0
64 #define HAVE_LINE_STRIPS 1
65 #define HAVE_TRIANGLES 1
66 #define HAVE_TRI_STRIPS 1
67 #define HAVE_TRI_STRIP_1 0
68 #define HAVE_TRI_FANS 1
70 #define HAVE_QUAD_STRIPS 0
71 #define HAVE_POLYGONS 1
75 #define HW_POINTS RADEON_CP_VC_CNTL_PRIM_TYPE_POINT
76 #define HW_LINES RADEON_CP_VC_CNTL_PRIM_TYPE_LINE
77 #define HW_LINE_LOOP 0
78 #define HW_LINE_STRIP RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP
79 #define HW_TRIANGLES RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST
80 #define HW_TRIANGLE_STRIP_0 RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP
81 #define HW_TRIANGLE_STRIP_1 0
82 #define HW_TRIANGLE_FAN RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
84 #define HW_QUAD_STRIP 0
85 #define HW_POLYGON RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN
88 static GLboolean discrete_prim
[0x10] = {
96 1, /* 7 rect list (unused) */
97 1, /* 8 3vert point */
108 #define LOCAL_VARS r100ContextPtr rmesa = R100_CONTEXT(ctx)
109 #define ELT_TYPE GLushort
111 #define ELT_INIT(prim, hw_prim) \
112 radeonTclPrimitive( ctx, prim, hw_prim | RADEON_CP_VC_CNTL_PRIM_WALK_IND )
114 #define GET_MESA_ELTS() rmesa->tcl.Elts
117 /* Don't really know how many elts will fit in what's left of cmdbuf,
118 * as there is state to emit, etc:
121 /* Testing on isosurf shows a maximum around here. Don't know if it's
122 * the card or driver or kernel module that is causing the behaviour.
124 #define GET_MAX_HW_ELTS() 300
127 #define RESET_STIPPLE() do { \
128 RADEON_STATECHANGE( rmesa, lin ); \
129 radeonEmitState(&rmesa->radeon); \
132 #define AUTO_STIPPLE( mode ) do { \
133 RADEON_STATECHANGE( rmesa, lin ); \
135 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] |= \
136 RADEON_LINE_PATTERN_AUTO_RESET; \
138 rmesa->hw.lin.cmd[LIN_RE_LINE_PATTERN] &= \
139 ~RADEON_LINE_PATTERN_AUTO_RESET; \
140 radeonEmitState(&rmesa->radeon); \
145 #define ALLOC_ELTS(nr) radeonAllocElts( rmesa, nr )
147 static GLushort
*radeonAllocElts( r100ContextPtr rmesa
, GLuint nr
)
149 if (rmesa
->radeon
.dma
.flush
)
150 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
152 radeonEmitAOS( rmesa
,
153 rmesa
->radeon
.tcl
.aos_count
, 0 );
155 return radeonAllocEltsOpenEnded( rmesa
, rmesa
->tcl
.vertex_format
,
156 rmesa
->tcl
.hw_primitive
, nr
);
159 #define CLOSE_ELTS() if (0) RADEON_NEWPRIM( rmesa )
163 /* TODO: Try to extend existing primitive if both are identical,
164 * discrete and there are no intervening state changes. (Somewhat
165 * duplicates changes to DrawArrays code)
167 static void radeonEmitPrim( struct gl_context
*ctx
,
173 r100ContextPtr rmesa
= R100_CONTEXT( ctx
);
174 radeonTclPrimitive( ctx
, prim
, hwprim
);
176 radeonEmitAOS( rmesa
,
177 rmesa
->radeon
.tcl
.aos_count
,
180 /* Why couldn't this packet have taken an offset param?
182 radeonEmitVbufPrim( rmesa
,
183 rmesa
->tcl
.vertex_format
,
184 rmesa
->tcl
.hw_primitive
,
188 #define EMIT_PRIM( ctx, prim, hwprim, start, count ) do { \
189 radeonEmitPrim( ctx, prim, hwprim, start, count ); \
190 (void) rmesa; } while (0)
192 #define MAX_CONVERSION_SIZE 40
194 /* Try & join small primitives
197 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) 0
199 #define PREFER_DISCRETE_ELT_PRIM( NR, PRIM ) \
202 rmesa->tcl.hw_primitive == (PRIM| \
203 RADEON_CP_VC_CNTL_PRIM_WALK_IND| \
204 RADEON_CP_VC_CNTL_TCL_ENABLE)))
207 #ifdef MESA_BIG_ENDIAN
208 /* We could do without (most of) this ugliness if dest was always 32 bit word aligned... */
209 #define EMIT_ELT(dest, offset, x) do { \
210 int off = offset + ( ( (GLuint)dest & 0x2 ) >> 1 ); \
211 GLushort *des = (GLushort *)( (GLuint)dest & ~0x2 ); \
212 (des)[ off + 1 - 2 * ( off & 1 ) ] = (GLushort)(x); \
213 (void)rmesa; } while (0)
215 #define EMIT_ELT(dest, offset, x) do { \
216 (dest)[offset] = (GLushort) (x); \
217 (void)rmesa; } while (0)
220 #define EMIT_TWO_ELTS(dest, offset, x, y) *(GLuint *)(dest+offset) = ((y)<<16)|(x);
224 #define TAG(x) tcl_##x
225 #include "tnl_dd/t_dd_dmatmp2.h"
227 /**********************************************************************/
228 /* External entrypoints */
229 /**********************************************************************/
231 void radeonEmitPrimitive( struct gl_context
*ctx
,
236 tcl_render_tab_verts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
239 void radeonEmitEltPrimitive( struct gl_context
*ctx
,
244 tcl_render_tab_elts
[flags
&PRIM_MODE_MASK
]( ctx
, first
, last
, flags
);
247 void radeonTclPrimitive( struct gl_context
*ctx
,
251 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
253 GLuint newprim
= hw_prim
| RADEON_CP_VC_CNTL_TCL_ENABLE
;
255 radeon_prepare_render(&rmesa
->radeon
);
257 if (newprim
!= rmesa
->tcl
.hw_primitive
||
258 !discrete_prim
[hw_prim
&0xf]) {
259 RADEON_NEWPRIM( rmesa
);
260 rmesa
->tcl
.hw_primitive
= newprim
;
263 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
264 se_cntl
&= ~RADEON_FLAT_SHADE_VTX_LAST
;
266 if (prim
== GL_POLYGON
&& (ctx
->_TriangleCaps
& DD_FLATSHADE
))
267 se_cntl
|= RADEON_FLAT_SHADE_VTX_0
;
269 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
271 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
272 RADEON_STATECHANGE( rmesa
, set
);
273 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
277 /**********************************************************************/
278 /* Fog blend factor computation for hw tcl */
279 /* same calculation used as in t_vb_fog.c */
280 /**********************************************************************/
282 #define FOG_EXP_TABLE_SIZE 256
283 #define FOG_MAX (10.0)
284 #define EXP_FOG_MAX .0006595
285 #define FOG_INCR (FOG_MAX/FOG_EXP_TABLE_SIZE)
286 static GLfloat exp_table
[FOG_EXP_TABLE_SIZE
];
289 #define NEG_EXP( result, narg ) \
291 GLfloat f = (GLfloat) (narg * (1.0/FOG_INCR)); \
292 GLint k = (GLint) f; \
293 if (k > FOG_EXP_TABLE_SIZE-2) \
294 result = (GLfloat) EXP_FOG_MAX; \
296 result = exp_table[k] + (f-k)*(exp_table[k+1]-exp_table[k]); \
299 #define NEG_EXP( result, narg ) \
301 result = exp(-narg); \
307 * Initialize the exp_table[] lookup table for approximating exp().
310 radeonInitStaticFogData( void )
314 for ( ; i
< FOG_EXP_TABLE_SIZE
; i
++, f
+= FOG_INCR
) {
315 exp_table
[i
] = (GLfloat
) exp(-f
);
321 * Compute per-vertex fog blend factors from fog coordinates by
322 * evaluating the GL_LINEAR, GL_EXP or GL_EXP2 fog function.
323 * Fog coordinates are distances from the eye (typically between the
324 * near and far clip plane distances).
325 * Note the fog (eye Z) coords may be negative so we use ABS(z) below.
326 * Fog blend factors are in the range [0,1].
329 radeonComputeFogBlendFactor( struct gl_context
*ctx
, GLfloat fogcoord
)
331 GLfloat end
= ctx
->Fog
.End
;
333 const GLfloat z
= FABSF(fogcoord
);
335 switch (ctx
->Fog
.Mode
) {
337 if (ctx
->Fog
.Start
== ctx
->Fog
.End
)
340 d
= 1.0F
/ (ctx
->Fog
.End
- ctx
->Fog
.Start
);
341 temp
= (end
- z
) * d
;
342 return CLAMP(temp
, 0.0F
, 1.0F
);
345 d
= ctx
->Fog
.Density
;
346 NEG_EXP( temp
, d
* z
);
350 d
= ctx
->Fog
.Density
*ctx
->Fog
.Density
;
351 NEG_EXP( temp
, d
* z
* z
);
355 _mesa_problem(ctx
, "Bad fog mode in make_fog_coord");
361 * Predict total emit size for next rendering operation so there is no flush in middle of rendering
362 * Prediction has to aim towards the best possible value that is worse than worst case scenario
364 static GLuint
radeonEnsureEmitSize( struct gl_context
* ctx
, GLuint inputs
)
366 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
367 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
368 struct vertex_buffer
*VB
= &tnl
->vb
;
369 GLuint space_required
;
371 GLuint nr_aos
= 1; /* radeonEmitArrays does always emit one */
373 /* list of flags that are allocating aos object */
374 const GLuint flags_to_check
[] = {
380 /* predict number of aos to emit */
381 for (i
=0; i
< sizeof(flags_to_check
)/sizeof(flags_to_check
[0]); ++i
)
383 if (inputs
& flags_to_check
[i
])
386 for (i
= 0; i
< ctx
->Const
.MaxTextureUnits
; ++i
)
388 if (inputs
& VERT_BIT_TEX(i
))
393 /* count the prediction for state size */
395 state_size
= radeonCountStateEmitSize( &rmesa
->radeon
);
396 /* tcl may be changed in radeonEmitArrays so account for it if not dirty */
397 if (!rmesa
->hw
.tcl
.dirty
)
398 state_size
+= rmesa
->hw
.tcl
.check( rmesa
->radeon
.glCtx
, &rmesa
->hw
.tcl
);
399 /* predict size for elements */
400 for (i
= 0; i
< VB
->PrimitiveCount
; ++i
)
402 if (!VB
->Primitive
[i
].count
)
404 /* If primitive.count is less than MAX_CONVERSION_SIZE
405 rendering code may decide convert to elts.
406 In that case we have to make pessimistic prediction.
407 and use larger of 2 paths. */
408 const GLuint elts
= ELTS_BUFSZ(nr_aos
);
409 const GLuint index
= INDEX_BUFSZ
;
410 const GLuint vbuf
= VBUF_BUFSZ
;
411 if ( (!VB
->Elts
&& VB
->Primitive
[i
].count
>= MAX_CONVERSION_SIZE
)
412 || vbuf
> index
+ elts
)
413 space_required
+= vbuf
;
415 space_required
+= index
+ elts
;
416 space_required
+= VB
->Primitive
[i
].count
* 3;
417 space_required
+= AOS_BUFSZ(nr_aos
);
419 space_required
+= SCISSOR_BUFSZ
;
421 /* flush the buffer in case we need more than is left. */
422 if (rcommonEnsureCmdBufSpace(&rmesa
->radeon
, space_required
, __FUNCTION__
))
423 return space_required
+ radeonCountStateEmitSize( &rmesa
->radeon
);
425 return space_required
+ state_size
;
428 /**********************************************************************/
429 /* Render pipeline stage */
430 /**********************************************************************/
435 static GLboolean
radeon_run_tcl_render( struct gl_context
*ctx
,
436 struct tnl_pipeline_stage
*stage
)
438 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
439 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
440 struct vertex_buffer
*VB
= &tnl
->vb
;
441 GLuint inputs
= VERT_BIT_POS
| VERT_BIT_COLOR0
;
444 /* TODO: separate this from the swtnl pipeline
446 if (rmesa
->radeon
.TclFallback
)
447 return GL_TRUE
; /* fallback to software t&l */
452 /* NOTE: inputs != tnl->render_inputs - these are the untransformed
455 if (ctx
->Light
.Enabled
) {
456 inputs
|= VERT_BIT_NORMAL
;
459 if (ctx
->_TriangleCaps
& DD_SEPARATE_SPECULAR
) {
460 inputs
|= VERT_BIT_COLOR1
;
463 if ( (ctx
->Fog
.FogCoordinateSource
== GL_FOG_COORD
) && ctx
->Fog
.Enabled
) {
464 inputs
|= VERT_BIT_FOG
;
467 for (i
= 0 ; i
< ctx
->Const
.MaxTextureUnits
; i
++) {
468 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
469 /* TODO: probably should not emit texture coords when texgen is enabled */
470 if (rmesa
->TexGenNeedNormals
[i
]) {
471 inputs
|= VERT_BIT_NORMAL
;
473 inputs
|= VERT_BIT_TEX(i
);
477 radeonReleaseArrays( ctx
, ~0 );
478 GLuint emit_end
= radeonEnsureEmitSize( ctx
, inputs
)
479 + rmesa
->radeon
.cmdbuf
.cs
->cdw
;
480 radeonEmitArrays( ctx
, inputs
);
482 rmesa
->tcl
.Elts
= VB
->Elts
;
484 for (i
= 0 ; i
< VB
->PrimitiveCount
; i
++)
486 GLuint prim
= _tnl_translate_prim(&VB
->Primitive
[i
]);
487 GLuint start
= VB
->Primitive
[i
].start
;
488 GLuint length
= VB
->Primitive
[i
].count
;
494 radeonEmitEltPrimitive( ctx
, start
, start
+length
, prim
);
496 radeonEmitPrimitive( ctx
, start
, start
+length
, prim
);
499 if (emit_end
< rmesa
->radeon
.cmdbuf
.cs
->cdw
)
500 WARN_ONCE("Rendering was %d commands larger than predicted size."
501 " We might overflow command buffer.\n", rmesa
->radeon
.cmdbuf
.cs
->cdw
- emit_end
);
503 return GL_FALSE
; /* finished the pipe */
508 /* Initial state for tcl stage.
510 const struct tnl_pipeline_stage _radeon_tcl_stage
=
517 radeon_run_tcl_render
/* run */
522 /**********************************************************************/
523 /* Validate state at pipeline start */
524 /**********************************************************************/
527 /*-----------------------------------------------------------------------
528 * Manage TCL fallbacks
532 static void transition_to_swtnl( struct gl_context
*ctx
)
534 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
535 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
538 RADEON_NEWPRIM( rmesa
);
539 rmesa
->swtcl
.vertex_format
= 0;
541 radeonChooseVertexState( ctx
);
542 radeonChooseRenderState( ctx
);
544 _mesa_validate_all_lighting_tables( ctx
);
546 tnl
->Driver
.NotifyMaterialChange
=
547 _mesa_validate_all_lighting_tables
;
549 radeonReleaseArrays( ctx
, ~0 );
551 se_cntl
= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
];
552 se_cntl
|= RADEON_FLAT_SHADE_VTX_LAST
;
554 if (se_cntl
!= rmesa
->hw
.set
.cmd
[SET_SE_CNTL
]) {
555 RADEON_STATECHANGE( rmesa
, set
);
556 rmesa
->hw
.set
.cmd
[SET_SE_CNTL
] = se_cntl
;
561 static void transition_to_hwtnl( struct gl_context
*ctx
)
563 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
564 TNLcontext
*tnl
= TNL_CONTEXT(ctx
);
565 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
567 se_coord_fmt
&= ~(RADEON_VTX_XY_PRE_MULT_1_OVER_W0
|
568 RADEON_VTX_Z_PRE_MULT_1_OVER_W0
|
569 RADEON_VTX_W0_IS_NOT_1_OVER_W0
);
570 se_coord_fmt
|= RADEON_VTX_W0_IS_NOT_1_OVER_W0
;
572 if ( se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] ) {
573 RADEON_STATECHANGE( rmesa
, set
);
574 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
575 _tnl_need_projected_coords( ctx
, GL_FALSE
);
578 radeonUpdateMaterial( ctx
);
580 tnl
->Driver
.NotifyMaterialChange
= radeonUpdateMaterial
;
582 if ( rmesa
->radeon
.dma
.flush
)
583 rmesa
->radeon
.dma
.flush( rmesa
->radeon
.glCtx
);
585 rmesa
->radeon
.dma
.flush
= NULL
;
586 rmesa
->swtcl
.vertex_format
= 0;
588 // if (rmesa->swtcl.indexed_verts.buf)
589 // radeonReleaseDmaRegion( rmesa, &rmesa->swtcl.indexed_verts,
592 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
593 fprintf(stderr
, "Radeon end tcl fallback\n");
596 static char *fallbackStrings
[] = {
597 "Rasterization fallback",
598 "Unfilled triangles",
599 "Twosided lighting, differing materials",
600 "Materials in VB (maybe between begin/end)",
605 "Fogcoord with separate specular lighting"
609 static char *getFallbackString(GLuint bit
)
616 return fallbackStrings
[i
];
621 void radeonTclFallback( struct gl_context
*ctx
, GLuint bit
, GLboolean mode
)
623 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
624 GLuint oldfallback
= rmesa
->radeon
.TclFallback
;
627 rmesa
->radeon
.TclFallback
|= bit
;
628 if (oldfallback
== 0) {
629 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
630 fprintf(stderr
, "Radeon begin tcl fallback %s\n",
631 getFallbackString( bit
));
632 transition_to_swtnl( ctx
);
636 rmesa
->radeon
.TclFallback
&= ~bit
;
637 if (oldfallback
== bit
) {
638 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
639 fprintf(stderr
, "Radeon end tcl fallback %s\n",
640 getFallbackString( bit
));
641 transition_to_hwtnl( ctx
);