2 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
3 VA Linux Systems Inc., Fremont, California.
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 * Gareth Hughes <gareth@valinux.com>
31 * Brian Paul <brianp@valinux.com>
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/colormac.h"
37 #include "main/context.h"
38 #include "main/enums.h"
39 #include "main/image.h"
40 #include "main/simple_list.h"
41 #include "main/texformat.h"
42 #include "main/texstore.h"
43 #include "main/teximage.h"
44 #include "main/texobj.h"
46 #include "radeon_context.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_state.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_tex.h"
58 * Set the texture wrap modes.
60 * \param t Texture object whose wrap modes are to be set
61 * \param swrap Wrap mode for the \a s texture coordinate
62 * \param twrap Wrap mode for the \a t texture coordinate
65 static void radeonSetTexWrap( radeonTexObjPtr t
, GLenum swrap
, GLenum twrap
)
67 GLboolean is_clamp
= GL_FALSE
;
68 GLboolean is_clamp_to_border
= GL_FALSE
;
70 t
->pp_txfilter
&= ~(RADEON_CLAMP_S_MASK
| RADEON_CLAMP_T_MASK
| RADEON_BORDER_MODE_D3D
);
74 t
->pp_txfilter
|= RADEON_CLAMP_S_WRAP
;
77 t
->pp_txfilter
|= RADEON_CLAMP_S_CLAMP_GL
;
80 case GL_CLAMP_TO_EDGE
:
81 t
->pp_txfilter
|= RADEON_CLAMP_S_CLAMP_LAST
;
83 case GL_CLAMP_TO_BORDER
:
84 t
->pp_txfilter
|= RADEON_CLAMP_S_CLAMP_GL
;
85 is_clamp_to_border
= GL_TRUE
;
87 case GL_MIRRORED_REPEAT
:
88 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR
;
90 case GL_MIRROR_CLAMP_EXT
:
91 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR_CLAMP_GL
;
94 case GL_MIRROR_CLAMP_TO_EDGE_EXT
:
95 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR_CLAMP_LAST
;
97 case GL_MIRROR_CLAMP_TO_BORDER_EXT
:
98 t
->pp_txfilter
|= RADEON_CLAMP_S_MIRROR_CLAMP_GL
;
99 is_clamp_to_border
= GL_TRUE
;
102 _mesa_problem(NULL
, "bad S wrap mode in %s", __FUNCTION__
);
107 t
->pp_txfilter
|= RADEON_CLAMP_T_WRAP
;
110 t
->pp_txfilter
|= RADEON_CLAMP_T_CLAMP_GL
;
113 case GL_CLAMP_TO_EDGE
:
114 t
->pp_txfilter
|= RADEON_CLAMP_T_CLAMP_LAST
;
116 case GL_CLAMP_TO_BORDER
:
117 t
->pp_txfilter
|= RADEON_CLAMP_T_CLAMP_GL
;
118 is_clamp_to_border
= GL_TRUE
;
120 case GL_MIRRORED_REPEAT
:
121 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR
;
123 case GL_MIRROR_CLAMP_EXT
:
124 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR_CLAMP_GL
;
127 case GL_MIRROR_CLAMP_TO_EDGE_EXT
:
128 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR_CLAMP_LAST
;
130 case GL_MIRROR_CLAMP_TO_BORDER_EXT
:
131 t
->pp_txfilter
|= RADEON_CLAMP_T_MIRROR_CLAMP_GL
;
132 is_clamp_to_border
= GL_TRUE
;
135 _mesa_problem(NULL
, "bad T wrap mode in %s", __FUNCTION__
);
138 if ( is_clamp_to_border
) {
139 t
->pp_txfilter
|= RADEON_BORDER_MODE_D3D
;
142 t
->border_fallback
= (is_clamp
&& is_clamp_to_border
);
145 static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t
, GLfloat max
)
147 t
->pp_txfilter
&= ~RADEON_MAX_ANISO_MASK
;
150 t
->pp_txfilter
|= RADEON_MAX_ANISO_1_TO_1
;
151 } else if ( max
<= 2.0 ) {
152 t
->pp_txfilter
|= RADEON_MAX_ANISO_2_TO_1
;
153 } else if ( max
<= 4.0 ) {
154 t
->pp_txfilter
|= RADEON_MAX_ANISO_4_TO_1
;
155 } else if ( max
<= 8.0 ) {
156 t
->pp_txfilter
|= RADEON_MAX_ANISO_8_TO_1
;
158 t
->pp_txfilter
|= RADEON_MAX_ANISO_16_TO_1
;
163 * Set the texture magnification and minification modes.
165 * \param t Texture whose filter modes are to be set
166 * \param minf Texture minification mode
167 * \param magf Texture magnification mode
170 static void radeonSetTexFilter( radeonTexObjPtr t
, GLenum minf
, GLenum magf
)
172 GLuint anisotropy
= (t
->pp_txfilter
& RADEON_MAX_ANISO_MASK
);
174 /* Force revalidation to account for switches from/to mipmapping. */
175 t
->validated
= GL_FALSE
;
177 t
->pp_txfilter
&= ~(RADEON_MIN_FILTER_MASK
| RADEON_MAG_FILTER_MASK
);
179 /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */
180 if ( t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
183 case GL_NEAREST_MIPMAP_NEAREST
:
184 case GL_NEAREST_MIPMAP_LINEAR
:
185 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST
;
188 case GL_LINEAR_MIPMAP_NEAREST
:
189 case GL_LINEAR_MIPMAP_LINEAR
:
190 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR
;
196 else if ( anisotropy
== RADEON_MAX_ANISO_1_TO_1
) {
199 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST
;
202 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR
;
204 case GL_NEAREST_MIPMAP_NEAREST
:
205 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST
;
207 case GL_NEAREST_MIPMAP_LINEAR
:
208 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST
;
210 case GL_LINEAR_MIPMAP_NEAREST
:
211 t
->pp_txfilter
|= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR
;
213 case GL_LINEAR_MIPMAP_LINEAR
:
214 t
->pp_txfilter
|= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR
;
220 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_NEAREST
;
223 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_LINEAR
;
225 case GL_NEAREST_MIPMAP_NEAREST
:
226 case GL_LINEAR_MIPMAP_NEAREST
:
227 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST
;
229 case GL_NEAREST_MIPMAP_LINEAR
:
230 case GL_LINEAR_MIPMAP_LINEAR
:
231 t
->pp_txfilter
|= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR
;
238 t
->pp_txfilter
|= RADEON_MAG_FILTER_NEAREST
;
241 t
->pp_txfilter
|= RADEON_MAG_FILTER_LINEAR
;
246 static void radeonSetTexBorderColor( radeonTexObjPtr t
, const GLfloat color
[4] )
249 CLAMPED_FLOAT_TO_UBYTE(c
[0], color
[0]);
250 CLAMPED_FLOAT_TO_UBYTE(c
[1], color
[1]);
251 CLAMPED_FLOAT_TO_UBYTE(c
[2], color
[2]);
252 CLAMPED_FLOAT_TO_UBYTE(c
[3], color
[3]);
253 t
->pp_border_color
= radeonPackColor( 4, c
[0], c
[1], c
[2], c
[3] );
256 #define SCALED_FLOAT_TO_BYTE( x, scale ) \
257 (((GLuint)((255.0F / scale) * (x))) / 2)
259 static void radeonTexEnv( GLcontext
*ctx
, GLenum target
,
260 GLenum pname
, const GLfloat
*param
)
262 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
263 GLuint unit
= ctx
->Texture
.CurrentUnit
;
264 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
266 if ( RADEON_DEBUG
& RADEON_STATE
) {
267 fprintf( stderr
, "%s( %s )\n",
268 __FUNCTION__
, _mesa_lookup_enum_by_nr( pname
) );
272 case GL_TEXTURE_ENV_COLOR
: {
275 UNCLAMPED_FLOAT_TO_RGBA_CHAN( c
, texUnit
->EnvColor
);
276 envColor
= radeonPackColor( 4, c
[0], c
[1], c
[2], c
[3] );
277 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TFACTOR
] != envColor
) {
278 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
279 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TFACTOR
] = envColor
;
284 case GL_TEXTURE_LOD_BIAS_EXT
: {
288 /* The Radeon's LOD bias is a signed 2's complement value with a
289 * range of -1.0 <= bias < 4.0. We break this into two linear
290 * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
291 * [0.0,4.0] to [0,127].
293 min
= driQueryOptionb (&rmesa
->radeon
.optionCache
, "no_neg_lod_bias") ?
295 bias
= CLAMP( *param
, min
, 4.0 );
298 } else if ( bias
> 0 ) {
299 b
= ((GLuint
)SCALED_FLOAT_TO_BYTE( bias
, 4.0 )) << RADEON_LOD_BIAS_SHIFT
;
301 b
= ((GLuint
)SCALED_FLOAT_TO_BYTE( bias
, 1.0 )) << RADEON_LOD_BIAS_SHIFT
;
303 if ( (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFILTER
] & RADEON_LOD_BIAS_MASK
) != b
) {
304 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
305 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFILTER
] &= ~RADEON_LOD_BIAS_MASK
;
306 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFILTER
] |= (b
& RADEON_LOD_BIAS_MASK
);
318 * Changes variables and flags for a state update, which will happen at the
319 * next UpdateTextureState
322 static void radeonTexParameter( GLcontext
*ctx
, GLenum target
,
323 struct gl_texture_object
*texObj
,
324 GLenum pname
, const GLfloat
*params
)
326 radeonTexObj
* t
= radeon_tex_obj(texObj
);
328 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
, "%s( %s )\n", __FUNCTION__
,
329 _mesa_lookup_enum_by_nr( pname
) );
332 case GL_TEXTURE_MIN_FILTER
:
333 case GL_TEXTURE_MAG_FILTER
:
334 case GL_TEXTURE_MAX_ANISOTROPY_EXT
:
335 radeonSetTexMaxAnisotropy( t
, texObj
->MaxAnisotropy
);
336 radeonSetTexFilter( t
, texObj
->MinFilter
, texObj
->MagFilter
);
339 case GL_TEXTURE_WRAP_S
:
340 case GL_TEXTURE_WRAP_T
:
341 radeonSetTexWrap( t
, texObj
->WrapS
, texObj
->WrapT
);
344 case GL_TEXTURE_BORDER_COLOR
:
345 radeonSetTexBorderColor( t
, texObj
->BorderColor
);
348 case GL_TEXTURE_BASE_LEVEL
:
349 case GL_TEXTURE_MAX_LEVEL
:
350 case GL_TEXTURE_MIN_LOD
:
351 case GL_TEXTURE_MAX_LOD
:
353 /* This isn't the most efficient solution but there doesn't appear to
354 * be a nice alternative. Since there's no LOD clamping,
355 * we just have to rely on loading the right subset of mipmap levels
356 * to simulate a clamped LOD.
359 radeon_miptree_unreference(t
->mt
);
361 t
->validated
= GL_FALSE
;
370 static void radeonDeleteTexture( GLcontext
*ctx
,
371 struct gl_texture_object
*texObj
)
373 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
374 radeonTexObj
* t
= radeon_tex_obj(texObj
);
377 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
378 "%s( %p (target = %s) )\n", __FUNCTION__
, (void *)texObj
,
379 _mesa_lookup_enum_by_nr( texObj
->Target
) );
382 radeon_firevertices(&rmesa
->radeon
);
383 for ( i
= 0 ; i
< rmesa
->radeon
.glCtx
->Const
.MaxTextureUnits
; i
++ ) {
384 if ( t
== rmesa
->state
.texture
.unit
[i
].texobj
) {
385 rmesa
->state
.texture
.unit
[i
].texobj
= NULL
;
386 rmesa
->hw
.tex
[i
].dirty
= GL_FALSE
;
387 rmesa
->hw
.cube
[i
].dirty
= GL_FALSE
;
393 radeon_miptree_unreference(t
->mt
);
396 /* Free mipmap images and the texture object itself */
397 _mesa_delete_texture_object(ctx
, texObj
);
401 * - Same GEN_MODE for all active bits
402 * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj
403 * - STRQ presumably all supported (matrix means incoming R values
404 * can end up in STQ, this has implications for vertex support,
405 * presumably ok if maos is used, though?)
407 * Basically impossible to do this on the fly - just collect some
408 * basic info & do the checks from ValidateState().
410 static void radeonTexGen( GLcontext
*ctx
,
413 const GLfloat
*params
)
415 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
416 GLuint unit
= ctx
->Texture
.CurrentUnit
;
417 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
421 * Allocate a new texture object.
422 * Called via ctx->Driver.NewTextureObject.
423 * Note: we could use containment here to 'derive' the driver-specific
424 * texture object from the core mesa gl_texture_object. Not done at this time.
426 static struct gl_texture_object
*
427 radeonNewTextureObject( GLcontext
*ctx
, GLuint name
, GLenum target
)
429 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
430 radeonTexObj
* t
= CALLOC_STRUCT(radeon_tex_obj
);
432 _mesa_initialize_texture_object(&t
->base
, name
, target
);
433 t
->base
.MaxAnisotropy
= rmesa
->radeon
.initialMaxAnisotropy
;
435 t
->border_fallback
= GL_FALSE
;
437 t
->pp_txfilter
= RADEON_BORDER_MODE_OGL
;
438 t
->pp_txformat
= (RADEON_TXFORMAT_ENDIAN_NO_SWAP
|
439 RADEON_TXFORMAT_PERSPECTIVE_ENABLE
);
441 radeonSetTexWrap( t
, t
->base
.WrapS
, t
->base
.WrapT
);
442 radeonSetTexMaxAnisotropy( t
, t
->base
.MaxAnisotropy
);
443 radeonSetTexFilter( t
, t
->base
.MinFilter
, t
->base
.MagFilter
);
444 radeonSetTexBorderColor( t
, t
->base
.BorderColor
);
450 void radeonInitTextureFuncs( struct dd_function_table
*functions
)
452 functions
->ChooseTextureFormat
= radeonChooseTextureFormat_mesa
;
453 functions
->TexImage1D
= radeonTexImage1D
;
454 functions
->TexImage2D
= radeonTexImage2D
;
455 functions
->TexSubImage1D
= radeonTexSubImage1D
;
456 functions
->TexSubImage2D
= radeonTexSubImage2D
;
457 functions
->GetTexImage
= radeonGetTexImage
;
458 functions
->GetCompressedTexImage
= radeonGetCompressedTexImage
;
460 functions
->NewTextureObject
= radeonNewTextureObject
;
461 // functions->BindTexture = radeonBindTexture;
462 functions
->DeleteTexture
= radeonDeleteTexture
;
464 functions
->TexEnv
= radeonTexEnv
;
465 functions
->TexParameter
= radeonTexParameter
;
466 functions
->TexGen
= radeonTexGen
;
468 functions
->CompressedTexImage2D
= radeonCompressedTexImage2D
;
469 functions
->CompressedTexSubImage2D
= radeonCompressedTexSubImage2D
;
471 functions
->GenerateMipmap
= radeonGenerateMipmap
;
473 functions
->NewTextureImage
= radeonNewTextureImage
;
474 functions
->FreeTexImageData
= radeonFreeTexImageData
;
475 functions
->MapTexture
= radeonMapTexture
;
476 functions
->UnmapTexture
= radeonUnmapTexture
;
478 driInitTextureFormats();