src/mesa/drivers/dri/radeon/radeon_tex.c

   1 /*
   2 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   3                      VA Linux Systems Inc., Fremont, California.
   4
   5 All Rights Reserved.
   6
   7 Permission is hereby granted, free of charge, to any person obtaining
   8 a copy of this software and associated documentation files (the
   9 "Software"), to deal in the Software without restriction, including
  10 without limitation the rights to use, copy, modify, merge, publish,
  11 distribute, sublicense, and/or sell copies of the Software, and to
  12 permit persons to whom the Software is furnished to do so, subject to
  13 the following conditions:
  14
  15 The above copyright notice and this permission notice (including the
  16 next paragraph) shall be included in all copies or substantial
  17 portions of the Software.
  18
  19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26 */
  27
  28 /*
  29  * Authors:
  30  *    Gareth Hughes <gareth@valinux.com>
  31  *    Brian Paul <brianp@valinux.com>
  32  */
  33
  34 #include "main/glheader.h"
  35 #include "main/imports.h"
  36 #include "main/colormac.h"
  37 #include "main/context.h"
  38 #include "main/enums.h"
  39 #include "main/image.h"
  40 #include "main/simple_list.h"
  41 #include "main/texformat.h"
  42 #include "main/texstore.h"
  43 #include "main/teximage.h"
  44 #include "main/texobj.h"
  45
  46 #include "radeon_context.h"
  47 #include "radeon_mipmap_tree.h"
  48 #include "radeon_state.h"
  49 #include "radeon_ioctl.h"
  50 #include "radeon_swtcl.h"
  51 #include "radeon_tex.h"
  52
  53 #include "xmlpool.h"
  54
  55
  56
  57 /**
  58  * Set the texture wrap modes.
  59  *
  60  * \param t Texture object whose wrap modes are to be set
  61  * \param swrap Wrap mode for the \a s texture coordinate
  62  * \param twrap Wrap mode for the \a t texture coordinate
  63  */
  64
  65 static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
  66 {
  67    GLboolean  is_clamp = GL_FALSE;
  68    GLboolean  is_clamp_to_border = GL_FALSE;
  69
  70    t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D);
  71
  72    switch ( swrap ) {
  73    case GL_REPEAT:
  74       t->pp_txfilter |= RADEON_CLAMP_S_WRAP;
  75       break;
  76    case GL_CLAMP:
  77       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
  78       is_clamp = GL_TRUE;
  79       break;
  80    case GL_CLAMP_TO_EDGE:
  81       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST;
  82       break;
  83    case GL_CLAMP_TO_BORDER:
  84       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
  85       is_clamp_to_border = GL_TRUE;
  86       break;
  87    case GL_MIRRORED_REPEAT:
  88       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR;
  89       break;
  90    case GL_MIRROR_CLAMP_EXT:
  91       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
  92       is_clamp = GL_TRUE;
  93       break;
  94    case GL_MIRROR_CLAMP_TO_EDGE_EXT:
  95       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST;
  96       break;
  97    case GL_MIRROR_CLAMP_TO_BORDER_EXT:
  98       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
  99       is_clamp_to_border = GL_TRUE;
 100       break;
 101    default:
 102       _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
 103    }
 104
 105    switch ( twrap ) {
 106    case GL_REPEAT:
 107       t->pp_txfilter |= RADEON_CLAMP_T_WRAP;
 108       break;
 109    case GL_CLAMP:
 110       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
 111       is_clamp = GL_TRUE;
 112       break;
 113    case GL_CLAMP_TO_EDGE:
 114       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST;
 115       break;
 116    case GL_CLAMP_TO_BORDER:
 117       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
 118       is_clamp_to_border = GL_TRUE;
 119       break;
 120    case GL_MIRRORED_REPEAT:
 121       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR;
 122       break;
 123    case GL_MIRROR_CLAMP_EXT:
 124       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
 125       is_clamp = GL_TRUE;
 126       break;
 127    case GL_MIRROR_CLAMP_TO_EDGE_EXT:
 128       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST;
 129       break;
 130    case GL_MIRROR_CLAMP_TO_BORDER_EXT:
 131       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
 132       is_clamp_to_border = GL_TRUE;
 133       break;
 134    default:
 135       _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
 136    }
 137
 138    if ( is_clamp_to_border ) {
 139       t->pp_txfilter |= RADEON_BORDER_MODE_D3D;
 140    }
 141
 142    t->border_fallback = (is_clamp && is_clamp_to_border);
 143 }
 144
 145 static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
 146 {
 147    t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK;
 148
 149    if ( max == 1.0 ) {
 150       t->pp_txfilter |= RADEON_MAX_ANISO_1_TO_1;
 151    } else if ( max <= 2.0 ) {
 152       t->pp_txfilter |= RADEON_MAX_ANISO_2_TO_1;
 153    } else if ( max <= 4.0 ) {
 154       t->pp_txfilter |= RADEON_MAX_ANISO_4_TO_1;
 155    } else if ( max <= 8.0 ) {
 156       t->pp_txfilter |= RADEON_MAX_ANISO_8_TO_1;
 157    } else {
 158       t->pp_txfilter |= RADEON_MAX_ANISO_16_TO_1;
 159    }
 160 }
 161
 162 /**
 163  * Set the texture magnification and minification modes.
 164  *
 165  * \param t Texture whose filter modes are to be set
 166  * \param minf Texture minification mode
 167  * \param magf Texture magnification mode
 168  */
 169
 170 static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
 171 {
 172    GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK);
 173
 174    t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK);
 175
 176    /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */
 177    if ( t->base.Target == GL_TEXTURE_CUBE_MAP ) {
 178       switch ( minf ) {
 179       case GL_NEAREST:
 180       case GL_NEAREST_MIPMAP_NEAREST:
 181       case GL_NEAREST_MIPMAP_LINEAR:
 182          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
 183          break;
 184       case GL_LINEAR:
 185       case GL_LINEAR_MIPMAP_NEAREST:
 186       case GL_LINEAR_MIPMAP_LINEAR:
 187          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
 188          break;
 189       default:
 190          break;
 191       }
 192    }
 193    else if ( anisotropy == RADEON_MAX_ANISO_1_TO_1 ) {
 194       switch ( minf ) {
 195       case GL_NEAREST:
 196          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
 197          break;
 198       case GL_LINEAR:
 199          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
 200          break;
 201       case GL_NEAREST_MIPMAP_NEAREST:
 202          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST;
 203          break;
 204       case GL_NEAREST_MIPMAP_LINEAR:
 205          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST;
 206          break;
 207       case GL_LINEAR_MIPMAP_NEAREST:
 208          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR;
 209          break;
 210       case GL_LINEAR_MIPMAP_LINEAR:
 211          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR;
 212          break;
 213       }
 214    } else {
 215       switch ( minf ) {
 216       case GL_NEAREST:
 217          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST;
 218          break;
 219       case GL_LINEAR:
 220          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_LINEAR;
 221          break;
 222       case GL_NEAREST_MIPMAP_NEAREST:
 223       case GL_LINEAR_MIPMAP_NEAREST:
 224          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST;
 225          break;
 226       case GL_NEAREST_MIPMAP_LINEAR:
 227       case GL_LINEAR_MIPMAP_LINEAR:
 228          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR;
 229          break;
 230       }
 231    }
 232
 233    switch ( magf ) {
 234    case GL_NEAREST:
 235       t->pp_txfilter |= RADEON_MAG_FILTER_NEAREST;
 236       break;
 237    case GL_LINEAR:
 238       t->pp_txfilter |= RADEON_MAG_FILTER_LINEAR;
 239       break;
 240    }
 241 }
 242
 243 static void radeonSetTexBorderColor( radeonTexObjPtr t, GLubyte c[4] )
 244 {
 245    t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
 246 }
 247
 248 #define SCALED_FLOAT_TO_BYTE( x, scale ) \
 249                 (((GLuint)((255.0F / scale) * (x))) / 2)
 250
 251 static void radeonTexEnv( GLcontext *ctx, GLenum target,
 252                           GLenum pname, const GLfloat *param )
 253 {
 254    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 255    GLuint unit = ctx->Texture.CurrentUnit;
 256    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
 257
 258    if ( RADEON_DEBUG & DEBUG_STATE ) {
 259       fprintf( stderr, "%s( %s )\n",
 260                __FUNCTION__, _mesa_lookup_enum_by_nr( pname ) );
 261    }
 262
 263    switch ( pname ) {
 264    case GL_TEXTURE_ENV_COLOR: {
 265       GLubyte c[4];
 266       GLuint envColor;
 267       UNCLAMPED_FLOAT_TO_RGBA_CHAN( c, texUnit->EnvColor );
 268       envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
 269       if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) {
 270          RADEON_STATECHANGE( rmesa, tex[unit] );
 271          rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor;
 272       }
 273       break;
 274    }
 275
 276    case GL_TEXTURE_LOD_BIAS_EXT: {
 277       GLfloat bias, min;
 278       GLuint b;
 279
 280       /* The Radeon's LOD bias is a signed 2's complement value with a
 281        * range of -1.0 <= bias < 4.0.  We break this into two linear
 282        * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
 283        * [0.0,4.0] to [0,127].
 284        */
 285       min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ?
 286           0.0 : -1.0;
 287       bias = CLAMP( *param, min, 4.0 );
 288       if ( bias == 0 ) {
 289          b = 0;
 290       } else if ( bias > 0 ) {
 291          b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 4.0 )) << RADEON_LOD_BIAS_SHIFT;
 292       } else {
 293          b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 1.0 )) << RADEON_LOD_BIAS_SHIFT;
 294       }
 295       if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) {
 296          RADEON_STATECHANGE( rmesa, tex[unit] );
 297          rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK;
 298          rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK);
 299       }
 300       break;
 301    }
 302
 303    default:
 304       return;
 305    }
 306 }
 307
 308
 309 /**
 310  * Changes variables and flags for a state update, which will happen at the
 311  * next UpdateTextureState
 312  */
 313
 314 static void radeonTexParameter( GLcontext *ctx, GLenum target,
 315                                 struct gl_texture_object *texObj,
 316                                 GLenum pname, const GLfloat *params )
 317 {
 318    radeonTexObjPtr t = (radeonTexObjPtr) texObj->DriverData;
 319
 320    if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
 321       fprintf( stderr, "%s( %s )\n", __FUNCTION__,
 322                _mesa_lookup_enum_by_nr( pname ) );
 323    }
 324
 325    switch ( pname ) {
 326    case GL_TEXTURE_MIN_FILTER:
 327    case GL_TEXTURE_MAG_FILTER:
 328    case GL_TEXTURE_MAX_ANISOTROPY_EXT:
 329       radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
 330       radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
 331       break;
 332
 333    case GL_TEXTURE_WRAP_S:
 334    case GL_TEXTURE_WRAP_T:
 335       radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
 336       break;
 337
 338    case GL_TEXTURE_BORDER_COLOR:
 339       radeonSetTexBorderColor( t, texObj->_BorderChan );
 340       break;
 341
 342    case GL_TEXTURE_BASE_LEVEL:
 343    case GL_TEXTURE_MAX_LEVEL:
 344    case GL_TEXTURE_MIN_LOD:
 345    case GL_TEXTURE_MAX_LOD:
 346       /* This isn't the most efficient solution but there doesn't appear to
 347        * be a nice alternative.  Since there's no LOD clamping,
 348        * we just have to rely on loading the right subset of mipmap levels
 349        * to simulate a clamped LOD.
 350        */
 351       driSwapOutTextureObject( (driTextureObject *) t );
 352       break;
 353
 354    default:
 355       return;
 356    }
 357
 358    /* Mark this texobj as dirty (one bit per tex unit)
 359     */
 360    t->dirty_state = R100_TEX_ALL;
 361 }
 362
 363 static void radeonDeleteTexture( GLcontext *ctx,
 364                                  struct gl_texture_object *texObj )
 365 {
 366    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 367    radeonTexObj* t = radeon_tex_obj(texObj);
 368
 369    if ( RADEON_DEBUG & (DEBUG_STATE|DEBUG_TEXTURE) ) {
 370       fprintf( stderr, "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj,
 371                _mesa_lookup_enum_by_nr( texObj->Target ) );
 372    }
 373
 374    if ( rmesa ) {
 375      RADEON_FIREVERTICES( rmesa );
 376
 377    }
 378
 379    if (t->mt) {
 380       radeon_miptree_unreference(t->mt);
 381       t->mt = 0;
 382    }
 383    /* Free mipmap images and the texture object itself */
 384    _mesa_delete_texture_object(ctx, texObj);
 385 }
 386
 387 /* Need:
 388  *  - Same GEN_MODE for all active bits
 389  *  - Same EyePlane/ObjPlane for all active bits when using Eye/Obj
 390  *  - STRQ presumably all supported (matrix means incoming R values
 391  *    can end up in STQ, this has implications for vertex support,
 392  *    presumably ok if maos is used, though?)
 393  *
 394  * Basically impossible to do this on the fly - just collect some
 395  * basic info & do the checks from ValidateState().
 396  */
 397 static void radeonTexGen( GLcontext *ctx,
 398                           GLenum coord,
 399                           GLenum pname,
 400                           const GLfloat *params )
 401 {
 402    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 403    GLuint unit = ctx->Texture.CurrentUnit;
 404    rmesa->recheck_texgen[unit] = GL_TRUE;
 405 }
 406
 407 /**
 408  * Allocate a new texture object.
 409  * Called via ctx->Driver.NewTextureObject.
 410  * Note: we could use containment here to 'derive' the driver-specific
 411  * texture object from the core mesa gl_texture_object.  Not done at this time.
 412  */
 413 static struct gl_texture_object *
 414 radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target )
 415 {
 416    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 417    radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
 418
 419    _mesa_initialize_texture_object(&t->base, name, target);
 420    t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
 421
 422    t->border_fallback = GL_FALSE;
 423
 424    t->pp_txfilter = RADEON_BORDER_MODE_OGL;
 425    t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
 426                      RADEON_TXFORMAT_PERSPECTIVE_ENABLE);
 427
 428    radeonSetTexWrap( t, t->base.WrapS, t->base.WrapT );
 429    radeonSetTexMaxAnisotropy( t, t->base.MaxAnisotropy );
 430    radeonSetTexFilter( t, t->base.MinFilter, t->base.MagFilter );
 431    radeonSetTexBorderColor( t, t->base._BorderChan );
 432    return &t->base;
 433 }
 434
 435
 436
 437 void radeonInitTextureFuncs( struct dd_function_table *functions )
 438 {
 439    functions->ChooseTextureFormat       = radeonChooseTextureFormat;
 440    functions->TexImage1D                = radeonTexImage1D;
 441    functions->TexImage2D                = radeonTexImage2D;
 442    functions->TexSubImage1D             = radeonTexSubImage1D;
 443    functions->TexSubImage2D             = radeonTexSubImage2D;
 444
 445    functions->NewTextureObject          = radeonNewTextureObject;
 446    //   functions->BindTexture          = radeonBindTexture;
 447    functions->DeleteTexture             = radeonDeleteTexture;
 448    functions->IsTextureResident         = driIsTextureResident;
 449
 450    functions->TexEnv                    = radeonTexEnv;
 451    functions->TexParameter              = radeonTexParameter;
 452    functions->TexGen                    = radeonTexGen;
 453
 454    functions->CompressedTexImage2D      = radeonCompressedTexImage2D;
 455    functions->CompressedTexSubImage2D   = radeonCompressedTexSubImage2D;
 456
 457    functions->GenerateMipmap = radeonGenerateMipmap;
 458
 459    functions->NewTextureImage = radeonNewTextureImage;
 460    functions->FreeTexImageData = radeonFreeTexImageData;
 461    functions->MapTexture = radeonMapTexture;
 462    functions->UnmapTexture = radeonUnmapTexture;
 463
 464    driInitTextureFormats();
 465 }