src/mesa/drivers/dri/radeon/radeon_tex.c

   1 /*
   2 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   3                      VA Linux Systems Inc., Fremont, California.
   4
   5 All Rights Reserved.
   6
   7 Permission is hereby granted, free of charge, to any person obtaining
   8 a copy of this software and associated documentation files (the
   9 "Software"), to deal in the Software without restriction, including
  10 without limitation the rights to use, copy, modify, merge, publish,
  11 distribute, sublicense, and/or sell copies of the Software, and to
  12 permit persons to whom the Software is furnished to do so, subject to
  13 the following conditions:
  14
  15 The above copyright notice and this permission notice (including the
  16 next paragraph) shall be included in all copies or substantial
  17 portions of the Software.
  18
  19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26 */
  27
  28 /*
  29  * Authors:
  30  *    Gareth Hughes <gareth@valinux.com>
  31  *    Brian Paul <brianp@valinux.com>
  32  */
  33
  34 #include "main/glheader.h"
  35 #include "main/imports.h"
  36 #include "main/colormac.h"
  37 #include "main/context.h"
  38 #include "main/enums.h"
  39 #include "main/image.h"
  40 #include "main/simple_list.h"
  41 #include "main/texformat.h"
  42 #include "main/texstore.h"
  43 #include "main/teximage.h"
  44 #include "main/texobj.h"
  45
  46 #include "radeon_context.h"
  47 #include "radeon_mipmap_tree.h"
  48 #include "radeon_state.h"
  49 #include "radeon_ioctl.h"
  50 #include "radeon_swtcl.h"
  51 #include "radeon_tex.h"
  52
  53 #include "xmlpool.h"
  54
  55
  56
  57 /**
  58  * Set the texture wrap modes.
  59  *
  60  * \param t Texture object whose wrap modes are to be set
  61  * \param swrap Wrap mode for the \a s texture coordinate
  62  * \param twrap Wrap mode for the \a t texture coordinate
  63  */
  64
  65 static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
  66 {
  67    GLboolean  is_clamp = GL_FALSE;
  68    GLboolean  is_clamp_to_border = GL_FALSE;
  69
  70    t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D);
  71
  72    switch ( swrap ) {
  73    case GL_REPEAT:
  74       t->pp_txfilter |= RADEON_CLAMP_S_WRAP;
  75       break;
  76    case GL_CLAMP:
  77       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
  78       is_clamp = GL_TRUE;
  79       break;
  80    case GL_CLAMP_TO_EDGE:
  81       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST;
  82       break;
  83    case GL_CLAMP_TO_BORDER:
  84       t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
  85       is_clamp_to_border = GL_TRUE;
  86       break;
  87    case GL_MIRRORED_REPEAT:
  88       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR;
  89       break;
  90    case GL_MIRROR_CLAMP_EXT:
  91       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
  92       is_clamp = GL_TRUE;
  93       break;
  94    case GL_MIRROR_CLAMP_TO_EDGE_EXT:
  95       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST;
  96       break;
  97    case GL_MIRROR_CLAMP_TO_BORDER_EXT:
  98       t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
  99       is_clamp_to_border = GL_TRUE;
 100       break;
 101    default:
 102       _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
 103    }
 104
 105    switch ( twrap ) {
 106    case GL_REPEAT:
 107       t->pp_txfilter |= RADEON_CLAMP_T_WRAP;
 108       break;
 109    case GL_CLAMP:
 110       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
 111       is_clamp = GL_TRUE;
 112       break;
 113    case GL_CLAMP_TO_EDGE:
 114       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST;
 115       break;
 116    case GL_CLAMP_TO_BORDER:
 117       t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
 118       is_clamp_to_border = GL_TRUE;
 119       break;
 120    case GL_MIRRORED_REPEAT:
 121       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR;
 122       break;
 123    case GL_MIRROR_CLAMP_EXT:
 124       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
 125       is_clamp = GL_TRUE;
 126       break;
 127    case GL_MIRROR_CLAMP_TO_EDGE_EXT:
 128       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST;
 129       break;
 130    case GL_MIRROR_CLAMP_TO_BORDER_EXT:
 131       t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
 132       is_clamp_to_border = GL_TRUE;
 133       break;
 134    default:
 135       _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
 136    }
 137
 138    if ( is_clamp_to_border ) {
 139       t->pp_txfilter |= RADEON_BORDER_MODE_D3D;
 140    }
 141
 142    t->border_fallback = (is_clamp && is_clamp_to_border);
 143 }
 144
 145 static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
 146 {
 147    t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK;
 148
 149    if ( max == 1.0 ) {
 150       t->pp_txfilter |= RADEON_MAX_ANISO_1_TO_1;
 151    } else if ( max <= 2.0 ) {
 152       t->pp_txfilter |= RADEON_MAX_ANISO_2_TO_1;
 153    } else if ( max <= 4.0 ) {
 154       t->pp_txfilter |= RADEON_MAX_ANISO_4_TO_1;
 155    } else if ( max <= 8.0 ) {
 156       t->pp_txfilter |= RADEON_MAX_ANISO_8_TO_1;
 157    } else {
 158       t->pp_txfilter |= RADEON_MAX_ANISO_16_TO_1;
 159    }
 160 }
 161
 162 /**
 163  * Set the texture magnification and minification modes.
 164  *
 165  * \param t Texture whose filter modes are to be set
 166  * \param minf Texture minification mode
 167  * \param magf Texture magnification mode
 168  */
 169
 170 static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
 171 {
 172    GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK);
 173
 174    /* Force revalidation to account for switches from/to mipmapping. */
 175    t->validated = GL_FALSE;
 176
 177    t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK);
 178
 179    /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */
 180    if ( t->base.Target == GL_TEXTURE_CUBE_MAP ) {
 181       switch ( minf ) {
 182       case GL_NEAREST:
 183       case GL_NEAREST_MIPMAP_NEAREST:
 184       case GL_NEAREST_MIPMAP_LINEAR:
 185          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
 186          break;
 187       case GL_LINEAR:
 188       case GL_LINEAR_MIPMAP_NEAREST:
 189       case GL_LINEAR_MIPMAP_LINEAR:
 190          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
 191          break;
 192       default:
 193          break;
 194       }
 195    }
 196    else if ( anisotropy == RADEON_MAX_ANISO_1_TO_1 ) {
 197       switch ( minf ) {
 198       case GL_NEAREST:
 199          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
 200          break;
 201       case GL_LINEAR:
 202          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
 203          break;
 204       case GL_NEAREST_MIPMAP_NEAREST:
 205          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST;
 206          break;
 207       case GL_NEAREST_MIPMAP_LINEAR:
 208          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST;
 209          break;
 210       case GL_LINEAR_MIPMAP_NEAREST:
 211          t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR;
 212          break;
 213       case GL_LINEAR_MIPMAP_LINEAR:
 214          t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR;
 215          break;
 216       }
 217    } else {
 218       switch ( minf ) {
 219       case GL_NEAREST:
 220          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST;
 221          break;
 222       case GL_LINEAR:
 223          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_LINEAR;
 224          break;
 225       case GL_NEAREST_MIPMAP_NEAREST:
 226       case GL_LINEAR_MIPMAP_NEAREST:
 227          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST;
 228          break;
 229       case GL_NEAREST_MIPMAP_LINEAR:
 230       case GL_LINEAR_MIPMAP_LINEAR:
 231          t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR;
 232          break;
 233       }
 234    }
 235
 236    switch ( magf ) {
 237    case GL_NEAREST:
 238       t->pp_txfilter |= RADEON_MAG_FILTER_NEAREST;
 239       break;
 240    case GL_LINEAR:
 241       t->pp_txfilter |= RADEON_MAG_FILTER_LINEAR;
 242       break;
 243    }
 244 }
 245
 246 static void radeonSetTexBorderColor( radeonTexObjPtr t, const GLfloat color[4] )
 247 {
 248    GLubyte c[4];
 249    CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
 250    CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
 251    CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
 252    CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
 253    t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
 254 }
 255
 256 #define SCALED_FLOAT_TO_BYTE( x, scale ) \
 257                 (((GLuint)((255.0F / scale) * (x))) / 2)
 258
 259 static void radeonTexEnv( GLcontext *ctx, GLenum target,
 260                           GLenum pname, const GLfloat *param )
 261 {
 262    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 263    GLuint unit = ctx->Texture.CurrentUnit;
 264    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
 265
 266    if ( RADEON_DEBUG & RADEON_STATE ) {
 267       fprintf( stderr, "%s( %s )\n",
 268                __FUNCTION__, _mesa_lookup_enum_by_nr( pname ) );
 269    }
 270
 271    switch ( pname ) {
 272    case GL_TEXTURE_ENV_COLOR: {
 273       GLubyte c[4];
 274       GLuint envColor;
 275       UNCLAMPED_FLOAT_TO_RGBA_CHAN( c, texUnit->EnvColor );
 276       envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
 277       if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) {
 278          RADEON_STATECHANGE( rmesa, tex[unit] );
 279          rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor;
 280       }
 281       break;
 282    }
 283
 284    case GL_TEXTURE_LOD_BIAS_EXT: {
 285       GLfloat bias, min;
 286       GLuint b;
 287
 288       /* The Radeon's LOD bias is a signed 2's complement value with a
 289        * range of -1.0 <= bias < 4.0.  We break this into two linear
 290        * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
 291        * [0.0,4.0] to [0,127].
 292        */
 293       min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ?
 294           0.0 : -1.0;
 295       bias = CLAMP( *param, min, 4.0 );
 296       if ( bias == 0 ) {
 297          b = 0;
 298       } else if ( bias > 0 ) {
 299          b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 4.0 )) << RADEON_LOD_BIAS_SHIFT;
 300       } else {
 301          b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 1.0 )) << RADEON_LOD_BIAS_SHIFT;
 302       }
 303       if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) {
 304          RADEON_STATECHANGE( rmesa, tex[unit] );
 305          rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK;
 306          rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK);
 307       }
 308       break;
 309    }
 310
 311    default:
 312       return;
 313    }
 314 }
 315
 316
 317 /**
 318  * Changes variables and flags for a state update, which will happen at the
 319  * next UpdateTextureState
 320  */
 321
 322 static void radeonTexParameter( GLcontext *ctx, GLenum target,
 323                                 struct gl_texture_object *texObj,
 324                                 GLenum pname, const GLfloat *params )
 325 {
 326    radeonTexObj* t = radeon_tex_obj(texObj);
 327
 328    radeon_print(RADEON_TEXTURE, RADEON_VERBOSE, "%s( %s )\n", __FUNCTION__,
 329                _mesa_lookup_enum_by_nr( pname ) );
 330
 331    switch ( pname ) {
 332    case GL_TEXTURE_MIN_FILTER:
 333    case GL_TEXTURE_MAG_FILTER:
 334    case GL_TEXTURE_MAX_ANISOTROPY_EXT:
 335       radeonSetTexMaxAnisotropy( t, texObj->MaxAnisotropy );
 336       radeonSetTexFilter( t, texObj->MinFilter, texObj->MagFilter );
 337       break;
 338
 339    case GL_TEXTURE_WRAP_S:
 340    case GL_TEXTURE_WRAP_T:
 341       radeonSetTexWrap( t, texObj->WrapS, texObj->WrapT );
 342       break;
 343
 344    case GL_TEXTURE_BORDER_COLOR:
 345       radeonSetTexBorderColor( t, texObj->BorderColor );
 346       break;
 347
 348    case GL_TEXTURE_BASE_LEVEL:
 349    case GL_TEXTURE_MAX_LEVEL:
 350    case GL_TEXTURE_MIN_LOD:
 351    case GL_TEXTURE_MAX_LOD:
 352
 353       /* This isn't the most efficient solution but there doesn't appear to
 354        * be a nice alternative.  Since there's no LOD clamping,
 355        * we just have to rely on loading the right subset of mipmap levels
 356        * to simulate a clamped LOD.
 357        */
 358       if (t->mt) {
 359          radeon_miptree_unreference(t->mt);
 360          t->mt = 0;
 361          t->validated = GL_FALSE;
 362       }
 363       break;
 364
 365    default:
 366       return;
 367    }
 368 }
 369
 370 static void radeonDeleteTexture( GLcontext *ctx,
 371                                  struct gl_texture_object *texObj )
 372 {
 373    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 374    radeonTexObj* t = radeon_tex_obj(texObj);
 375    int i;
 376
 377    radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
 378          "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj,
 379                _mesa_lookup_enum_by_nr( texObj->Target ) );
 380
 381    if ( rmesa ) {
 382      radeon_firevertices(&rmesa->radeon);
 383      for ( i = 0 ; i < rmesa->radeon.glCtx->Const.MaxTextureUnits ; i++ ) {
 384        if ( t == rmesa->state.texture.unit[i].texobj ) {
 385          rmesa->state.texture.unit[i].texobj = NULL;
 386          rmesa->hw.tex[i].dirty = GL_FALSE;
 387          rmesa->hw.cube[i].dirty = GL_FALSE;
 388        }
 389      }
 390    }
 391
 392    if (t->mt) {
 393       radeon_miptree_unreference(t->mt);
 394       t->mt = 0;
 395    }
 396    /* Free mipmap images and the texture object itself */
 397    _mesa_delete_texture_object(ctx, texObj);
 398 }
 399
 400 /* Need:
 401  *  - Same GEN_MODE for all active bits
 402  *  - Same EyePlane/ObjPlane for all active bits when using Eye/Obj
 403  *  - STRQ presumably all supported (matrix means incoming R values
 404  *    can end up in STQ, this has implications for vertex support,
 405  *    presumably ok if maos is used, though?)
 406  *
 407  * Basically impossible to do this on the fly - just collect some
 408  * basic info & do the checks from ValidateState().
 409  */
 410 static void radeonTexGen( GLcontext *ctx,
 411                           GLenum coord,
 412                           GLenum pname,
 413                           const GLfloat *params )
 414 {
 415    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 416    GLuint unit = ctx->Texture.CurrentUnit;
 417    rmesa->recheck_texgen[unit] = GL_TRUE;
 418 }
 419
 420 /**
 421  * Allocate a new texture object.
 422  * Called via ctx->Driver.NewTextureObject.
 423  * Note: we could use containment here to 'derive' the driver-specific
 424  * texture object from the core mesa gl_texture_object.  Not done at this time.
 425  */
 426 static struct gl_texture_object *
 427 radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target )
 428 {
 429    r100ContextPtr rmesa = R100_CONTEXT(ctx);
 430    radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
 431
 432    _mesa_initialize_texture_object(&t->base, name, target);
 433    t->base.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
 434
 435    t->border_fallback = GL_FALSE;
 436
 437    t->pp_txfilter = RADEON_BORDER_MODE_OGL;
 438    t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
 439                      RADEON_TXFORMAT_PERSPECTIVE_ENABLE);
 440
 441    radeonSetTexWrap( t, t->base.WrapS, t->base.WrapT );
 442    radeonSetTexMaxAnisotropy( t, t->base.MaxAnisotropy );
 443    radeonSetTexFilter( t, t->base.MinFilter, t->base.MagFilter );
 444    radeonSetTexBorderColor( t, t->base.BorderColor );
 445    return &t->base;
 446 }
 447
 448
 449
 450 void radeonInitTextureFuncs( struct dd_function_table *functions )
 451 {
 452    functions->ChooseTextureFormat       = radeonChooseTextureFormat_mesa;
 453    functions->TexImage1D                = radeonTexImage1D;
 454    functions->TexImage2D                = radeonTexImage2D;
 455    functions->TexSubImage1D             = radeonTexSubImage1D;
 456    functions->TexSubImage2D             = radeonTexSubImage2D;
 457    functions->GetTexImage               = radeonGetTexImage;
 458    functions->GetCompressedTexImage     = radeonGetCompressedTexImage;
 459
 460    functions->NewTextureObject          = radeonNewTextureObject;
 461    //   functions->BindTexture          = radeonBindTexture;
 462    functions->DeleteTexture             = radeonDeleteTexture;
 463
 464    functions->TexEnv                    = radeonTexEnv;
 465    functions->TexParameter              = radeonTexParameter;
 466    functions->TexGen                    = radeonTexGen;
 467
 468    functions->CompressedTexImage2D      = radeonCompressedTexImage2D;
 469    functions->CompressedTexSubImage2D   = radeonCompressedTexSubImage2D;
 470
 471    functions->GenerateMipmap = radeonGenerateMipmap;
 472
 473    functions->NewTextureImage = radeonNewTextureImage;
 474    functions->FreeTexImageData = radeonFreeTexImageData;
 475    functions->MapTexture = radeonMapTexture;
 476    functions->UnmapTexture = radeonUnmapTexture;
 477
 478    driInitTextureFormats();
 479 }