mesa: remove target param from ctx->Driver.TexParameter()
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_tex.c
1 /*
2 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
3 VA Linux Systems Inc., Fremont, California.
4
5 All Rights Reserved.
6
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
14
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
18
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 */
27
28 /*
29 * Authors:
30 * Gareth Hughes <gareth@valinux.com>
31 * Brian Paul <brianp@valinux.com>
32 */
33
34 #include "main/glheader.h"
35 #include "main/imports.h"
36 #include "main/colormac.h"
37 #include "main/context.h"
38 #include "main/enums.h"
39 #include "main/image.h"
40 #include "main/simple_list.h"
41 #include "main/teximage.h"
42 #include "main/texobj.h"
43
44 #include "radeon_context.h"
45 #include "radeon_mipmap_tree.h"
46 #include "radeon_ioctl.h"
47 #include "radeon_tex.h"
48
49 #include "xmlpool.h"
50
51
52
53 /**
54 * Set the texture wrap modes.
55 *
56 * \param t Texture object whose wrap modes are to be set
57 * \param swrap Wrap mode for the \a s texture coordinate
58 * \param twrap Wrap mode for the \a t texture coordinate
59 */
60
61 static void radeonSetTexWrap( radeonTexObjPtr t, GLenum swrap, GLenum twrap )
62 {
63 GLboolean is_clamp = GL_FALSE;
64 GLboolean is_clamp_to_border = GL_FALSE;
65
66 t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D);
67
68 switch ( swrap ) {
69 case GL_REPEAT:
70 t->pp_txfilter |= RADEON_CLAMP_S_WRAP;
71 break;
72 case GL_CLAMP:
73 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
74 is_clamp = GL_TRUE;
75 break;
76 case GL_CLAMP_TO_EDGE:
77 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST;
78 break;
79 case GL_CLAMP_TO_BORDER:
80 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL;
81 is_clamp_to_border = GL_TRUE;
82 break;
83 case GL_MIRRORED_REPEAT:
84 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR;
85 break;
86 case GL_MIRROR_CLAMP_EXT:
87 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
88 is_clamp = GL_TRUE;
89 break;
90 case GL_MIRROR_CLAMP_TO_EDGE_EXT:
91 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST;
92 break;
93 case GL_MIRROR_CLAMP_TO_BORDER_EXT:
94 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL;
95 is_clamp_to_border = GL_TRUE;
96 break;
97 default:
98 _mesa_problem(NULL, "bad S wrap mode in %s", __FUNCTION__);
99 }
100
101 if (t->base.Target != GL_TEXTURE_1D) {
102 switch ( twrap ) {
103 case GL_REPEAT:
104 t->pp_txfilter |= RADEON_CLAMP_T_WRAP;
105 break;
106 case GL_CLAMP:
107 t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
108 is_clamp = GL_TRUE;
109 break;
110 case GL_CLAMP_TO_EDGE:
111 t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_LAST;
112 break;
113 case GL_CLAMP_TO_BORDER:
114 t->pp_txfilter |= RADEON_CLAMP_T_CLAMP_GL;
115 is_clamp_to_border = GL_TRUE;
116 break;
117 case GL_MIRRORED_REPEAT:
118 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR;
119 break;
120 case GL_MIRROR_CLAMP_EXT:
121 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
122 is_clamp = GL_TRUE;
123 break;
124 case GL_MIRROR_CLAMP_TO_EDGE_EXT:
125 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_LAST;
126 break;
127 case GL_MIRROR_CLAMP_TO_BORDER_EXT:
128 t->pp_txfilter |= RADEON_CLAMP_T_MIRROR_CLAMP_GL;
129 is_clamp_to_border = GL_TRUE;
130 break;
131 default:
132 _mesa_problem(NULL, "bad T wrap mode in %s", __FUNCTION__);
133 }
134 }
135
136 if ( is_clamp_to_border ) {
137 t->pp_txfilter |= RADEON_BORDER_MODE_D3D;
138 }
139
140 t->border_fallback = (is_clamp && is_clamp_to_border);
141 }
142
143 static void radeonSetTexMaxAnisotropy( radeonTexObjPtr t, GLfloat max )
144 {
145 t->pp_txfilter &= ~RADEON_MAX_ANISO_MASK;
146
147 if ( max == 1.0 ) {
148 t->pp_txfilter |= RADEON_MAX_ANISO_1_TO_1;
149 } else if ( max <= 2.0 ) {
150 t->pp_txfilter |= RADEON_MAX_ANISO_2_TO_1;
151 } else if ( max <= 4.0 ) {
152 t->pp_txfilter |= RADEON_MAX_ANISO_4_TO_1;
153 } else if ( max <= 8.0 ) {
154 t->pp_txfilter |= RADEON_MAX_ANISO_8_TO_1;
155 } else {
156 t->pp_txfilter |= RADEON_MAX_ANISO_16_TO_1;
157 }
158 }
159
160 /**
161 * Set the texture magnification and minification modes.
162 *
163 * \param t Texture whose filter modes are to be set
164 * \param minf Texture minification mode
165 * \param magf Texture magnification mode
166 */
167
168 static void radeonSetTexFilter( radeonTexObjPtr t, GLenum minf, GLenum magf )
169 {
170 GLuint anisotropy = (t->pp_txfilter & RADEON_MAX_ANISO_MASK);
171
172 /* Force revalidation to account for switches from/to mipmapping. */
173 t->validated = GL_FALSE;
174
175 t->pp_txfilter &= ~(RADEON_MIN_FILTER_MASK | RADEON_MAG_FILTER_MASK);
176
177 /* r100 chips can't handle mipmaps/aniso for cubemap/volume textures */
178 if ( t->base.Target == GL_TEXTURE_CUBE_MAP ) {
179 switch ( minf ) {
180 case GL_NEAREST:
181 case GL_NEAREST_MIPMAP_NEAREST:
182 case GL_NEAREST_MIPMAP_LINEAR:
183 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
184 break;
185 case GL_LINEAR:
186 case GL_LINEAR_MIPMAP_NEAREST:
187 case GL_LINEAR_MIPMAP_LINEAR:
188 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
189 break;
190 default:
191 break;
192 }
193 }
194 else if ( anisotropy == RADEON_MAX_ANISO_1_TO_1 ) {
195 switch ( minf ) {
196 case GL_NEAREST:
197 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST;
198 break;
199 case GL_LINEAR:
200 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR;
201 break;
202 case GL_NEAREST_MIPMAP_NEAREST:
203 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_NEAREST;
204 break;
205 case GL_NEAREST_MIPMAP_LINEAR:
206 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_NEAREST;
207 break;
208 case GL_LINEAR_MIPMAP_NEAREST:
209 t->pp_txfilter |= RADEON_MIN_FILTER_NEAREST_MIP_LINEAR;
210 break;
211 case GL_LINEAR_MIPMAP_LINEAR:
212 t->pp_txfilter |= RADEON_MIN_FILTER_LINEAR_MIP_LINEAR;
213 break;
214 }
215 } else {
216 switch ( minf ) {
217 case GL_NEAREST:
218 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST;
219 break;
220 case GL_LINEAR:
221 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_LINEAR;
222 break;
223 case GL_NEAREST_MIPMAP_NEAREST:
224 case GL_LINEAR_MIPMAP_NEAREST:
225 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST;
226 break;
227 case GL_NEAREST_MIPMAP_LINEAR:
228 case GL_LINEAR_MIPMAP_LINEAR:
229 t->pp_txfilter |= RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR;
230 break;
231 }
232 }
233
234 switch ( magf ) {
235 case GL_NEAREST:
236 t->pp_txfilter |= RADEON_MAG_FILTER_NEAREST;
237 break;
238 case GL_LINEAR:
239 t->pp_txfilter |= RADEON_MAG_FILTER_LINEAR;
240 break;
241 }
242 }
243
244 static void radeonSetTexBorderColor( radeonTexObjPtr t, const GLfloat color[4] )
245 {
246 GLubyte c[4];
247 CLAMPED_FLOAT_TO_UBYTE(c[0], color[0]);
248 CLAMPED_FLOAT_TO_UBYTE(c[1], color[1]);
249 CLAMPED_FLOAT_TO_UBYTE(c[2], color[2]);
250 CLAMPED_FLOAT_TO_UBYTE(c[3], color[3]);
251 t->pp_border_color = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
252 }
253
254 #define SCALED_FLOAT_TO_BYTE( x, scale ) \
255 (((GLuint)((255.0F / scale) * (x))) / 2)
256
257 static void radeonTexEnv( struct gl_context *ctx, GLenum target,
258 GLenum pname, const GLfloat *param )
259 {
260 r100ContextPtr rmesa = R100_CONTEXT(ctx);
261 GLuint unit = ctx->Texture.CurrentUnit;
262 struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
263
264 if ( RADEON_DEBUG & RADEON_STATE ) {
265 fprintf( stderr, "%s( %s )\n",
266 __FUNCTION__, _mesa_lookup_enum_by_nr( pname ) );
267 }
268
269 switch ( pname ) {
270 case GL_TEXTURE_ENV_COLOR: {
271 GLubyte c[4];
272 GLuint envColor;
273 _mesa_unclamped_float_rgba_to_ubyte(c, texUnit->EnvColor);
274 envColor = radeonPackColor( 4, c[0], c[1], c[2], c[3] );
275 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] != envColor ) {
276 RADEON_STATECHANGE( rmesa, tex[unit] );
277 rmesa->hw.tex[unit].cmd[TEX_PP_TFACTOR] = envColor;
278 }
279 break;
280 }
281
282 case GL_TEXTURE_LOD_BIAS_EXT: {
283 GLfloat bias, min;
284 GLuint b;
285
286 /* The Radeon's LOD bias is a signed 2's complement value with a
287 * range of -1.0 <= bias < 4.0. We break this into two linear
288 * functions, one mapping [-1.0,0.0] to [-128,0] and one mapping
289 * [0.0,4.0] to [0,127].
290 */
291 min = driQueryOptionb (&rmesa->radeon.optionCache, "no_neg_lod_bias") ?
292 0.0 : -1.0;
293 bias = CLAMP( *param, min, 4.0 );
294 if ( bias == 0 ) {
295 b = 0;
296 } else if ( bias > 0 ) {
297 b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 4.0 )) << RADEON_LOD_BIAS_SHIFT;
298 } else {
299 b = ((GLuint)SCALED_FLOAT_TO_BYTE( bias, 1.0 )) << RADEON_LOD_BIAS_SHIFT;
300 }
301 if ( (rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] & RADEON_LOD_BIAS_MASK) != b ) {
302 RADEON_STATECHANGE( rmesa, tex[unit] );
303 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] &= ~RADEON_LOD_BIAS_MASK;
304 rmesa->hw.tex[unit].cmd[TEX_PP_TXFILTER] |= (b & RADEON_LOD_BIAS_MASK);
305 }
306 break;
307 }
308
309 default:
310 return;
311 }
312 }
313
314 void radeonTexUpdateParameters(struct gl_context *ctx, GLuint unit)
315 {
316 struct gl_sampler_object *samp = _mesa_get_samplerobj(ctx, unit);
317 radeonTexObj* t = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
318
319 radeonSetTexMaxAnisotropy(t , samp->MaxAnisotropy);
320 radeonSetTexFilter(t, samp->MinFilter, samp->MagFilter);
321 radeonSetTexWrap(t, samp->WrapS, samp->WrapT);
322 radeonSetTexBorderColor(t, samp->BorderColor.f);
323 }
324
325
326 /**
327 * Changes variables and flags for a state update, which will happen at the
328 * next UpdateTextureState
329 */
330
331 static void radeonTexParameter( struct gl_context *ctx,
332 struct gl_texture_object *texObj,
333 GLenum pname, const GLfloat *params )
334 {
335 radeonTexObj* t = radeon_tex_obj(texObj);
336
337 radeon_print(RADEON_TEXTURE, RADEON_VERBOSE, "%s( %s )\n", __FUNCTION__,
338 _mesa_lookup_enum_by_nr( pname ) );
339
340 switch ( pname ) {
341 case GL_TEXTURE_BASE_LEVEL:
342 case GL_TEXTURE_MAX_LEVEL:
343 case GL_TEXTURE_MIN_LOD:
344 case GL_TEXTURE_MAX_LOD:
345 t->validated = GL_FALSE;
346 break;
347
348 default:
349 return;
350 }
351 }
352
353 static void radeonDeleteTexture( struct gl_context *ctx,
354 struct gl_texture_object *texObj )
355 {
356 r100ContextPtr rmesa = R100_CONTEXT(ctx);
357 radeonTexObj* t = radeon_tex_obj(texObj);
358 int i;
359
360 radeon_print(RADEON_TEXTURE, RADEON_NORMAL,
361 "%s( %p (target = %s) )\n", __FUNCTION__, (void *)texObj,
362 _mesa_lookup_enum_by_nr( texObj->Target ) );
363
364 if ( rmesa ) {
365 radeon_firevertices(&rmesa->radeon);
366 for ( i = 0 ; i < rmesa->radeon.glCtx.Const.MaxTextureUnits ; i++ ) {
367 if ( t == rmesa->state.texture.unit[i].texobj ) {
368 rmesa->state.texture.unit[i].texobj = NULL;
369 rmesa->hw.tex[i].dirty = GL_FALSE;
370 rmesa->hw.cube[i].dirty = GL_FALSE;
371 }
372 }
373 }
374
375 radeon_miptree_unreference(&t->mt);
376
377 /* Free mipmap images and the texture object itself */
378 _mesa_delete_texture_object(ctx, texObj);
379 }
380
381 /* Need:
382 * - Same GEN_MODE for all active bits
383 * - Same EyePlane/ObjPlane for all active bits when using Eye/Obj
384 * - STRQ presumably all supported (matrix means incoming R values
385 * can end up in STQ, this has implications for vertex support,
386 * presumably ok if maos is used, though?)
387 *
388 * Basically impossible to do this on the fly - just collect some
389 * basic info & do the checks from ValidateState().
390 */
391 static void radeonTexGen( struct gl_context *ctx,
392 GLenum coord,
393 GLenum pname,
394 const GLfloat *params )
395 {
396 r100ContextPtr rmesa = R100_CONTEXT(ctx);
397 GLuint unit = ctx->Texture.CurrentUnit;
398 rmesa->recheck_texgen[unit] = GL_TRUE;
399 }
400
401 /**
402 * Allocate a new texture object.
403 * Called via ctx->Driver.NewTextureObject.
404 * Note: we could use containment here to 'derive' the driver-specific
405 * texture object from the core mesa gl_texture_object. Not done at this time.
406 */
407 static struct gl_texture_object *
408 radeonNewTextureObject( struct gl_context *ctx, GLuint name, GLenum target )
409 {
410 r100ContextPtr rmesa = R100_CONTEXT(ctx);
411 radeonTexObj* t = CALLOC_STRUCT(radeon_tex_obj);
412
413 _mesa_initialize_texture_object(ctx, &t->base, name, target);
414 t->base.Sampler.MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
415
416 t->border_fallback = GL_FALSE;
417
418 t->pp_txfilter = RADEON_BORDER_MODE_OGL;
419 t->pp_txformat = (RADEON_TXFORMAT_ENDIAN_NO_SWAP |
420 RADEON_TXFORMAT_PERSPECTIVE_ENABLE);
421
422 radeonSetTexWrap( t, t->base.Sampler.WrapS, t->base.Sampler.WrapT );
423 radeonSetTexMaxAnisotropy( t, t->base.Sampler.MaxAnisotropy );
424 radeonSetTexFilter( t, t->base.Sampler.MinFilter, t->base.Sampler.MagFilter );
425 radeonSetTexBorderColor( t, t->base.Sampler.BorderColor.f );
426 return &t->base;
427 }
428
429
430 static struct gl_sampler_object *
431 radeonNewSamplerObject(struct gl_context *ctx, GLuint name)
432 {
433 r100ContextPtr rmesa = R100_CONTEXT(ctx);
434 struct gl_sampler_object *samp = _mesa_new_sampler_object(ctx, name);
435 if (samp)
436 samp->MaxAnisotropy = rmesa->radeon.initialMaxAnisotropy;
437 return samp;
438 }
439
440
441 void radeonInitTextureFuncs( radeonContextPtr radeon, struct dd_function_table *functions )
442 {
443 radeon_init_common_texture_funcs(radeon, functions);
444
445 functions->NewTextureObject = radeonNewTextureObject;
446 // functions->BindTexture = radeonBindTexture;
447 functions->DeleteTexture = radeonDeleteTexture;
448
449 functions->TexEnv = radeonTexEnv;
450 functions->TexParameter = radeonTexParameter;
451 functions->TexGen = radeonTexGen;
452 functions->NewSamplerObject = radeonNewSamplerObject;
453 }