src/mesa/drivers/dri/radeon/radeon_texmem.c

   1 /**************************************************************************
   2
   3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   4                      VA Linux Systems Inc., Fremont, California.
   5
   6 All Rights Reserved.
   7
   8 Permission is hereby granted, free of charge, to any person obtaining
   9 a copy of this software and associated documentation files (the
  10 "Software"), to deal in the Software without restriction, including
  11 without limitation on the rights to use, copy, modify, merge, publish,
  12 distribute, sub license, and/or sell copies of the Software, and to
  13 permit persons to whom the Software is furnished to do so, subject to
  14 the following conditions:
  15
  16 The above copyright notice and this permission notice (including the
  17 next paragraph) shall be included in all copies or substantial
  18 portions of the Software.
  19
  20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  23 NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR
  24 SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  25 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
  26 IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  27 SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Kevin E. Martin <martin@valinux.com>
  34  *   Gareth Hughes <gareth@valinux.com>
  35  *
  36  */
  37 #include <errno.h>
  38
  39 #include "main/glheader.h"
  40 #include "main/imports.h"
  41 #include "main/context.h"
  42 #include "main/macros.h"
  43
  44 #include "radeon_context.h"
  45 #include "radeon_ioctl.h"
  46 #include "radeon_tex.h"
  47
  48 #include <unistd.h>  /* for usleep() */
  49
  50
  51 /**
  52  * Destroy any device-dependent state associated with the texture.  This may
  53  * include NULLing out hardware state that points to the texture.
  54  */
  55 void
  56 radeonDestroyTexObj( radeonContextPtr rmesa, radeonTexObjPtr t )
  57 {
  58    if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
  59       fprintf( stderr, "%s( %p, %p )\n", __FUNCTION__, (void *)t, (void *)t->base.tObj );
  60    }
  61
  62    if ( rmesa != NULL ) {
  63       unsigned   i;
  64
  65
  66       for ( i = 0 ; i < rmesa->glCtx->Const.MaxTextureUnits ; i++ ) {
  67          if ( t == rmesa->state.texture.unit[i].texobj ) {
  68             rmesa->state.texture.unit[i].texobj = NULL;
  69          }
  70       }
  71    }
  72 }
  73
  74
  75 /* ------------------------------------------------------------
  76  * Texture image conversions
  77  */
  78
  79
  80 static void radeonUploadRectSubImage( radeonContextPtr rmesa,
  81                                       radeonTexObjPtr t,
  82                                       struct gl_texture_image *texImage,
  83                                       GLint x, GLint y,
  84                                       GLint width, GLint height )
  85 {
  86    const struct gl_texture_format *texFormat = texImage->TexFormat;
  87    int blit_format, dstPitch, done;
  88
  89    switch ( texFormat->TexelBytes ) {
  90    case 1:
  91       blit_format = RADEON_GMC_DST_8BPP_CI;
  92       break;
  93    case 2:
  94       blit_format = RADEON_GMC_DST_16BPP;
  95       break;
  96    case 4:
  97       blit_format = RADEON_GMC_DST_32BPP;
  98       break;
  99    default:
 100       fprintf( stderr, "radeonUploadRectSubImage: unknown blit_format (texelbytes=%d)\n",
 101                texFormat->TexelBytes);
 102       return;
 103    }
 104
 105    t->image[0][0].data = texImage->Data;
 106
 107    /* Currently don't need to cope with small pitches.
 108     */
 109    width = texImage->Width;
 110    height = texImage->Height;
 111    dstPitch = t->pp_txpitch + 32;
 112
 113    {    /* FIXME: prefer GART-texturing if possible */
 114       /* Data not in GART memory, or bad pitch.
 115        */
 116       for (done = 0; done < height ; ) {
 117          struct radeon_dma_region region;
 118          int lines = MIN2( height - done, RADEON_BUFFER_SIZE / dstPitch );
 119          int src_pitch;
 120          char *tex;
 121
 122          src_pitch = texImage->RowStride * texFormat->TexelBytes;
 123
 124          tex = (char *)texImage->Data + done * src_pitch;
 125
 126          memset(&region, 0, sizeof(region));
 127          radeonAllocDmaRegion( rmesa, &region, lines * dstPitch, 1024 );
 128
 129          /* Copy texdata to dma:
 130           */
 131          if (0)
 132             fprintf(stderr, "%s: src_pitch %d dst_pitch %d\n",
 133                     __FUNCTION__, src_pitch, dstPitch);
 134
 135          if (src_pitch == dstPitch) {
 136             memcpy( region.address + region.start, tex, lines * src_pitch );
 137          }
 138          else {
 139             char *buf = region.address + region.start;
 140             int i;
 141             for (i = 0 ; i < lines ; i++) {
 142                memcpy( buf, tex, src_pitch );
 143                buf += dstPitch;
 144                tex += src_pitch;
 145             }
 146          }
 147
 148          radeonEmitWait( rmesa, RADEON_WAIT_3D );
 149
 150
 151
 152          /* Blit to framebuffer
 153           */
 154          radeonEmitBlit( rmesa,
 155                        blit_format,
 156                        dstPitch, GET_START( &region ),
 157                        dstPitch, t->bufAddr,
 158                        0, 0,
 159                        0, done,
 160                        width, lines );
 161
 162          radeonEmitWait( rmesa, RADEON_WAIT_2D );
 163
 164          radeonReleaseDmaRegion( rmesa, &region, __FUNCTION__ );
 165          done += lines;
 166       }
 167    }
 168 }
 169
 170
 171 /**
 172  * Upload the texture image associated with texture \a t at the specified
 173  * level at the address relative to \a start.
 174  */
 175 static void uploadSubImage( radeonContextPtr rmesa, radeonTexObjPtr t,
 176                             GLint hwlevel,
 177                             GLint x, GLint y, GLint width, GLint height,
 178                             GLuint face )
 179 {
 180    struct gl_texture_image *texImage = NULL;
 181    GLuint offset;
 182    GLint imageWidth, imageHeight;
 183    GLint ret;
 184    drm_radeon_texture_t tex;
 185    drm_radeon_tex_image_t tmp;
 186    const int level = hwlevel + t->base.firstLevel;
 187
 188    if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
 189       fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
 190                __FUNCTION__, (void *)t, (void *)t->base.tObj, level, width, height, face );
 191    }
 192
 193    ASSERT(face < 6);
 194
 195    /* Ensure we have a valid texture to upload */
 196    if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) {
 197       _mesa_problem(NULL, "bad texture level in %s", __FUNCTION__);
 198       return;
 199    }
 200
 201    texImage = t->base.tObj->Image[face][level];
 202
 203    if ( !texImage ) {
 204       if ( RADEON_DEBUG & DEBUG_TEXTURE )
 205          fprintf( stderr, "%s: texImage %d is NULL!\n", __FUNCTION__, level );
 206       return;
 207    }
 208    if ( !texImage->Data ) {
 209       if ( RADEON_DEBUG & DEBUG_TEXTURE )
 210          fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ );
 211       return;
 212    }
 213
 214
 215    if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
 216       assert(level == 0);
 217       assert(hwlevel == 0);
 218       if ( RADEON_DEBUG & DEBUG_TEXTURE )
 219          fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__);
 220       radeonUploadRectSubImage( rmesa, t, texImage, x, y, width, height );
 221       return;
 222    }
 223
 224    imageWidth = texImage->Width;
 225    imageHeight = texImage->Height;
 226
 227    offset = t->bufAddr + t->base.totalSize * face / 6;
 228
 229    if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
 230       GLint imageX = 0;
 231       GLint imageY = 0;
 232       GLint blitX = t->image[face][hwlevel].x;
 233       GLint blitY = t->image[face][hwlevel].y;
 234       GLint blitWidth = t->image[face][hwlevel].width;
 235       GLint blitHeight = t->image[face][hwlevel].height;
 236       fprintf( stderr, "   upload image: %d,%d at %d,%d\n",
 237                imageWidth, imageHeight, imageX, imageY );
 238       fprintf( stderr, "   upload  blit: %d,%d at %d,%d\n",
 239                blitWidth, blitHeight, blitX, blitY );
 240       fprintf( stderr, "       blit ofs: 0x%07x level: %d/%d\n",
 241                (GLuint)offset, hwlevel, level );
 242    }
 243
 244    t->image[face][hwlevel].data = texImage->Data;
 245
 246    /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
 247     * NOTE: we're always use a 1KB-wide blit and I8 texture format.
 248     * We used to use 1, 2 and 4-byte texels and used to use the texture
 249     * width to dictate the blit width - but that won't work for compressed
 250     * textures. (Brian)
 251     * NOTE: can't do that with texture tiling. (sroland)
 252     */
 253    tex.offset = offset;
 254    tex.image = &tmp;
 255    /* copy (x,y,width,height,data) */
 256    memcpy( &tmp, &t->image[face][hwlevel], sizeof(drm_radeon_tex_image_t) );
 257
 258    if (texImage->TexFormat->TexelBytes) {
 259       /* use multi-byte upload scheme */
 260       tex.height = imageHeight;
 261       tex.width = imageWidth;
 262       tex.format = t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK;
 263       tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1);
 264       tex.offset += tmp.x & ~1023;
 265       tmp.x = tmp.x % 1024;
 266       if (t->tile_bits & RADEON_TXO_MICRO_TILE_X2) {
 267          /* need something like "tiled coordinates" ? */
 268          tmp.y = tmp.x / (tex.pitch * 128) * 2;
 269          tmp.x = tmp.x % (tex.pitch * 128) / 2 / texImage->TexFormat->TexelBytes;
 270          tex.pitch |= RADEON_DST_TILE_MICRO >> 22;
 271       }
 272       else {
 273          tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1);
 274       }
 275       if ((t->tile_bits & RADEON_TXO_MACRO_TILE) &&
 276          (texImage->Width * texImage->TexFormat->TexelBytes >= 256)) {
 277          /* radeon switches off macro tiling for small textures/mipmaps it seems */
 278          tex.pitch |= RADEON_DST_TILE_MACRO >> 22;
 279       }
 280    }
 281    else {
 282       /* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is
 283          needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */
 284       /* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed
 285          so the kernel module reads the right amount of data. */
 286       tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */
 287       tex.pitch = (BLIT_WIDTH_BYTES / 64);
 288       tex.height = (imageHeight + 3) / 4;
 289       tex.width = (imageWidth + 3) / 4;
 290       switch (t->pp_txformat & RADEON_TXFORMAT_FORMAT_MASK) {
 291       case RADEON_TXFORMAT_DXT1:
 292          tex.width *= 8;
 293          break;
 294       case RADEON_TXFORMAT_DXT23:
 295       case RADEON_TXFORMAT_DXT45:
 296          tex.width *= 16;
 297          break;
 298       }
 299    }
 300
 301    LOCK_HARDWARE( rmesa );
 302    do {
 303       ret = drmCommandWriteRead( rmesa->dri.fd, DRM_RADEON_TEXTURE,
 304                                  &tex, sizeof(drm_radeon_texture_t) );
 305    } while ( ret == -EAGAIN );
 306
 307    UNLOCK_HARDWARE( rmesa );
 308
 309    if ( ret ) {
 310       fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret );
 311       fprintf( stderr, "   offset=0x%08x\n",
 312                offset );
 313       fprintf( stderr, "   image width=%d height=%d\n",
 314                imageWidth, imageHeight );
 315       fprintf( stderr, "    blit width=%d height=%d data=%p\n",
 316                t->image[face][hwlevel].width, t->image[face][hwlevel].height,
 317                t->image[face][hwlevel].data );
 318       exit( 1 );
 319    }
 320 }
 321
 322
 323 /**
 324  * Upload the texture images associated with texture \a t.  This might
 325  * require the allocation of texture memory.
 326  *
 327  * \param rmesa Context pointer
 328  * \param t Texture to be uploaded
 329  * \param face Cube map face to be uploaded.  Zero for non-cube maps.
 330  */
 331
 332 int radeonUploadTexImages( radeonContextPtr rmesa, radeonTexObjPtr t, GLuint face )
 333 {
 334    int numLevels;
 335
 336    if ( !t || t->base.totalSize == 0 || t->image_override )
 337       return 0;
 338
 339    if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
 340       fprintf( stderr, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__,
 341                (void *)rmesa->glCtx, (void *)t->base.tObj, t->base.totalSize,
 342                t->base.firstLevel, t->base.lastLevel );
 343    }
 344
 345    numLevels = t->base.lastLevel - t->base.firstLevel + 1;
 346
 347    if (RADEON_DEBUG & DEBUG_SYNC) {
 348       fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
 349       radeonFinish( rmesa->glCtx );
 350    }
 351
 352    LOCK_HARDWARE( rmesa );
 353
 354    if ( t->base.memBlock == NULL ) {
 355       int heap;
 356
 357       heap = driAllocateTexture( rmesa->texture_heaps, rmesa->nr_heaps,
 358                                  (driTextureObject *) t );
 359       if ( heap == -1 ) {
 360          UNLOCK_HARDWARE( rmesa );
 361          return -1;
 362       }
 363
 364       /* Set the base offset of the texture image */
 365       t->bufAddr = rmesa->radeonScreen->texOffset[heap]
 366            + t->base.memBlock->ofs;
 367       t->pp_txoffset = t->bufAddr;
 368
 369       if (!(t->base.tObj->Image[0][0]->IsClientData)) {
 370          /* hope it's safe to add that here... */
 371          t->pp_txoffset |= t->tile_bits;
 372       }
 373
 374       /* Mark this texobj as dirty on all units:
 375        */
 376       t->dirty_state = TEX_ALL;
 377    }
 378
 379
 380    /* Let the world know we've used this memory recently.
 381     */
 382    driUpdateTextureLRU( (driTextureObject *) t );
 383    UNLOCK_HARDWARE( rmesa );
 384
 385
 386    /* Upload any images that are new */
 387    if (t->base.dirty_images[face]) {
 388       int i;
 389       for ( i = 0 ; i < numLevels ; i++ ) {
 390          if ( (t->base.dirty_images[face] & (1 << (i+t->base.firstLevel))) != 0 ) {
 391             uploadSubImage( rmesa, t, i, 0, 0, t->image[face][i].width,
 392                             t->image[face][i].height, face );
 393          }
 394       }
 395       t->base.dirty_images[face] = 0;
 396    }
 397
 398    if (RADEON_DEBUG & DEBUG_SYNC) {
 399       fprintf(stderr, "%s: Syncing\n", __FUNCTION__ );
 400       radeonFinish( rmesa->glCtx );
 401    }
 402
 403    return 0;
 404 }