1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation on the rights to use, copy, modify, merge, publish,
12 distribute, sub license, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
23 NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR
24 SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
25 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
26 IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
39 #include "main/glheader.h"
40 #include "main/imports.h"
41 #include "main/context.h"
42 #include "main/macros.h"
44 #include "radeon_context.h"
45 #include "radeon_ioctl.h"
46 #include "radeon_tex.h"
48 #include <unistd.h> /* for usleep() */
52 * Destroy any device-dependent state associated with the texture. This may
53 * include NULLing out hardware state that points to the texture.
56 radeonDestroyTexObj( radeonContextPtr rmesa
, radeonTexObjPtr t
)
58 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
59 fprintf( stderr
, "%s( %p, %p )\n", __FUNCTION__
, (void *)t
, (void *)t
->base
.tObj
);
62 if ( rmesa
!= NULL
) {
66 for ( i
= 0 ; i
< rmesa
->glCtx
->Const
.MaxTextureUnits
; i
++ ) {
67 if ( t
== rmesa
->state
.texture
.unit
[i
].texobj
) {
68 rmesa
->state
.texture
.unit
[i
].texobj
= NULL
;
75 /* ------------------------------------------------------------
76 * Texture image conversions
80 static void radeonUploadRectSubImage( radeonContextPtr rmesa
,
82 struct gl_texture_image
*texImage
,
84 GLint width
, GLint height
)
86 const struct gl_texture_format
*texFormat
= texImage
->TexFormat
;
87 int blit_format
, dstPitch
, done
;
89 switch ( texFormat
->TexelBytes
) {
91 blit_format
= RADEON_GMC_DST_8BPP_CI
;
94 blit_format
= RADEON_GMC_DST_16BPP
;
97 blit_format
= RADEON_GMC_DST_32BPP
;
100 fprintf( stderr
, "radeonUploadRectSubImage: unknown blit_format (texelbytes=%d)\n",
101 texFormat
->TexelBytes
);
105 t
->image
[0][0].data
= texImage
->Data
;
107 /* Currently don't need to cope with small pitches.
109 width
= texImage
->Width
;
110 height
= texImage
->Height
;
111 dstPitch
= t
->pp_txpitch
+ 32;
113 { /* FIXME: prefer GART-texturing if possible */
114 /* Data not in GART memory, or bad pitch.
116 for (done
= 0; done
< height
; ) {
117 struct radeon_dma_region region
;
118 int lines
= MIN2( height
- done
, RADEON_BUFFER_SIZE
/ dstPitch
);
122 src_pitch
= texImage
->RowStride
* texFormat
->TexelBytes
;
124 tex
= (char *)texImage
->Data
+ done
* src_pitch
;
126 memset(®ion
, 0, sizeof(region
));
127 radeonAllocDmaRegion( rmesa
, ®ion
, lines
* dstPitch
, 1024 );
129 /* Copy texdata to dma:
132 fprintf(stderr
, "%s: src_pitch %d dst_pitch %d\n",
133 __FUNCTION__
, src_pitch
, dstPitch
);
135 if (src_pitch
== dstPitch
) {
136 memcpy( region
.address
+ region
.start
, tex
, lines
* src_pitch
);
139 char *buf
= region
.address
+ region
.start
;
141 for (i
= 0 ; i
< lines
; i
++) {
142 memcpy( buf
, tex
, src_pitch
);
148 radeonEmitWait( rmesa
, RADEON_WAIT_3D
);
152 /* Blit to framebuffer
154 radeonEmitBlit( rmesa
,
156 dstPitch
, GET_START( ®ion
),
157 dstPitch
, t
->bufAddr
,
162 radeonEmitWait( rmesa
, RADEON_WAIT_2D
);
164 radeonReleaseDmaRegion( rmesa
, ®ion
, __FUNCTION__
);
172 * Upload the texture image associated with texture \a t at the specified
173 * level at the address relative to \a start.
175 static void uploadSubImage( radeonContextPtr rmesa
, radeonTexObjPtr t
,
177 GLint x
, GLint y
, GLint width
, GLint height
,
180 struct gl_texture_image
*texImage
= NULL
;
182 GLint imageWidth
, imageHeight
;
184 drm_radeon_texture_t tex
;
185 drm_radeon_tex_image_t tmp
;
186 const int level
= hwlevel
+ t
->base
.firstLevel
;
188 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
189 fprintf( stderr
, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
190 __FUNCTION__
, (void *)t
, (void *)t
->base
.tObj
, level
, width
, height
, face
);
195 /* Ensure we have a valid texture to upload */
196 if ( ( hwlevel
< 0 ) || ( hwlevel
>= RADEON_MAX_TEXTURE_LEVELS
) ) {
197 _mesa_problem(NULL
, "bad texture level in %s", __FUNCTION__
);
201 texImage
= t
->base
.tObj
->Image
[face
][level
];
204 if ( RADEON_DEBUG
& DEBUG_TEXTURE
)
205 fprintf( stderr
, "%s: texImage %d is NULL!\n", __FUNCTION__
, level
);
208 if ( !texImage
->Data
) {
209 if ( RADEON_DEBUG
& DEBUG_TEXTURE
)
210 fprintf( stderr
, "%s: image data is NULL!\n", __FUNCTION__
);
215 if (t
->base
.tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
217 assert(hwlevel
== 0);
218 if ( RADEON_DEBUG
& DEBUG_TEXTURE
)
219 fprintf( stderr
, "%s: image data is rectangular\n", __FUNCTION__
);
220 radeonUploadRectSubImage( rmesa
, t
, texImage
, x
, y
, width
, height
);
224 imageWidth
= texImage
->Width
;
225 imageHeight
= texImage
->Height
;
227 offset
= t
->bufAddr
+ t
->base
.totalSize
* face
/ 6;
229 if ( RADEON_DEBUG
& (DEBUG_TEXTURE
|DEBUG_IOCTL
) ) {
232 GLint blitX
= t
->image
[face
][hwlevel
].x
;
233 GLint blitY
= t
->image
[face
][hwlevel
].y
;
234 GLint blitWidth
= t
->image
[face
][hwlevel
].width
;
235 GLint blitHeight
= t
->image
[face
][hwlevel
].height
;
236 fprintf( stderr
, " upload image: %d,%d at %d,%d\n",
237 imageWidth
, imageHeight
, imageX
, imageY
);
238 fprintf( stderr
, " upload blit: %d,%d at %d,%d\n",
239 blitWidth
, blitHeight
, blitX
, blitY
);
240 fprintf( stderr
, " blit ofs: 0x%07x level: %d/%d\n",
241 (GLuint
)offset
, hwlevel
, level
);
244 t
->image
[face
][hwlevel
].data
= texImage
->Data
;
246 /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
247 * NOTE: we're always use a 1KB-wide blit and I8 texture format.
248 * We used to use 1, 2 and 4-byte texels and used to use the texture
249 * width to dictate the blit width - but that won't work for compressed
251 * NOTE: can't do that with texture tiling. (sroland)
255 /* copy (x,y,width,height,data) */
256 memcpy( &tmp
, &t
->image
[face
][hwlevel
], sizeof(drm_radeon_tex_image_t
) );
258 if (texImage
->TexFormat
->TexelBytes
) {
259 /* use multi-byte upload scheme */
260 tex
.height
= imageHeight
;
261 tex
.width
= imageWidth
;
262 tex
.format
= t
->pp_txformat
& RADEON_TXFORMAT_FORMAT_MASK
;
263 tex
.pitch
= MAX2((texImage
->Width
* texImage
->TexFormat
->TexelBytes
) / 64, 1);
264 tex
.offset
+= tmp
.x
& ~1023;
265 tmp
.x
= tmp
.x
% 1024;
266 if (t
->tile_bits
& RADEON_TXO_MICRO_TILE_X2
) {
267 /* need something like "tiled coordinates" ? */
268 tmp
.y
= tmp
.x
/ (tex
.pitch
* 128) * 2;
269 tmp
.x
= tmp
.x
% (tex
.pitch
* 128) / 2 / texImage
->TexFormat
->TexelBytes
;
270 tex
.pitch
|= RADEON_DST_TILE_MICRO
>> 22;
273 tmp
.x
= tmp
.x
>> (texImage
->TexFormat
->TexelBytes
>> 1);
275 if ((t
->tile_bits
& RADEON_TXO_MACRO_TILE
) &&
276 (texImage
->Width
* texImage
->TexFormat
->TexelBytes
>= 256)) {
277 /* radeon switches off macro tiling for small textures/mipmaps it seems */
278 tex
.pitch
|= RADEON_DST_TILE_MACRO
>> 22;
282 /* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is
283 needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */
284 /* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed
285 so the kernel module reads the right amount of data. */
286 tex
.format
= RADEON_TXFORMAT_I8
; /* any 1-byte texel format */
287 tex
.pitch
= (BLIT_WIDTH_BYTES
/ 64);
288 tex
.height
= (imageHeight
+ 3) / 4;
289 tex
.width
= (imageWidth
+ 3) / 4;
290 switch (t
->pp_txformat
& RADEON_TXFORMAT_FORMAT_MASK
) {
291 case RADEON_TXFORMAT_DXT1
:
294 case RADEON_TXFORMAT_DXT23
:
295 case RADEON_TXFORMAT_DXT45
:
301 LOCK_HARDWARE( rmesa
);
303 ret
= drmCommandWriteRead( rmesa
->dri
.fd
, DRM_RADEON_TEXTURE
,
304 &tex
, sizeof(drm_radeon_texture_t
) );
305 } while ( ret
== -EAGAIN
);
307 UNLOCK_HARDWARE( rmesa
);
310 fprintf( stderr
, "DRM_RADEON_TEXTURE: return = %d\n", ret
);
311 fprintf( stderr
, " offset=0x%08x\n",
313 fprintf( stderr
, " image width=%d height=%d\n",
314 imageWidth
, imageHeight
);
315 fprintf( stderr
, " blit width=%d height=%d data=%p\n",
316 t
->image
[face
][hwlevel
].width
, t
->image
[face
][hwlevel
].height
,
317 t
->image
[face
][hwlevel
].data
);
324 * Upload the texture images associated with texture \a t. This might
325 * require the allocation of texture memory.
327 * \param rmesa Context pointer
328 * \param t Texture to be uploaded
329 * \param face Cube map face to be uploaded. Zero for non-cube maps.
332 int radeonUploadTexImages( radeonContextPtr rmesa
, radeonTexObjPtr t
, GLuint face
)
336 if ( !t
|| t
->base
.totalSize
== 0 || t
->image_override
)
339 if ( RADEON_DEBUG
& (DEBUG_TEXTURE
|DEBUG_IOCTL
) ) {
340 fprintf( stderr
, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__
,
341 (void *)rmesa
->glCtx
, (void *)t
->base
.tObj
, t
->base
.totalSize
,
342 t
->base
.firstLevel
, t
->base
.lastLevel
);
345 numLevels
= t
->base
.lastLevel
- t
->base
.firstLevel
+ 1;
347 if (RADEON_DEBUG
& DEBUG_SYNC
) {
348 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
349 radeonFinish( rmesa
->glCtx
);
352 LOCK_HARDWARE( rmesa
);
354 if ( t
->base
.memBlock
== NULL
) {
357 heap
= driAllocateTexture( rmesa
->texture_heaps
, rmesa
->nr_heaps
,
358 (driTextureObject
*) t
);
360 UNLOCK_HARDWARE( rmesa
);
364 /* Set the base offset of the texture image */
365 t
->bufAddr
= rmesa
->radeonScreen
->texOffset
[heap
]
366 + t
->base
.memBlock
->ofs
;
367 t
->pp_txoffset
= t
->bufAddr
;
369 if (!(t
->base
.tObj
->Image
[0][0]->IsClientData
)) {
370 /* hope it's safe to add that here... */
371 t
->pp_txoffset
|= t
->tile_bits
;
374 /* Mark this texobj as dirty on all units:
376 t
->dirty_state
= TEX_ALL
;
380 /* Let the world know we've used this memory recently.
382 driUpdateTextureLRU( (driTextureObject
*) t
);
383 UNLOCK_HARDWARE( rmesa
);
386 /* Upload any images that are new */
387 if (t
->base
.dirty_images
[face
]) {
389 for ( i
= 0 ; i
< numLevels
; i
++ ) {
390 if ( (t
->base
.dirty_images
[face
] & (1 << (i
+t
->base
.firstLevel
))) != 0 ) {
391 uploadSubImage( rmesa
, t
, i
, 0, 0, t
->image
[face
][i
].width
,
392 t
->image
[face
][i
].height
, face
);
395 t
->base
.dirty_images
[face
] = 0;
398 if (RADEON_DEBUG
& DEBUG_SYNC
) {
399 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
400 radeonFinish( rmesa
->glCtx
);