1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_texmem.c,v 1.7 2002/12/16 16:18:59 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation on the rights to use, copy, modify, merge, publish,
13 distribute, sub license, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
24 NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR THEIR
25 SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
26 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR
27 IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 **************************************************************************/
34 * Kevin E. Martin <martin@valinux.com>
35 * Gareth Hughes <gareth@valinux.com>
45 #include "radeon_context.h"
46 #include "radeon_ioctl.h"
47 #include "radeon_tex.h"
49 #include <unistd.h> /* for usleep() */
53 * Destroy any device-dependent state associated with the texture. This may
54 * include NULLing out hardware state that points to the texture.
57 radeonDestroyTexObj( radeonContextPtr rmesa
, radeonTexObjPtr t
)
59 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
60 fprintf( stderr
, "%s( %p, %p )\n", __FUNCTION__
, (void *)t
, (void *)t
->base
.tObj
);
63 if ( rmesa
!= NULL
) {
67 for ( i
= 0 ; i
< rmesa
->glCtx
->Const
.MaxTextureUnits
; i
++ ) {
68 if ( t
== rmesa
->state
.texture
.unit
[i
].texobj
) {
69 rmesa
->state
.texture
.unit
[i
].texobj
= NULL
;
70 rmesa
->hw
.tex
[i
].dirty
= GL_FALSE
;
77 /* ------------------------------------------------------------
78 * Texture image conversions
82 static void radeonUploadRectSubImage( radeonContextPtr rmesa
,
84 struct gl_texture_image
*texImage
,
86 GLint width
, GLint height
)
88 const struct gl_texture_format
*texFormat
= texImage
->TexFormat
;
89 int blit_format
, dstPitch
, done
;
91 switch ( texFormat
->TexelBytes
) {
93 blit_format
= RADEON_GMC_DST_8BPP_CI
;
96 blit_format
= RADEON_GMC_DST_16BPP
;
99 blit_format
= RADEON_GMC_DST_32BPP
;
102 fprintf( stderr
, "radeonUploadRectSubImage: unknown blit_format (texelbytes=%d)\n",
103 texFormat
->TexelBytes
);
107 t
->image
[0][0].data
= texImage
->Data
;
109 /* Currently don't need to cope with small pitches.
111 width
= texImage
->Width
;
112 height
= texImage
->Height
;
113 dstPitch
= t
->pp_txpitch
+ 32;
115 { /* FIXME: prefer GART-texturing if possible */
116 /* Data not in GART memory, or bad pitch.
118 for (done
= 0; done
< height
; ) {
119 struct radeon_dma_region region
;
120 int lines
= MIN2( height
- done
, RADEON_BUFFER_SIZE
/ dstPitch
);
124 src_pitch
= texImage
->RowStride
* texFormat
->TexelBytes
;
126 tex
= (char *)texImage
->Data
+ done
* src_pitch
;
128 memset(®ion
, 0, sizeof(region
));
129 radeonAllocDmaRegion( rmesa
, ®ion
, lines
* dstPitch
, 1024 );
131 /* Copy texdata to dma:
134 fprintf(stderr
, "%s: src_pitch %d dst_pitch %d\n",
135 __FUNCTION__
, src_pitch
, dstPitch
);
137 if (src_pitch
== dstPitch
) {
138 memcpy( region
.address
+ region
.start
, tex
, lines
* src_pitch
);
141 char *buf
= region
.address
+ region
.start
;
143 for (i
= 0 ; i
< lines
; i
++) {
144 memcpy( buf
, tex
, src_pitch
);
150 radeonEmitWait( rmesa
, RADEON_WAIT_3D
);
154 /* Blit to framebuffer
156 radeonEmitBlit( rmesa
,
158 dstPitch
, GET_START( ®ion
),
159 dstPitch
, t
->bufAddr
,
164 radeonEmitWait( rmesa
, RADEON_WAIT_2D
);
166 radeonReleaseDmaRegion( rmesa
, ®ion
, __FUNCTION__
);
174 * Upload the texture image associated with texture \a t at the specified
175 * level at the address relative to \a start.
177 static void uploadSubImage( radeonContextPtr rmesa
, radeonTexObjPtr t
,
179 GLint x
, GLint y
, GLint width
, GLint height
,
182 struct gl_texture_image
*texImage
= NULL
;
184 GLint imageWidth
, imageHeight
;
186 drm_radeon_texture_t tex
;
187 drm_radeon_tex_image_t tmp
;
188 const int level
= hwlevel
+ t
->base
.firstLevel
;
190 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
191 fprintf( stderr
, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
192 __FUNCTION__
, (void *)t
, (void *)t
->base
.tObj
, level
, width
, height
, face
);
197 /* Ensure we have a valid texture to upload */
198 if ( ( hwlevel
< 0 ) || ( hwlevel
>= RADEON_MAX_TEXTURE_LEVELS
) ) {
199 _mesa_problem(NULL
, "bad texture level in %s", __FUNCTION__
);
203 texImage
= t
->base
.tObj
->Image
[face
][level
];
206 if ( RADEON_DEBUG
& DEBUG_TEXTURE
)
207 fprintf( stderr
, "%s: texImage %d is NULL!\n", __FUNCTION__
, level
);
210 if ( !texImage
->Data
) {
211 if ( RADEON_DEBUG
& DEBUG_TEXTURE
)
212 fprintf( stderr
, "%s: image data is NULL!\n", __FUNCTION__
);
217 if (t
->base
.tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
219 assert(hwlevel
== 0);
220 if ( RADEON_DEBUG
& DEBUG_TEXTURE
)
221 fprintf( stderr
, "%s: image data is rectangular\n", __FUNCTION__
);
222 radeonUploadRectSubImage( rmesa
, t
, texImage
, x
, y
, width
, height
);
226 imageWidth
= texImage
->Width
;
227 imageHeight
= texImage
->Height
;
231 if ( RADEON_DEBUG
& (DEBUG_TEXTURE
|DEBUG_IOCTL
) ) {
234 GLint blitX
= t
->image
[face
][hwlevel
].x
;
235 GLint blitY
= t
->image
[face
][hwlevel
].y
;
236 GLint blitWidth
= t
->image
[face
][hwlevel
].width
;
237 GLint blitHeight
= t
->image
[face
][hwlevel
].height
;
238 fprintf( stderr
, " upload image: %d,%d at %d,%d\n",
239 imageWidth
, imageHeight
, imageX
, imageY
);
240 fprintf( stderr
, " upload blit: %d,%d at %d,%d\n",
241 blitWidth
, blitHeight
, blitX
, blitY
);
242 fprintf( stderr
, " blit ofs: 0x%07x level: %d/%d\n",
243 (GLuint
)offset
, hwlevel
, level
);
246 t
->image
[face
][hwlevel
].data
= texImage
->Data
;
248 /* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
249 * NOTE: we're always use a 1KB-wide blit and I8 texture format.
250 * We used to use 1, 2 and 4-byte texels and used to use the texture
251 * width to dictate the blit width - but that won't work for compressed
253 * NOTE: can't do that with texture tiling. (sroland)
257 /* copy (x,y,width,height,data) */
258 memcpy( &tmp
, &t
->image
[face
][hwlevel
], sizeof(drm_radeon_tex_image_t
) );
260 if (texImage
->TexFormat
->TexelBytes
) {
261 /* use multi-byte upload scheme */
262 tex
.height
= imageHeight
;
263 tex
.width
= imageWidth
;
264 tex
.format
= t
->pp_txformat
& RADEON_TXFORMAT_FORMAT_MASK
;
265 tex
.pitch
= MAX2((texImage
->Width
* texImage
->TexFormat
->TexelBytes
) / 64, 1);
266 tex
.offset
+= tmp
.x
& ~1023;
267 tmp
.x
= tmp
.x
% 1024;
268 if (t
->tile_bits
& RADEON_TXO_MICRO_TILE_X2
) {
269 /* need something like "tiled coordinates" ? */
270 tmp
.y
= tmp
.x
/ (tex
.pitch
* 128) * 2;
271 tmp
.x
= tmp
.x
% (tex
.pitch
* 128) / 2 / texImage
->TexFormat
->TexelBytes
;
272 tex
.pitch
|= RADEON_DST_TILE_MICRO
>> 22;
275 tmp
.x
= tmp
.x
>> (texImage
->TexFormat
->TexelBytes
>> 1);
277 if ((t
->tile_bits
& RADEON_TXO_MACRO_TILE
) &&
278 (texImage
->Width
* texImage
->TexFormat
->TexelBytes
>= 256)) {
279 /* radeon switches off macro tiling for small textures/mipmaps it seems */
280 tex
.pitch
|= RADEON_DST_TILE_MACRO
>> 22;
284 /* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is
285 needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */
286 /* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed
287 so the kernel module reads the right amount of data. */
288 tex
.format
= RADEON_TXFORMAT_I8
; /* any 1-byte texel format */
289 tex
.pitch
= (BLIT_WIDTH_BYTES
/ 64);
290 tex
.height
= (imageHeight
+ 3) / 4;
291 tex
.width
= (imageWidth
+ 3) / 4;
292 switch (t
->pp_txformat
& RADEON_TXFORMAT_FORMAT_MASK
) {
293 case RADEON_TXFORMAT_DXT1
:
296 case RADEON_TXFORMAT_DXT23
:
297 case RADEON_TXFORMAT_DXT45
:
303 LOCK_HARDWARE( rmesa
);
305 ret
= drmCommandWriteRead( rmesa
->dri
.fd
, DRM_RADEON_TEXTURE
,
306 &tex
, sizeof(drm_radeon_texture_t
) );
307 } while ( ret
&& errno
== EAGAIN
);
309 UNLOCK_HARDWARE( rmesa
);
312 fprintf( stderr
, "DRM_RADEON_TEXTURE: return = %d\n", ret
);
313 fprintf( stderr
, " offset=0x%08x\n",
315 fprintf( stderr
, " image width=%d height=%d\n",
316 imageWidth
, imageHeight
);
317 fprintf( stderr
, " blit width=%d height=%d data=%p\n",
318 t
->image
[face
][hwlevel
].width
, t
->image
[face
][hwlevel
].height
,
319 t
->image
[face
][hwlevel
].data
);
326 * Upload the texture images associated with texture \a t. This might
327 * require the allocation of texture memory.
329 * \param rmesa Context pointer
330 * \param t Texture to be uploaded
331 * \param face Cube map face to be uploaded. Zero for non-cube maps.
334 int radeonUploadTexImages( radeonContextPtr rmesa
, radeonTexObjPtr t
, GLuint face
)
336 const int numLevels
= t
->base
.lastLevel
- t
->base
.firstLevel
+ 1;
338 if ( RADEON_DEBUG
& (DEBUG_TEXTURE
|DEBUG_IOCTL
) ) {
339 fprintf( stderr
, "%s( %p, %p ) sz=%d lvls=%d-%d\n", __FUNCTION__
,
340 (void *)rmesa
->glCtx
, (void *)t
->base
.tObj
, t
->base
.totalSize
,
341 t
->base
.firstLevel
, t
->base
.lastLevel
);
344 if ( !t
|| t
->base
.totalSize
== 0 )
347 if (RADEON_DEBUG
& DEBUG_SYNC
) {
348 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
349 radeonFinish( rmesa
->glCtx
);
352 LOCK_HARDWARE( rmesa
);
354 if ( t
->base
.memBlock
== NULL
) {
357 heap
= driAllocateTexture( rmesa
->texture_heaps
, rmesa
->nr_heaps
,
358 (driTextureObject
*) t
);
360 UNLOCK_HARDWARE( rmesa
);
364 /* Set the base offset of the texture image */
365 t
->bufAddr
= rmesa
->radeonScreen
->texOffset
[heap
]
366 + t
->base
.memBlock
->ofs
;
367 t
->pp_txoffset
= t
->bufAddr
;
369 if (!(t
->base
.tObj
->Image
[0][0]->IsClientData
)) {
370 /* hope it's safe to add that here... */
371 t
->pp_txoffset
|= t
->tile_bits
;
374 /* Mark this texobj as dirty on all units:
376 t
->dirty_state
= TEX_ALL
;
380 /* Let the world know we've used this memory recently.
382 driUpdateTextureLRU( (driTextureObject
*) t
);
383 UNLOCK_HARDWARE( rmesa
);
386 /* Upload any images that are new */
387 if (t
->base
.dirty_images
[face
]) {
389 for ( i
= 0 ; i
< numLevels
; i
++ ) {
390 if ( (t
->base
.dirty_images
[face
] & (1 << (i
+t
->base
.firstLevel
))) != 0 ) {
391 uploadSubImage( rmesa
, t
, i
, 0, 0, t
->image
[face
][i
].width
,
392 t
->image
[face
][i
].height
, face
);
395 t
->base
.dirty_images
[face
] = 0;
398 if (RADEON_DEBUG
& DEBUG_SYNC
) {
399 fprintf(stderr
, "%s: Syncing\n", __FUNCTION__
);
400 radeonFinish( rmesa
->glCtx
);