1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c,v 1.6 2002/12/16 16:18:59 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
42 #include "texformat.h"
45 #include "radeon_context.h"
46 #include "radeon_state.h"
47 #include "radeon_ioctl.h"
48 #include "radeon_swtcl.h"
49 #include "radeon_tex.h"
50 #include "radeon_tcl.h"
53 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
54 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
55 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
56 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
57 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
58 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
59 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
60 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
61 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
64 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
65 #define _COLOR_REV(f) \
66 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
68 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
69 #define _ALPHA_REV(f) \
70 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
72 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
74 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
75 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
76 && (tx_table[f].format != 0xffffffff) )
79 GLuint format
, filter
;
115 * This function computes the number of bytes of storage needed for
116 * the given texture object (all mipmap levels, all cube faces).
117 * The \c image[face][level].x/y/width/height parameters for upload/blitting
118 * are computed here. \c pp_txfilter, \c pp_txformat, etc. will be set here
121 * \param rmesa Context pointer
122 * \param tObj GL texture object whose images are to be posted to
125 static void radeonSetTexImages( radeonContextPtr rmesa
,
126 struct gl_texture_object
*tObj
)
128 radeonTexObjPtr t
= (radeonTexObjPtr
)tObj
->DriverData
;
129 const struct gl_texture_image
*baseImage
= tObj
->Image
[0][tObj
->BaseLevel
];
130 GLint curOffset
, blitWidth
;
133 GLint log2Width
, log2Height
, log2Depth
;
135 /* Set the hardware texture format
138 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
139 RADEON_TXFORMAT_ALPHA_IN_MAP
);
140 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
142 if ( VALID_FORMAT( baseImage
->TexFormat
->MesaFormat
) ) {
143 t
->pp_txformat
|= tx_table
[ baseImage
->TexFormat
->MesaFormat
].format
;
144 t
->pp_txfilter
|= tx_table
[ baseImage
->TexFormat
->MesaFormat
].filter
;
147 _mesa_problem(NULL
, "unexpected texture format in %s", __FUNCTION__
);
151 texelBytes
= baseImage
->TexFormat
->TexelBytes
;
153 /* Compute which mipmap levels we really want to send to the hardware.
156 if (tObj
->Target
!= GL_TEXTURE_CUBE_MAP
)
157 driCalculateTextureFirstLastLevel( (driTextureObject
*) t
);
159 /* r100 can't handle mipmaps for cube/3d textures, so don't waste
161 t
->base
.firstLevel
= t
->base
.lastLevel
= tObj
->BaseLevel
;
163 log2Width
= tObj
->Image
[0][t
->base
.firstLevel
]->WidthLog2
;
164 log2Height
= tObj
->Image
[0][t
->base
.firstLevel
]->HeightLog2
;
165 log2Depth
= tObj
->Image
[0][t
->base
.firstLevel
]->DepthLog2
;
167 numLevels
= t
->base
.lastLevel
- t
->base
.firstLevel
+ 1;
169 assert(numLevels
<= RADEON_MAX_TEXTURE_LEVELS
);
171 /* Calculate mipmap offsets and dimensions for blitting (uploading)
172 * The idea is that we lay out the mipmap levels within a block of
173 * memory organized as a rectangle of width BLIT_WIDTH_BYTES.
176 blitWidth
= BLIT_WIDTH_BYTES
;
179 /* figure out if this texture is suitable for tiling. */
180 if (texelBytes
&& (tObj
->Target
!= GL_TEXTURE_RECTANGLE_NV
)) {
181 if (rmesa
->texmicrotile
&& (baseImage
->Height
> 1)) {
182 /* allow 32 (bytes) x 1 mip (which will use two times the space
183 the non-tiled version would use) max if base texture is large enough */
184 if ((numLevels
== 1) ||
185 (((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 32) &&
186 (baseImage
->Width
* texelBytes
> 64)) ||
187 ((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 16)) {
188 /* R100 has two microtile bits (only the txoffset reg, not the blitter)
189 weird: X2 + OPT: 32bit correct, 16bit completely hosed
190 X2: 32bit correct, 16bit correct
191 OPT: 32bit large mips correct, small mips hosed, 16bit completely hosed */
192 t
->tile_bits
|= RADEON_TXO_MICRO_TILE_X2
/*| RADEON_TXO_MICRO_TILE_OPT*/;
195 if ((baseImage
->Width
* texelBytes
>= 256) && (baseImage
->Height
>= 16)) {
196 /* R100 disables macro tiling only if mip width is smaller than 256 bytes, and not
197 in the case if height is smaller than 16 (not 100% sure), as does the r200,
198 so need to disable macro tiling in that case */
199 if ((numLevels
== 1) || ((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 4)) {
200 t
->tile_bits
|= RADEON_TXO_MACRO_TILE
;
205 for (i
= 0; i
< numLevels
; i
++) {
206 const struct gl_texture_image
*texImage
;
209 texImage
= tObj
->Image
[0][i
+ t
->base
.firstLevel
];
213 /* find image size in bytes */
214 if (texImage
->IsCompressed
) {
215 /* need to calculate the size AFTER padding even though the texture is
216 submitted without padding.
217 Only handle pot textures currently - don't know if npot is even possible,
218 size calculation would certainly need (trivial) adjustments.
219 Align (and later pad) to 32byte, not sure what that 64byte blit width is
221 if ((t
->pp_txformat
& RADEON_TXFORMAT_FORMAT_MASK
) == RADEON_TXFORMAT_DXT1
) {
222 /* RGB_DXT1/RGBA_DXT1, 8 bytes per block */
223 if ((texImage
->Width
+ 3) < 8) /* width one block */
224 size
= texImage
->CompressedSize
* 4;
225 else if ((texImage
->Width
+ 3) < 16)
226 size
= texImage
->CompressedSize
* 2;
227 else size
= texImage
->CompressedSize
;
229 else /* DXT3/5, 16 bytes per block */
230 if ((texImage
->Width
+ 3) < 8)
231 size
= texImage
->CompressedSize
* 2;
232 else size
= texImage
->CompressedSize
;
234 else if (tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
235 size
= ((texImage
->Width
* texelBytes
+ 63) & ~63) * texImage
->Height
;
237 else if (t
->tile_bits
& RADEON_TXO_MICRO_TILE_X2
) {
238 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
239 though the actual offset may be different (if texture is less than
240 32 bytes width) to the untiled case */
241 int w
= (texImage
->Width
* texelBytes
* 2 + 31) & ~31;
242 size
= (w
* ((texImage
->Height
+ 1) / 2)) * texImage
->Depth
;
243 blitWidth
= MAX2(texImage
->Width
, 64 / texelBytes
);
246 int w
= (texImage
->Width
* texelBytes
+ 31) & ~31;
247 size
= w
* texImage
->Height
* texImage
->Depth
;
248 blitWidth
= MAX2(texImage
->Width
, 64 / texelBytes
);
252 /* Align to 32-byte offset. It is faster to do this unconditionally
253 * (no branch penalty).
256 curOffset
= (curOffset
+ 0x1f) & ~0x1f;
259 t
->image
[0][i
].x
= curOffset
; /* fix x and y coords up later together with offset */
260 t
->image
[0][i
].y
= 0;
261 t
->image
[0][i
].width
= MIN2(size
/ texelBytes
, blitWidth
);
262 t
->image
[0][i
].height
= (size
/ texelBytes
) / t
->image
[0][i
].width
;
265 t
->image
[0][i
].x
= curOffset
% BLIT_WIDTH_BYTES
;
266 t
->image
[0][i
].y
= curOffset
/ BLIT_WIDTH_BYTES
;
267 t
->image
[0][i
].width
= MIN2(size
, BLIT_WIDTH_BYTES
);
268 t
->image
[0][i
].height
= size
/ t
->image
[0][i
].width
;
272 /* for debugging only and only applicable to non-rectangle targets */
273 assert(size
% t
->image
[0][i
].width
== 0);
274 assert(t
->image
[0][i
].x
== 0
275 || (size
< BLIT_WIDTH_BYTES
&& t
->image
[0][i
].height
== 1));
280 "level %d: %dx%d x=%d y=%d w=%d h=%d size=%d at %d\n",
281 i
, texImage
->Width
, texImage
->Height
,
282 t
->image
[0][i
].x
, t
->image
[0][i
].y
,
283 t
->image
[0][i
].width
, t
->image
[0][i
].height
, size
, curOffset
);
289 /* Align the total size of texture memory block.
291 t
->base
.totalSize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
293 /* Setup remaining cube face blits, if needed */
294 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
295 const GLuint faceSize
= t
->base
.totalSize
;
297 /* reuse face 0 x/y/width/height - just update the offset when uploading */
298 for (face
= 1; face
< 6; face
++) {
299 for (i
= 0; i
< numLevels
; i
++) {
300 t
->image
[face
][i
].x
= t
->image
[0][i
].x
;
301 t
->image
[face
][i
].y
= t
->image
[0][i
].y
;
302 t
->image
[face
][i
].width
= t
->image
[0][i
].width
;
303 t
->image
[face
][i
].height
= t
->image
[0][i
].height
;
306 t
->base
.totalSize
= 6 * faceSize
; /* total texmem needed */
311 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
312 t
->pp_txfilter
|= (numLevels
- 1) << RADEON_MAX_MIP_LEVEL_SHIFT
;
314 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
315 RADEON_TXFORMAT_HEIGHT_MASK
|
316 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
317 RADEON_TXFORMAT_F5_WIDTH_MASK
|
318 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
319 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
320 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
322 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
323 assert(log2Width
== log2Height
);
324 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_F5_WIDTH_SHIFT
) |
325 (log2Height
<< RADEON_TXFORMAT_F5_HEIGHT_SHIFT
) |
326 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE
));
327 t
->pp_cubic_faces
= ((log2Width
<< RADEON_FACE_WIDTH_1_SHIFT
) |
328 (log2Height
<< RADEON_FACE_HEIGHT_1_SHIFT
) |
329 (log2Width
<< RADEON_FACE_WIDTH_2_SHIFT
) |
330 (log2Height
<< RADEON_FACE_HEIGHT_2_SHIFT
) |
331 (log2Width
<< RADEON_FACE_WIDTH_3_SHIFT
) |
332 (log2Height
<< RADEON_FACE_HEIGHT_3_SHIFT
) |
333 (log2Width
<< RADEON_FACE_WIDTH_4_SHIFT
) |
334 (log2Height
<< RADEON_FACE_HEIGHT_4_SHIFT
));
337 t
->pp_txsize
= (((tObj
->Image
[0][t
->base
.firstLevel
]->Width
- 1) << 0) |
338 ((tObj
->Image
[0][t
->base
.firstLevel
]->Height
- 1) << 16));
340 /* Only need to round to nearest 32 for textures, but the blitter
341 * requires 64-byte aligned pitches, and we may/may not need the
342 * blitter. NPOT only!
344 if (baseImage
->IsCompressed
)
345 t
->pp_txpitch
= (tObj
->Image
[0][t
->base
.firstLevel
]->Width
+ 63) & ~(63);
347 t
->pp_txpitch
= ((tObj
->Image
[0][t
->base
.firstLevel
]->Width
* texelBytes
) + 63) & ~(63);
350 t
->dirty_state
= TEX_ALL
;
352 /* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */
357 /* ================================================================
358 * Texture combine functions
361 /* GL_ARB_texture_env_combine support
364 /* The color tables have combine functions for GL_SRC_COLOR,
365 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
367 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
370 RADEON_COLOR_ARG_A_T0_COLOR
,
371 RADEON_COLOR_ARG_A_T1_COLOR
,
372 RADEON_COLOR_ARG_A_T2_COLOR
375 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
376 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
377 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
380 RADEON_COLOR_ARG_A_T0_ALPHA
,
381 RADEON_COLOR_ARG_A_T1_ALPHA
,
382 RADEON_COLOR_ARG_A_T2_ALPHA
385 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
386 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
387 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
391 static GLuint radeon_tfactor_color
[] =
393 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
394 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
395 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
396 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
399 static GLuint radeon_primary_color
[] =
401 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
402 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
403 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
404 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
407 static GLuint radeon_previous_color
[] =
409 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
410 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
411 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
412 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
415 /* GL_ZERO table - indices 0-3
416 * GL_ONE table - indices 1-4
418 static GLuint radeon_zero_color
[] =
420 RADEON_COLOR_ARG_A_ZERO
,
421 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
422 RADEON_COLOR_ARG_A_ZERO
,
423 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
424 RADEON_COLOR_ARG_A_ZERO
428 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
430 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
433 RADEON_ALPHA_ARG_A_T0_ALPHA
,
434 RADEON_ALPHA_ARG_A_T1_ALPHA
,
435 RADEON_ALPHA_ARG_A_T2_ALPHA
438 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
439 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
440 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
444 static GLuint radeon_tfactor_alpha
[] =
446 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
447 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
450 static GLuint radeon_primary_alpha
[] =
452 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
453 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
456 static GLuint radeon_previous_alpha
[] =
458 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
459 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
462 /* GL_ZERO table - indices 0-1
463 * GL_ONE table - indices 1-2
465 static GLuint radeon_zero_alpha
[] =
467 RADEON_ALPHA_ARG_A_ZERO
,
468 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
469 RADEON_ALPHA_ARG_A_ZERO
473 /* Extract the arg from slot A, shift it into the correct argument slot
474 * and set the corresponding complement bit.
476 #define RADEON_COLOR_ARG( n, arg ) \
479 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
480 << RADEON_COLOR_ARG_##arg##_SHIFT); \
482 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
483 << RADEON_COMP_ARG_##arg##_SHIFT); \
486 #define RADEON_ALPHA_ARG( n, arg ) \
489 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
490 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
492 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
493 << RADEON_COMP_ARG_##arg##_SHIFT); \
497 /* ================================================================
498 * Texture unit state management
501 static GLboolean
radeonUpdateTextureEnv( GLcontext
*ctx
, int unit
)
503 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
504 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
505 GLuint color_combine
, alpha_combine
;
506 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
507 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
508 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
509 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
510 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
511 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
514 /* texUnit->_Current can be NULL if and only if the texture unit is
515 * not actually enabled.
517 assert( (texUnit
->_ReallyEnabled
== 0)
518 || (texUnit
->_Current
!= NULL
) );
520 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
521 fprintf( stderr
, "%s( %p, %d )\n", __FUNCTION__
, (void *)ctx
, unit
);
524 /* Set the texture environment state. Isn't this nice and clean?
525 * The chip will automagically set the texture alpha to 0xff when
526 * the texture format does not include an alpha component. This
527 * reduces the amount of special-casing we have to do, alpha-only
528 * textures being a notable exception.
530 /* Don't cache these results.
532 rmesa
->state
.texture
.unit
[unit
].format
= 0;
533 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
535 if ( !texUnit
->_ReallyEnabled
) {
536 color_combine
= color_combine0
;
537 alpha_combine
= alpha_combine0
;
540 GLuint color_arg
[3], alpha_arg
[3];
542 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
543 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
544 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
545 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
549 * Extract the color and alpha combine function arguments.
551 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
552 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
553 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
558 color_arg
[i
] = radeon_texture_color
[op
][unit
];
561 color_arg
[i
] = radeon_tfactor_color
[op
];
563 case GL_PRIMARY_COLOR
:
564 color_arg
[i
] = radeon_primary_color
[op
];
567 color_arg
[i
] = radeon_previous_color
[op
];
570 color_arg
[i
] = radeon_zero_color
[op
];
573 color_arg
[i
] = radeon_zero_color
[op
+1];
578 /* implement ogl 1.4/1.5 core spec here, not specification of
579 * GL_ARB_texture_env_crossbar (which would require disabling blending
580 * instead of undefined results when referencing not enabled texunit) */
581 color_arg
[i
] = radeon_texture_color
[op
][srcRGBi
- GL_TEXTURE0
];
588 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
589 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
590 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
595 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
598 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
600 case GL_PRIMARY_COLOR
:
601 alpha_arg
[i
] = radeon_primary_alpha
[op
];
604 alpha_arg
[i
] = radeon_previous_alpha
[op
];
607 alpha_arg
[i
] = radeon_zero_alpha
[op
];
610 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
615 alpha_arg
[i
] = radeon_texture_alpha
[op
][srcAi
- GL_TEXTURE0
];
623 * Build up the color and alpha combine functions.
625 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
627 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
628 RADEON_COLOR_ARG_B_ZERO
|
629 RADEON_BLEND_CTL_ADD
|
631 RADEON_COLOR_ARG( 0, C
);
634 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
635 RADEON_BLEND_CTL_ADD
|
637 RADEON_COLOR_ARG( 0, A
);
638 RADEON_COLOR_ARG( 1, B
);
641 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
643 RADEON_BLEND_CTL_ADD
|
645 RADEON_COLOR_ARG( 0, A
);
646 RADEON_COLOR_ARG( 1, C
);
649 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
651 RADEON_BLEND_CTL_ADDSIGNED
|
653 RADEON_COLOR_ARG( 0, A
);
654 RADEON_COLOR_ARG( 1, C
);
657 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
659 RADEON_BLEND_CTL_SUBTRACT
|
661 RADEON_COLOR_ARG( 0, A
);
662 RADEON_COLOR_ARG( 1, C
);
665 color_combine
= (RADEON_BLEND_CTL_BLEND
|
667 RADEON_COLOR_ARG( 0, B
);
668 RADEON_COLOR_ARG( 1, A
);
669 RADEON_COLOR_ARG( 2, C
);
672 case GL_DOT3_RGB_EXT
:
673 case GL_DOT3_RGBA_EXT
:
674 /* The EXT version of the DOT3 extension does not support the
675 * scale factor, but the ARB version (and the version in OpenGL
683 /* The R100 / RV200 only support a 1X multiplier in hardware
686 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
691 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
692 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
693 /* is it necessary to set this or will it be ignored anyway? */
697 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
698 RADEON_BLEND_CTL_DOT3
|
700 RADEON_COLOR_ARG( 0, A
);
701 RADEON_COLOR_ARG( 1, B
);
704 case GL_MODULATE_ADD_ATI
:
705 color_combine
= (RADEON_BLEND_CTL_ADD
|
707 RADEON_COLOR_ARG( 0, A
);
708 RADEON_COLOR_ARG( 1, C
);
709 RADEON_COLOR_ARG( 2, B
);
711 case GL_MODULATE_SIGNED_ADD_ATI
:
712 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
714 RADEON_COLOR_ARG( 0, A
);
715 RADEON_COLOR_ARG( 1, C
);
716 RADEON_COLOR_ARG( 2, B
);
718 case GL_MODULATE_SUBTRACT_ATI
:
719 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
721 RADEON_COLOR_ARG( 0, A
);
722 RADEON_COLOR_ARG( 1, C
);
723 RADEON_COLOR_ARG( 2, B
);
729 switch ( texUnit
->_CurrentCombine
->ModeA
) {
731 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
732 RADEON_ALPHA_ARG_B_ZERO
|
733 RADEON_BLEND_CTL_ADD
|
735 RADEON_ALPHA_ARG( 0, C
);
738 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
739 RADEON_BLEND_CTL_ADD
|
741 RADEON_ALPHA_ARG( 0, A
);
742 RADEON_ALPHA_ARG( 1, B
);
745 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
747 RADEON_BLEND_CTL_ADD
|
749 RADEON_ALPHA_ARG( 0, A
);
750 RADEON_ALPHA_ARG( 1, C
);
753 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
755 RADEON_BLEND_CTL_ADDSIGNED
|
757 RADEON_ALPHA_ARG( 0, A
);
758 RADEON_ALPHA_ARG( 1, C
);
761 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
763 RADEON_BLEND_CTL_SUBTRACT
|
765 RADEON_ALPHA_ARG( 0, A
);
766 RADEON_ALPHA_ARG( 1, C
);
769 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
771 RADEON_ALPHA_ARG( 0, B
);
772 RADEON_ALPHA_ARG( 1, A
);
773 RADEON_ALPHA_ARG( 2, C
);
776 case GL_MODULATE_ADD_ATI
:
777 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
779 RADEON_ALPHA_ARG( 0, A
);
780 RADEON_ALPHA_ARG( 1, C
);
781 RADEON_ALPHA_ARG( 2, B
);
783 case GL_MODULATE_SIGNED_ADD_ATI
:
784 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
786 RADEON_ALPHA_ARG( 0, A
);
787 RADEON_ALPHA_ARG( 1, C
);
788 RADEON_ALPHA_ARG( 2, B
);
790 case GL_MODULATE_SUBTRACT_ATI
:
791 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
793 RADEON_ALPHA_ARG( 0, A
);
794 RADEON_ALPHA_ARG( 1, C
);
795 RADEON_ALPHA_ARG( 2, B
);
801 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
802 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
803 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
807 * Apply the scale factor.
809 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
810 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
816 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
817 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
818 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
819 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
820 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
826 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
827 RADEON_MIN_FILTER_MASK | \
828 RADEON_MAG_FILTER_MASK | \
829 RADEON_MAX_ANISO_MASK | \
830 RADEON_YUV_TO_RGB | \
831 RADEON_YUV_TEMPERATURE_MASK | \
832 RADEON_CLAMP_S_MASK | \
833 RADEON_CLAMP_T_MASK | \
834 RADEON_BORDER_MODE_D3D )
836 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
837 RADEON_TXFORMAT_HEIGHT_MASK | \
838 RADEON_TXFORMAT_FORMAT_MASK | \
839 RADEON_TXFORMAT_F5_WIDTH_MASK | \
840 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
841 RADEON_TXFORMAT_ALPHA_IN_MAP | \
842 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
843 RADEON_TXFORMAT_NON_POWER2)
846 static void import_tex_obj_state( radeonContextPtr rmesa
,
848 radeonTexObjPtr texobj
)
850 GLuint
*cmd
= RADEON_DB_STATE( tex
[unit
] );
852 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
853 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
854 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
855 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
856 cmd
[TEX_PP_TXOFFSET
] = texobj
->pp_txoffset
;
857 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
859 if (texobj
->base
.tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
860 GLuint
*cube_cmd
= RADEON_DB_STATE( cube
[unit
] );
861 GLuint bytesPerFace
= texobj
->base
.totalSize
/ 6;
862 ASSERT(texobj
->base
.totalSize
% 6 == 0);
864 cube_cmd
[CUBE_PP_CUBIC_FACES
] = texobj
->pp_cubic_faces
;
865 /* dont know if this setup conforms to OpenGL..
866 * at least it matches the behavior of mesa software renderer
868 cube_cmd
[CUBE_PP_CUBIC_OFFSET_0
] = texobj
->pp_txoffset
; /* right */
869 cube_cmd
[CUBE_PP_CUBIC_OFFSET_1
] = texobj
->pp_txoffset
+ 1 * bytesPerFace
; /* left */
870 cube_cmd
[CUBE_PP_CUBIC_OFFSET_2
] = texobj
->pp_txoffset
+ 2 * bytesPerFace
; /* top */
871 cube_cmd
[CUBE_PP_CUBIC_OFFSET_3
] = texobj
->pp_txoffset
+ 3 * bytesPerFace
; /* bottom */
872 cube_cmd
[CUBE_PP_CUBIC_OFFSET_4
] = texobj
->pp_txoffset
+ 4 * bytesPerFace
; /* front */
873 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.cube
[unit
] );
874 cmd
[TEX_PP_TXOFFSET
] = texobj
->pp_txoffset
+ 5 * bytesPerFace
; /* back */
876 else if (texobj
->base
.tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
877 GLuint
*txr_cmd
= RADEON_DB_STATE( txr
[unit
] );
878 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
879 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
880 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.txr
[unit
] );
883 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.tex
[unit
] );
885 texobj
->dirty_state
&= ~(1<<unit
);
891 static void set_texgen_matrix( radeonContextPtr rmesa
,
893 const GLfloat
*s_plane
,
894 const GLfloat
*t_plane
,
895 const GLfloat
*r_plane
,
896 const GLfloat
*q_plane
)
898 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
899 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
900 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
901 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
903 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
904 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
905 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
906 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
908 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
909 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
910 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
911 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
913 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
914 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
915 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
916 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
918 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
919 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
922 /* Returns GL_FALSE if fallback required.
924 static GLboolean
radeon_validate_texgen( GLcontext
*ctx
, GLuint unit
)
926 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
927 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
928 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
929 GLuint tmp
= rmesa
->TexGenEnabled
;
930 static const GLfloat reflect
[16] = {
936 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
937 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
938 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
939 rmesa
->TexGenNeedNormals
[unit
] = 0;
941 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
942 /* Disabled, no fallback:
944 rmesa
->TexGenEnabled
|=
945 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
948 /* the r100 cannot do texgen for some coords and not for others
949 * we do not detect such cases (certainly can't do it here) and just
950 * ASSUME that when S and T are texgen enabled we do not need other
951 * non-texgen enabled coords, no matter if the R and Q bits are texgen
952 * enabled. Still check for mixed mode texgen for all coords.
954 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
955 (texUnit
->TexGenEnabled
& T_BIT
) &&
956 (texUnit
->GenModeS
== texUnit
->GenModeT
) ) {
957 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
958 (texUnit
->GenModeS
!= texUnit
->GenModeR
)) ||
959 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
960 (texUnit
->GenModeS
!= texUnit
->GenModeQ
)) ) {
961 /* Mixed modes, fallback:
963 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
964 fprintf(stderr
, "fallback mixed texgen\n");
967 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
970 /* some texgen mode not including both S and T bits */
971 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
972 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
976 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
977 /* need this here for vtxfmt presumably. Argh we need to set
978 this from way too many places, would be much easier if we could leave
979 tcl q coord always enabled as on r200) */
980 RADEON_STATECHANGE( rmesa
, tcl
);
981 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_Q_BIT(unit
);
984 switch (texUnit
->GenModeS
) {
985 case GL_OBJECT_LINEAR
:
986 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
987 set_texgen_matrix( rmesa
, unit
,
988 texUnit
->ObjectPlaneS
,
989 texUnit
->ObjectPlaneT
,
990 texUnit
->ObjectPlaneR
,
991 texUnit
->ObjectPlaneQ
);
995 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
996 set_texgen_matrix( rmesa
, unit
,
1000 texUnit
->EyePlaneQ
);
1003 case GL_REFLECTION_MAP_NV
:
1004 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
1005 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
1006 /* TODO: unknown if this is needed/correct */
1007 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
1008 reflect
+ 8, reflect
+ 12 );
1011 case GL_NORMAL_MAP_NV
:
1012 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
1013 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
1017 /* the mode which everyone uses :-( */
1019 /* Unsupported mode, fallback:
1021 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
1022 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
1026 if (tmp
!= rmesa
->TexGenEnabled
) {
1027 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1034 static void disable_tex( GLcontext
*ctx
, int unit
)
1036 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1038 if (rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & (RADEON_TEX_0_ENABLE
<<unit
)) {
1039 /* Texture unit disabled */
1040 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= NULL
) {
1041 /* The old texture is no longer bound to this texture unit.
1045 rmesa
->state
.texture
.unit
[unit
].texobj
->base
.bound
&= ~(1UL << unit
);
1046 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1049 RADEON_STATECHANGE( rmesa
, ctx
);
1050 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &=
1051 ~((RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
);
1053 RADEON_STATECHANGE( rmesa
, tcl
);
1054 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_ST_BIT(unit
) |
1055 RADEON_Q_BIT(unit
));
1057 if (rmesa
->TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
1058 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
1059 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1062 if (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE
) {
1063 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
1064 cubic_map bit on unit 2 when the unit is disabled, otherwise every
1065 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
1066 units, better be safe than sorry though).*/
1067 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
1068 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE
;
1072 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
1073 GLuint tmp
= rmesa
->TexGenEnabled
;
1075 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
1076 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
1077 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
1078 rmesa
->TexGenNeedNormals
[unit
] = 0;
1079 rmesa
->TexGenEnabled
|=
1080 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
1082 if (tmp
!= rmesa
->TexGenEnabled
) {
1083 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1084 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1090 static GLboolean
enable_tex_2d( GLcontext
*ctx
, int unit
)
1092 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1093 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1094 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1095 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1097 /* Need to load the 2d images associated with this unit.
1099 if (t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
1100 t
->pp_txformat
&= ~RADEON_TXFORMAT_NON_POWER2
;
1101 t
->base
.dirty_images
[0] = ~0;
1104 ASSERT(tObj
->Target
== GL_TEXTURE_2D
|| tObj
->Target
== GL_TEXTURE_1D
);
1106 if ( t
->base
.dirty_images
[0] ) {
1107 RADEON_FIREVERTICES( rmesa
);
1108 radeonSetTexImages( rmesa
, tObj
);
1109 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, 0 );
1110 if ( !t
->base
.memBlock
)
1117 static GLboolean
enable_tex_cube( GLcontext
*ctx
, int unit
)
1119 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1120 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1121 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1122 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1125 /* Need to load the 2d images associated with this unit.
1127 if (t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
1128 t
->pp_txformat
&= ~RADEON_TXFORMAT_NON_POWER2
;
1129 for (face
= 0; face
< 6; face
++)
1130 t
->base
.dirty_images
[face
] = ~0;
1133 ASSERT(tObj
->Target
== GL_TEXTURE_CUBE_MAP
);
1135 if ( t
->base
.dirty_images
[0] || t
->base
.dirty_images
[1] ||
1136 t
->base
.dirty_images
[2] || t
->base
.dirty_images
[3] ||
1137 t
->base
.dirty_images
[4] || t
->base
.dirty_images
[5] ) {
1139 RADEON_FIREVERTICES( rmesa
);
1140 /* layout memory space, once for all faces */
1141 radeonSetTexImages( rmesa
, tObj
);
1144 /* upload (per face) */
1145 for (face
= 0; face
< 6; face
++) {
1146 if (t
->base
.dirty_images
[face
]) {
1147 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, face
);
1151 if ( !t
->base
.memBlock
) {
1152 /* texmem alloc failed, use s/w fallback */
1159 static GLboolean
enable_tex_rect( GLcontext
*ctx
, int unit
)
1161 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1162 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1163 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1164 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1166 if (!(t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
)) {
1167 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
1168 t
->base
.dirty_images
[0] = ~0;
1171 ASSERT(tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
);
1173 if ( t
->base
.dirty_images
[0] ) {
1174 RADEON_FIREVERTICES( rmesa
);
1175 radeonSetTexImages( rmesa
, tObj
);
1176 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, 0 );
1177 if ( !t
->base
.memBlock
/* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
1178 fprintf(stderr
, "%s: upload failed\n", __FUNCTION__
);
1187 static GLboolean
update_tex_common( GLcontext
*ctx
, int unit
)
1189 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1190 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1191 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1192 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1195 /* Fallback if there's a texture border */
1196 if ( tObj
->Image
[0][tObj
->BaseLevel
]->Border
> 0 ) {
1197 fprintf(stderr
, "%s: border\n", __FUNCTION__
);
1201 /* Update state if this is a different texture object to last
1204 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= t
) {
1205 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= NULL
) {
1206 /* The old texture is no longer bound to this texture unit.
1210 rmesa
->state
.texture
.unit
[unit
].texobj
->base
.bound
&=
1214 rmesa
->state
.texture
.unit
[unit
].texobj
= t
;
1215 t
->base
.bound
|= (1UL << unit
);
1216 t
->dirty_state
|= 1<<unit
;
1217 driUpdateTextureLRU( (driTextureObject
*) t
); /* XXX: should be locked! */
1223 if ( !(rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & (RADEON_TEX_0_ENABLE
<<unit
))) {
1224 RADEON_STATECHANGE( rmesa
, ctx
);
1225 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1226 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1228 RADEON_STATECHANGE( rmesa
, tcl
);
1230 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_ST_BIT(unit
);
1232 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1235 if (t
->dirty_state
& (1<<unit
)) {
1236 import_tex_obj_state( rmesa
, unit
, t
);
1237 /* may need to update texture matrix (for texrect adjustments) */
1238 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1241 if (rmesa
->recheck_texgen
[unit
]) {
1242 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1243 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1244 rmesa
->recheck_texgen
[unit
] = 0;
1245 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1248 format
= tObj
->Image
[0][tObj
->BaseLevel
]->_BaseFormat
;
1249 if ( rmesa
->state
.texture
.unit
[unit
].format
!= format
||
1250 rmesa
->state
.texture
.unit
[unit
].envMode
!= texUnit
->EnvMode
) {
1251 rmesa
->state
.texture
.unit
[unit
].format
= format
;
1252 rmesa
->state
.texture
.unit
[unit
].envMode
= texUnit
->EnvMode
;
1253 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1258 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1259 return !t
->border_fallback
;
1264 static GLboolean
radeonUpdateTextureUnit( GLcontext
*ctx
, int unit
)
1266 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1268 if ( texUnit
->_ReallyEnabled
& (TEXTURE_RECT_BIT
) ) {
1269 return (enable_tex_rect( ctx
, unit
) &&
1270 update_tex_common( ctx
, unit
));
1272 else if ( texUnit
->_ReallyEnabled
& (TEXTURE_1D_BIT
| TEXTURE_2D_BIT
) ) {
1273 return (enable_tex_2d( ctx
, unit
) &&
1274 update_tex_common( ctx
, unit
));
1276 else if ( texUnit
->_ReallyEnabled
& (TEXTURE_CUBE_BIT
) ) {
1277 return (enable_tex_cube( ctx
, unit
) &&
1278 update_tex_common( ctx
, unit
));
1280 else if ( texUnit
->_ReallyEnabled
) {
1284 disable_tex( ctx
, unit
);
1289 void radeonUpdateTextureState( GLcontext
*ctx
)
1291 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1294 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1295 radeonUpdateTextureUnit( ctx
, 1 ) &&
1296 radeonUpdateTextureUnit( ctx
, 2 ));
1298 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1300 if (rmesa
->TclFallback
)
1301 radeonChooseVertexState( ctx
);