1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c,v 1.6 2002/12/16 16:18:59 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
42 #include "texformat.h"
45 #include "radeon_context.h"
46 #include "radeon_state.h"
47 #include "radeon_ioctl.h"
48 #include "radeon_swtcl.h"
49 #include "radeon_tex.h"
50 #include "radeon_tcl.h"
53 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
54 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
55 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
56 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
57 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
58 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
59 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
60 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
61 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
64 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
65 #define _COLOR_REV(f) \
66 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
68 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
69 #define _ALPHA_REV(f) \
70 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
72 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
74 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
75 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
76 && (tx_table[f].format != 0xffffffff) )
79 GLuint format
, filter
;
115 * This function computes the number of bytes of storage needed for
116 * the given texture object (all mipmap levels, all cube faces).
117 * The \c image[face][level].x/y/width/height parameters for upload/blitting
118 * are computed here. \c pp_txfilter, \c pp_txformat, etc. will be set here
121 * \param rmesa Context pointer
122 * \param tObj GL texture object whose images are to be posted to
125 static void radeonSetTexImages( radeonContextPtr rmesa
,
126 struct gl_texture_object
*tObj
)
128 radeonTexObjPtr t
= (radeonTexObjPtr
)tObj
->DriverData
;
129 const struct gl_texture_image
*baseImage
= tObj
->Image
[0][tObj
->BaseLevel
];
130 GLint curOffset
, blitWidth
;
133 GLint log2Width
, log2Height
, log2Depth
;
135 /* Set the hardware texture format
138 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
139 RADEON_TXFORMAT_ALPHA_IN_MAP
);
140 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
142 if ( VALID_FORMAT( baseImage
->TexFormat
->MesaFormat
) ) {
143 t
->pp_txformat
|= tx_table
[ baseImage
->TexFormat
->MesaFormat
].format
;
144 t
->pp_txfilter
|= tx_table
[ baseImage
->TexFormat
->MesaFormat
].filter
;
147 _mesa_problem(NULL
, "unexpected texture format in %s", __FUNCTION__
);
151 texelBytes
= baseImage
->TexFormat
->TexelBytes
;
153 /* Compute which mipmap levels we really want to send to the hardware.
156 if (tObj
->Target
!= GL_TEXTURE_CUBE_MAP
)
157 driCalculateTextureFirstLastLevel( (driTextureObject
*) t
);
159 /* r100 can't handle mipmaps for cube/3d textures, so don't waste
161 t
->base
.firstLevel
= t
->base
.lastLevel
= tObj
->BaseLevel
;
163 log2Width
= tObj
->Image
[0][t
->base
.firstLevel
]->WidthLog2
;
164 log2Height
= tObj
->Image
[0][t
->base
.firstLevel
]->HeightLog2
;
165 log2Depth
= tObj
->Image
[0][t
->base
.firstLevel
]->DepthLog2
;
167 numLevels
= t
->base
.lastLevel
- t
->base
.firstLevel
+ 1;
169 assert(numLevels
<= RADEON_MAX_TEXTURE_LEVELS
);
171 /* Calculate mipmap offsets and dimensions for blitting (uploading)
172 * The idea is that we lay out the mipmap levels within a block of
173 * memory organized as a rectangle of width BLIT_WIDTH_BYTES.
176 blitWidth
= BLIT_WIDTH_BYTES
;
179 /* figure out if this texture is suitable for tiling. */
180 if (texelBytes
&& (tObj
->Target
!= GL_TEXTURE_RECTANGLE_NV
)) {
181 if (rmesa
->texmicrotile
&& (baseImage
->Height
> 1)) {
182 /* allow 32 (bytes) x 1 mip (which will use two times the space
183 the non-tiled version would use) max if base texture is large enough */
184 if ((numLevels
== 1) ||
185 (((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 32) &&
186 (baseImage
->Width
* texelBytes
> 64)) ||
187 ((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 16)) {
188 /* R100 has two microtile bits (only the txoffset reg, not the blitter)
189 weird: X2 + OPT: 32bit correct, 16bit completely hosed
190 X2: 32bit correct, 16bit correct
191 OPT: 32bit large mips correct, small mips hosed, 16bit completely hosed */
192 t
->tile_bits
|= RADEON_TXO_MICRO_TILE_X2
/*| RADEON_TXO_MICRO_TILE_OPT*/;
195 if ((baseImage
->Width
* texelBytes
>= 256) && (baseImage
->Height
>= 16)) {
196 /* R100 disables macro tiling only if mip width is smaller than 256 bytes, and not
197 in the case if height is smaller than 16 (not 100% sure), as does the r200,
198 so need to disable macro tiling in that case */
199 if ((numLevels
== 1) || ((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 4)) {
200 t
->tile_bits
|= RADEON_TXO_MACRO_TILE
;
205 for (i
= 0; i
< numLevels
; i
++) {
206 const struct gl_texture_image
*texImage
;
209 texImage
= tObj
->Image
[0][i
+ t
->base
.firstLevel
];
213 /* find image size in bytes */
214 if (texImage
->IsCompressed
) {
215 /* need to calculate the size AFTER padding even though the texture is
216 submitted without padding.
217 Only handle pot textures currently - don't know if npot is even possible,
218 size calculation would certainly need (trivial) adjustments.
219 Align (and later pad) to 32byte, not sure what that 64byte blit width is
221 if ((t
->pp_txformat
& RADEON_TXFORMAT_FORMAT_MASK
) == RADEON_TXFORMAT_DXT1
) {
222 /* RGB_DXT1/RGBA_DXT1, 8 bytes per block */
223 if ((texImage
->Width
+ 3) < 8) /* width one block */
224 size
= texImage
->CompressedSize
* 4;
225 else if ((texImage
->Width
+ 3) < 16)
226 size
= texImage
->CompressedSize
* 2;
227 else size
= texImage
->CompressedSize
;
229 else /* DXT3/5, 16 bytes per block */
230 if ((texImage
->Width
+ 3) < 8)
231 size
= texImage
->CompressedSize
* 2;
232 else size
= texImage
->CompressedSize
;
234 else if (tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
235 size
= ((texImage
->Width
* texelBytes
+ 63) & ~63) * texImage
->Height
;
237 else if (t
->tile_bits
& RADEON_TXO_MICRO_TILE_X2
) {
238 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
239 though the actual offset may be different (if texture is less than
240 32 bytes width) to the untiled case */
241 int w
= (texImage
->Width
* texelBytes
* 2 + 31) & ~31;
242 size
= (w
* ((texImage
->Height
+ 1) / 2)) * texImage
->Depth
;
243 blitWidth
= MAX2(texImage
->Width
, 64 / texelBytes
);
246 int w
= (texImage
->Width
* texelBytes
+ 31) & ~31;
247 size
= w
* texImage
->Height
* texImage
->Depth
;
248 blitWidth
= MAX2(texImage
->Width
, 64 / texelBytes
);
252 /* Align to 32-byte offset. It is faster to do this unconditionally
253 * (no branch penalty).
256 curOffset
= (curOffset
+ 0x1f) & ~0x1f;
259 t
->image
[0][i
].x
= curOffset
; /* fix x and y coords up later together with offset */
260 t
->image
[0][i
].y
= 0;
261 t
->image
[0][i
].width
= MIN2(size
/ texelBytes
, blitWidth
);
262 t
->image
[0][i
].height
= (size
/ texelBytes
) / t
->image
[0][i
].width
;
265 t
->image
[0][i
].x
= curOffset
% BLIT_WIDTH_BYTES
;
266 t
->image
[0][i
].y
= curOffset
/ BLIT_WIDTH_BYTES
;
267 t
->image
[0][i
].width
= MIN2(size
, BLIT_WIDTH_BYTES
);
268 t
->image
[0][i
].height
= size
/ t
->image
[0][i
].width
;
272 /* for debugging only and only applicable to non-rectangle targets */
273 assert(size
% t
->image
[0][i
].width
== 0);
274 assert(t
->image
[0][i
].x
== 0
275 || (size
< BLIT_WIDTH_BYTES
&& t
->image
[0][i
].height
== 1));
280 "level %d: %dx%d x=%d y=%d w=%d h=%d size=%d at %d\n",
281 i
, texImage
->Width
, texImage
->Height
,
282 t
->image
[0][i
].x
, t
->image
[0][i
].y
,
283 t
->image
[0][i
].width
, t
->image
[0][i
].height
, size
, curOffset
);
289 /* Align the total size of texture memory block.
291 t
->base
.totalSize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
293 /* Setup remaining cube face blits, if needed */
294 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
295 const GLuint faceSize
= t
->base
.totalSize
;
297 /* reuse face 0 x/y/width/height - just update the offset when uploading */
298 for (face
= 1; face
< 6; face
++) {
299 for (i
= 0; i
< numLevels
; i
++) {
300 t
->image
[face
][i
].x
= t
->image
[0][i
].x
;
301 t
->image
[face
][i
].y
= t
->image
[0][i
].y
;
302 t
->image
[face
][i
].width
= t
->image
[0][i
].width
;
303 t
->image
[face
][i
].height
= t
->image
[0][i
].height
;
306 t
->base
.totalSize
= 6 * faceSize
; /* total texmem needed */
311 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
312 t
->pp_txfilter
|= (numLevels
- 1) << RADEON_MAX_MIP_LEVEL_SHIFT
;
314 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
315 RADEON_TXFORMAT_HEIGHT_MASK
|
316 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
317 RADEON_TXFORMAT_F5_WIDTH_MASK
|
318 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
319 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
320 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
322 if (tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
323 assert(log2Width
== log2Height
);
324 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_F5_WIDTH_SHIFT
) |
325 (log2Height
<< RADEON_TXFORMAT_F5_HEIGHT_SHIFT
) |
326 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE
));
327 t
->pp_cubic_faces
= ((log2Width
<< RADEON_FACE_WIDTH_1_SHIFT
) |
328 (log2Height
<< RADEON_FACE_HEIGHT_1_SHIFT
) |
329 (log2Width
<< RADEON_FACE_WIDTH_2_SHIFT
) |
330 (log2Height
<< RADEON_FACE_HEIGHT_2_SHIFT
) |
331 (log2Width
<< RADEON_FACE_WIDTH_3_SHIFT
) |
332 (log2Height
<< RADEON_FACE_HEIGHT_3_SHIFT
) |
333 (log2Width
<< RADEON_FACE_WIDTH_4_SHIFT
) |
334 (log2Height
<< RADEON_FACE_HEIGHT_4_SHIFT
));
337 t
->pp_txsize
= (((tObj
->Image
[0][t
->base
.firstLevel
]->Width
- 1) << 0) |
338 ((tObj
->Image
[0][t
->base
.firstLevel
]->Height
- 1) << 16));
340 /* Only need to round to nearest 32 for textures, but the blitter
341 * requires 64-byte aligned pitches, and we may/may not need the
342 * blitter. NPOT only!
344 if (baseImage
->IsCompressed
)
345 t
->pp_txpitch
= (tObj
->Image
[0][t
->base
.firstLevel
]->Width
+ 63) & ~(63);
347 t
->pp_txpitch
= ((tObj
->Image
[0][t
->base
.firstLevel
]->Width
* texelBytes
) + 63) & ~(63);
350 t
->dirty_state
= TEX_ALL
;
352 /* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */
357 /* ================================================================
358 * Texture combine functions
361 /* GL_ARB_texture_env_combine support
364 /* The color tables have combine functions for GL_SRC_COLOR,
365 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
367 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
370 RADEON_COLOR_ARG_A_T0_COLOR
,
371 RADEON_COLOR_ARG_A_T1_COLOR
,
372 RADEON_COLOR_ARG_A_T2_COLOR
375 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
376 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
377 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
380 RADEON_COLOR_ARG_A_T0_ALPHA
,
381 RADEON_COLOR_ARG_A_T1_ALPHA
,
382 RADEON_COLOR_ARG_A_T2_ALPHA
385 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
386 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
387 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
391 static GLuint radeon_tfactor_color
[] =
393 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
394 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
395 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
396 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
399 static GLuint radeon_primary_color
[] =
401 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
402 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
403 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
404 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
407 static GLuint radeon_previous_color
[] =
409 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
410 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
411 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
412 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
415 /* GL_ZERO table - indices 0-3
416 * GL_ONE table - indices 1-4
418 static GLuint radeon_zero_color
[] =
420 RADEON_COLOR_ARG_A_ZERO
,
421 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
422 RADEON_COLOR_ARG_A_ZERO
,
423 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
424 RADEON_COLOR_ARG_A_ZERO
428 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
430 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
433 RADEON_ALPHA_ARG_A_T0_ALPHA
,
434 RADEON_ALPHA_ARG_A_T1_ALPHA
,
435 RADEON_ALPHA_ARG_A_T2_ALPHA
438 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
439 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
440 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
444 static GLuint radeon_tfactor_alpha
[] =
446 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
447 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
450 static GLuint radeon_primary_alpha
[] =
452 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
453 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
456 static GLuint radeon_previous_alpha
[] =
458 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
459 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
462 /* GL_ZERO table - indices 0-1
463 * GL_ONE table - indices 1-2
465 static GLuint radeon_zero_alpha
[] =
467 RADEON_ALPHA_ARG_A_ZERO
,
468 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
469 RADEON_ALPHA_ARG_A_ZERO
473 /* Extract the arg from slot A, shift it into the correct argument slot
474 * and set the corresponding complement bit.
476 #define RADEON_COLOR_ARG( n, arg ) \
479 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
480 << RADEON_COLOR_ARG_##arg##_SHIFT); \
482 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
483 << RADEON_COMP_ARG_##arg##_SHIFT); \
486 #define RADEON_ALPHA_ARG( n, arg ) \
489 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
490 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
492 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
493 << RADEON_COMP_ARG_##arg##_SHIFT); \
497 /* ================================================================
498 * Texture unit state management
501 static GLboolean
radeonUpdateTextureEnv( GLcontext
*ctx
, int unit
)
503 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
504 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
505 GLuint color_combine
, alpha_combine
;
506 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
507 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
508 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
509 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
510 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
511 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
514 /* texUnit->_Current can be NULL if and only if the texture unit is
515 * not actually enabled.
517 assert( (texUnit
->_ReallyEnabled
== 0)
518 || (texUnit
->_Current
!= NULL
) );
520 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
521 fprintf( stderr
, "%s( %p, %d )\n", __FUNCTION__
, (void *)ctx
, unit
);
524 /* Set the texture environment state. Isn't this nice and clean?
525 * The chip will automagically set the texture alpha to 0xff when
526 * the texture format does not include an alpha component. This
527 * reduces the amount of special-casing we have to do, alpha-only
528 * textures being a notable exception. Doesn't work for luminance
529 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
531 /* Don't cache these results.
533 rmesa
->state
.texture
.unit
[unit
].format
= 0;
534 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
536 if ( !texUnit
->_ReallyEnabled
) {
537 color_combine
= color_combine0
;
538 alpha_combine
= alpha_combine0
;
541 GLuint color_arg
[3], alpha_arg
[3];
543 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
544 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
545 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
546 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
550 * Extract the color and alpha combine function arguments.
552 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
553 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
554 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
559 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
560 color_arg
[i
] = radeon_zero_color
[op
];
562 color_arg
[i
] = radeon_texture_color
[op
][unit
];
565 color_arg
[i
] = radeon_tfactor_color
[op
];
567 case GL_PRIMARY_COLOR
:
568 color_arg
[i
] = radeon_primary_color
[op
];
571 color_arg
[i
] = radeon_previous_color
[op
];
574 color_arg
[i
] = radeon_zero_color
[op
];
577 color_arg
[i
] = radeon_zero_color
[op
+1];
582 GLuint txunit
= srcRGBi
- GL_TEXTURE0
;
583 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
584 color_arg
[i
] = radeon_zero_color
[op
];
586 /* implement ogl 1.4/1.5 core spec here, not specification of
587 * GL_ARB_texture_env_crossbar (which would require disabling blending
588 * instead of undefined results when referencing not enabled texunit) */
589 color_arg
[i
] = radeon_texture_color
[op
][txunit
];
597 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
598 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
599 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
604 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
605 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
607 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
610 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
612 case GL_PRIMARY_COLOR
:
613 alpha_arg
[i
] = radeon_primary_alpha
[op
];
616 alpha_arg
[i
] = radeon_previous_alpha
[op
];
619 alpha_arg
[i
] = radeon_zero_alpha
[op
];
622 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
627 GLuint txunit
= srcAi
- GL_TEXTURE0
;
628 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
629 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
631 alpha_arg
[i
] = radeon_texture_alpha
[op
][txunit
];
640 * Build up the color and alpha combine functions.
642 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
644 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
645 RADEON_COLOR_ARG_B_ZERO
|
646 RADEON_BLEND_CTL_ADD
|
648 RADEON_COLOR_ARG( 0, C
);
651 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
652 RADEON_BLEND_CTL_ADD
|
654 RADEON_COLOR_ARG( 0, A
);
655 RADEON_COLOR_ARG( 1, B
);
658 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
660 RADEON_BLEND_CTL_ADD
|
662 RADEON_COLOR_ARG( 0, A
);
663 RADEON_COLOR_ARG( 1, C
);
666 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
668 RADEON_BLEND_CTL_ADDSIGNED
|
670 RADEON_COLOR_ARG( 0, A
);
671 RADEON_COLOR_ARG( 1, C
);
674 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
676 RADEON_BLEND_CTL_SUBTRACT
|
678 RADEON_COLOR_ARG( 0, A
);
679 RADEON_COLOR_ARG( 1, C
);
682 color_combine
= (RADEON_BLEND_CTL_BLEND
|
684 RADEON_COLOR_ARG( 0, B
);
685 RADEON_COLOR_ARG( 1, A
);
686 RADEON_COLOR_ARG( 2, C
);
689 case GL_DOT3_RGB_EXT
:
690 case GL_DOT3_RGBA_EXT
:
691 /* The EXT version of the DOT3 extension does not support the
692 * scale factor, but the ARB version (and the version in OpenGL
700 /* The R100 / RV200 only support a 1X multiplier in hardware
703 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
708 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
709 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
710 /* is it necessary to set this or will it be ignored anyway? */
714 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
715 RADEON_BLEND_CTL_DOT3
|
717 RADEON_COLOR_ARG( 0, A
);
718 RADEON_COLOR_ARG( 1, B
);
721 case GL_MODULATE_ADD_ATI
:
722 color_combine
= (RADEON_BLEND_CTL_ADD
|
724 RADEON_COLOR_ARG( 0, A
);
725 RADEON_COLOR_ARG( 1, C
);
726 RADEON_COLOR_ARG( 2, B
);
728 case GL_MODULATE_SIGNED_ADD_ATI
:
729 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
731 RADEON_COLOR_ARG( 0, A
);
732 RADEON_COLOR_ARG( 1, C
);
733 RADEON_COLOR_ARG( 2, B
);
735 case GL_MODULATE_SUBTRACT_ATI
:
736 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
738 RADEON_COLOR_ARG( 0, A
);
739 RADEON_COLOR_ARG( 1, C
);
740 RADEON_COLOR_ARG( 2, B
);
746 switch ( texUnit
->_CurrentCombine
->ModeA
) {
748 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
749 RADEON_ALPHA_ARG_B_ZERO
|
750 RADEON_BLEND_CTL_ADD
|
752 RADEON_ALPHA_ARG( 0, C
);
755 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
756 RADEON_BLEND_CTL_ADD
|
758 RADEON_ALPHA_ARG( 0, A
);
759 RADEON_ALPHA_ARG( 1, B
);
762 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
764 RADEON_BLEND_CTL_ADD
|
766 RADEON_ALPHA_ARG( 0, A
);
767 RADEON_ALPHA_ARG( 1, C
);
770 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
772 RADEON_BLEND_CTL_ADDSIGNED
|
774 RADEON_ALPHA_ARG( 0, A
);
775 RADEON_ALPHA_ARG( 1, C
);
778 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
780 RADEON_BLEND_CTL_SUBTRACT
|
782 RADEON_ALPHA_ARG( 0, A
);
783 RADEON_ALPHA_ARG( 1, C
);
786 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
788 RADEON_ALPHA_ARG( 0, B
);
789 RADEON_ALPHA_ARG( 1, A
);
790 RADEON_ALPHA_ARG( 2, C
);
793 case GL_MODULATE_ADD_ATI
:
794 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
796 RADEON_ALPHA_ARG( 0, A
);
797 RADEON_ALPHA_ARG( 1, C
);
798 RADEON_ALPHA_ARG( 2, B
);
800 case GL_MODULATE_SIGNED_ADD_ATI
:
801 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
803 RADEON_ALPHA_ARG( 0, A
);
804 RADEON_ALPHA_ARG( 1, C
);
805 RADEON_ALPHA_ARG( 2, B
);
807 case GL_MODULATE_SUBTRACT_ATI
:
808 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
810 RADEON_ALPHA_ARG( 0, A
);
811 RADEON_ALPHA_ARG( 1, C
);
812 RADEON_ALPHA_ARG( 2, B
);
818 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
819 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
820 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
824 * Apply the scale factor.
826 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
827 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
833 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
834 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
835 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
836 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
837 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
843 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
844 RADEON_MIN_FILTER_MASK | \
845 RADEON_MAG_FILTER_MASK | \
846 RADEON_MAX_ANISO_MASK | \
847 RADEON_YUV_TO_RGB | \
848 RADEON_YUV_TEMPERATURE_MASK | \
849 RADEON_CLAMP_S_MASK | \
850 RADEON_CLAMP_T_MASK | \
851 RADEON_BORDER_MODE_D3D )
853 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
854 RADEON_TXFORMAT_HEIGHT_MASK | \
855 RADEON_TXFORMAT_FORMAT_MASK | \
856 RADEON_TXFORMAT_F5_WIDTH_MASK | \
857 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
858 RADEON_TXFORMAT_ALPHA_IN_MAP | \
859 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
860 RADEON_TXFORMAT_NON_POWER2)
863 static void import_tex_obj_state( radeonContextPtr rmesa
,
865 radeonTexObjPtr texobj
)
867 /* do not use RADEON_DB_STATE to avoid stale texture caches */
868 int *cmd
= &rmesa
->hw
.tex
[unit
].cmd
[TEX_CMD_0
];
869 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
871 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
873 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
874 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
875 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
876 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
877 cmd
[TEX_PP_TXOFFSET
] = texobj
->pp_txoffset
;
878 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
880 if (texobj
->base
.tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
881 GLuint
*txr_cmd
= RADEON_DB_STATE( txr
[unit
] );
882 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
883 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
884 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.txr
[unit
] );
885 se_coord_fmt
|= RADEON_VTX_ST0_NONPARAMETRIC
<< unit
;
888 se_coord_fmt
&= ~(RADEON_VTX_ST0_NONPARAMETRIC
<< unit
);
890 if (texobj
->base
.tObj
->Target
== GL_TEXTURE_CUBE_MAP
) {
891 int *cube_cmd
= &rmesa
->hw
.cube
[unit
].cmd
[CUBE_CMD_0
];
892 GLuint bytesPerFace
= texobj
->base
.totalSize
/ 6;
893 ASSERT(texobj
->base
.totalSize
% 6 == 0);
895 RADEON_STATECHANGE( rmesa
, cube
[unit
] );
896 cube_cmd
[CUBE_PP_CUBIC_FACES
] = texobj
->pp_cubic_faces
;
897 /* dont know if this setup conforms to OpenGL..
898 * at least it matches the behavior of mesa software renderer
900 cube_cmd
[CUBE_PP_CUBIC_OFFSET_0
] = texobj
->pp_txoffset
; /* right */
901 cube_cmd
[CUBE_PP_CUBIC_OFFSET_1
] = texobj
->pp_txoffset
+ 1 * bytesPerFace
; /* left */
902 cube_cmd
[CUBE_PP_CUBIC_OFFSET_2
] = texobj
->pp_txoffset
+ 2 * bytesPerFace
; /* top */
903 cube_cmd
[CUBE_PP_CUBIC_OFFSET_3
] = texobj
->pp_txoffset
+ 3 * bytesPerFace
; /* bottom */
904 cube_cmd
[CUBE_PP_CUBIC_OFFSET_4
] = texobj
->pp_txoffset
+ 4 * bytesPerFace
; /* front */
905 cmd
[TEX_PP_TXOFFSET
] = texobj
->pp_txoffset
+ 5 * bytesPerFace
; /* back */
909 if (se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
]) {
910 RADEON_STATECHANGE( rmesa
, set
);
911 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
914 texobj
->dirty_state
&= ~(1<<unit
);
920 static void set_texgen_matrix( radeonContextPtr rmesa
,
922 const GLfloat
*s_plane
,
923 const GLfloat
*t_plane
,
924 const GLfloat
*r_plane
,
925 const GLfloat
*q_plane
)
927 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
928 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
929 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
930 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
932 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
933 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
934 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
935 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
937 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
938 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
939 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
940 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
942 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
943 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
944 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
945 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
947 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
948 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
951 /* Returns GL_FALSE if fallback required.
953 static GLboolean
radeon_validate_texgen( GLcontext
*ctx
, GLuint unit
)
955 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
956 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
957 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
958 GLuint tmp
= rmesa
->TexGenEnabled
;
959 static const GLfloat reflect
[16] = {
965 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
966 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
967 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
968 rmesa
->TexGenNeedNormals
[unit
] = 0;
970 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
971 /* Disabled, no fallback:
973 rmesa
->TexGenEnabled
|=
974 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
977 /* the r100 cannot do texgen for some coords and not for others
978 * we do not detect such cases (certainly can't do it here) and just
979 * ASSUME that when S and T are texgen enabled we do not need other
980 * non-texgen enabled coords, no matter if the R and Q bits are texgen
981 * enabled. Still check for mixed mode texgen for all coords.
983 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
984 (texUnit
->TexGenEnabled
& T_BIT
) &&
985 (texUnit
->GenModeS
== texUnit
->GenModeT
) ) {
986 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
987 (texUnit
->GenModeS
!= texUnit
->GenModeR
)) ||
988 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
989 (texUnit
->GenModeS
!= texUnit
->GenModeQ
)) ) {
990 /* Mixed modes, fallback:
992 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
993 fprintf(stderr
, "fallback mixed texgen\n");
996 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
999 /* some texgen mode not including both S and T bits */
1000 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
1001 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
1005 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
1006 /* need this here for vtxfmt presumably. Argh we need to set
1007 this from way too many places, would be much easier if we could leave
1008 tcl q coord always enabled as on r200) */
1009 RADEON_STATECHANGE( rmesa
, tcl
);
1010 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_Q_BIT(unit
);
1013 switch (texUnit
->GenModeS
) {
1014 case GL_OBJECT_LINEAR
:
1015 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
1016 set_texgen_matrix( rmesa
, unit
,
1017 texUnit
->ObjectPlaneS
,
1018 texUnit
->ObjectPlaneT
,
1019 texUnit
->ObjectPlaneR
,
1020 texUnit
->ObjectPlaneQ
);
1024 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
1025 set_texgen_matrix( rmesa
, unit
,
1029 texUnit
->EyePlaneQ
);
1032 case GL_REFLECTION_MAP_NV
:
1033 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
1034 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
1035 /* TODO: unknown if this is needed/correct */
1036 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
1037 reflect
+ 8, reflect
+ 12 );
1040 case GL_NORMAL_MAP_NV
:
1041 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
1042 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
1046 /* the mode which everyone uses :-( */
1048 /* Unsupported mode, fallback:
1050 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
1051 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
1055 if (tmp
!= rmesa
->TexGenEnabled
) {
1056 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1063 static void disable_tex( GLcontext
*ctx
, int unit
)
1065 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1067 if (rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & (RADEON_TEX_0_ENABLE
<<unit
)) {
1068 /* Texture unit disabled */
1069 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= NULL
) {
1070 /* The old texture is no longer bound to this texture unit.
1074 rmesa
->state
.texture
.unit
[unit
].texobj
->base
.bound
&= ~(1UL << unit
);
1075 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1078 RADEON_STATECHANGE( rmesa
, ctx
);
1079 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &=
1080 ~((RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
);
1082 RADEON_STATECHANGE( rmesa
, tcl
);
1083 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_ST_BIT(unit
) |
1084 RADEON_Q_BIT(unit
));
1086 if (rmesa
->TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
1087 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
1088 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1091 if (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE
) {
1092 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
1093 cubic_map bit on unit 2 when the unit is disabled, otherwise every
1094 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
1095 units, better be safe than sorry though).*/
1096 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
1097 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE
;
1101 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
1102 GLuint tmp
= rmesa
->TexGenEnabled
;
1104 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
1105 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
1106 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
1107 rmesa
->TexGenNeedNormals
[unit
] = 0;
1108 rmesa
->TexGenEnabled
|=
1109 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
1111 if (tmp
!= rmesa
->TexGenEnabled
) {
1112 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1113 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1119 static GLboolean
enable_tex_2d( GLcontext
*ctx
, int unit
)
1121 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1122 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1123 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1124 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1126 /* Need to load the 2d images associated with this unit.
1128 if (t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
1129 t
->pp_txformat
&= ~RADEON_TXFORMAT_NON_POWER2
;
1130 t
->base
.dirty_images
[0] = ~0;
1133 ASSERT(tObj
->Target
== GL_TEXTURE_2D
|| tObj
->Target
== GL_TEXTURE_1D
);
1135 if ( t
->base
.dirty_images
[0] ) {
1136 RADEON_FIREVERTICES( rmesa
);
1137 radeonSetTexImages( rmesa
, tObj
);
1138 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, 0 );
1139 if ( !t
->base
.memBlock
)
1146 static GLboolean
enable_tex_cube( GLcontext
*ctx
, int unit
)
1148 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1149 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1150 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1151 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1154 /* Need to load the 2d images associated with this unit.
1156 if (t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
1157 t
->pp_txformat
&= ~RADEON_TXFORMAT_NON_POWER2
;
1158 for (face
= 0; face
< 6; face
++)
1159 t
->base
.dirty_images
[face
] = ~0;
1162 ASSERT(tObj
->Target
== GL_TEXTURE_CUBE_MAP
);
1164 if ( t
->base
.dirty_images
[0] || t
->base
.dirty_images
[1] ||
1165 t
->base
.dirty_images
[2] || t
->base
.dirty_images
[3] ||
1166 t
->base
.dirty_images
[4] || t
->base
.dirty_images
[5] ) {
1168 RADEON_FIREVERTICES( rmesa
);
1169 /* layout memory space, once for all faces */
1170 radeonSetTexImages( rmesa
, tObj
);
1173 /* upload (per face) */
1174 for (face
= 0; face
< 6; face
++) {
1175 if (t
->base
.dirty_images
[face
]) {
1176 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, face
);
1180 if ( !t
->base
.memBlock
) {
1181 /* texmem alloc failed, use s/w fallback */
1188 static GLboolean
enable_tex_rect( GLcontext
*ctx
, int unit
)
1190 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1191 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1192 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1193 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1195 if (!(t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
)) {
1196 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
1197 t
->base
.dirty_images
[0] = ~0;
1200 ASSERT(tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
);
1202 if ( t
->base
.dirty_images
[0] ) {
1203 RADEON_FIREVERTICES( rmesa
);
1204 radeonSetTexImages( rmesa
, tObj
);
1205 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, 0 );
1206 if ( !t
->base
.memBlock
/* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
1207 fprintf(stderr
, "%s: upload failed\n", __FUNCTION__
);
1216 static GLboolean
update_tex_common( GLcontext
*ctx
, int unit
)
1218 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1219 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1220 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1221 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1224 /* Fallback if there's a texture border */
1225 if ( tObj
->Image
[0][tObj
->BaseLevel
]->Border
> 0 ) {
1226 fprintf(stderr
, "%s: border\n", __FUNCTION__
);
1229 /* yuv conversion only works in first unit */
1230 if (unit
!= 0 && (t
->pp_txfilter
& RADEON_YUV_TO_RGB
))
1233 /* Update state if this is a different texture object to last
1236 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= t
) {
1237 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= NULL
) {
1238 /* The old texture is no longer bound to this texture unit.
1242 rmesa
->state
.texture
.unit
[unit
].texobj
->base
.bound
&=
1246 rmesa
->state
.texture
.unit
[unit
].texobj
= t
;
1247 t
->base
.bound
|= (1UL << unit
);
1248 t
->dirty_state
|= 1<<unit
;
1249 driUpdateTextureLRU( (driTextureObject
*) t
); /* XXX: should be locked! */
1255 if ( !(rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & (RADEON_TEX_0_ENABLE
<<unit
))) {
1256 RADEON_STATECHANGE( rmesa
, ctx
);
1257 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1258 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1260 RADEON_STATECHANGE( rmesa
, tcl
);
1262 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_ST_BIT(unit
);
1264 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1267 if (t
->dirty_state
& (1<<unit
)) {
1268 import_tex_obj_state( rmesa
, unit
, t
);
1269 /* may need to update texture matrix (for texrect adjustments) */
1270 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1273 if (rmesa
->recheck_texgen
[unit
]) {
1274 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1275 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1276 rmesa
->recheck_texgen
[unit
] = 0;
1277 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1280 format
= tObj
->Image
[0][tObj
->BaseLevel
]->_BaseFormat
;
1281 if ( rmesa
->state
.texture
.unit
[unit
].format
!= format
||
1282 rmesa
->state
.texture
.unit
[unit
].envMode
!= texUnit
->EnvMode
) {
1283 rmesa
->state
.texture
.unit
[unit
].format
= format
;
1284 rmesa
->state
.texture
.unit
[unit
].envMode
= texUnit
->EnvMode
;
1285 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1290 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1291 return !t
->border_fallback
;
1296 static GLboolean
radeonUpdateTextureUnit( GLcontext
*ctx
, int unit
)
1298 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1300 if ( texUnit
->_ReallyEnabled
& (TEXTURE_RECT_BIT
) ) {
1301 return (enable_tex_rect( ctx
, unit
) &&
1302 update_tex_common( ctx
, unit
));
1304 else if ( texUnit
->_ReallyEnabled
& (TEXTURE_1D_BIT
| TEXTURE_2D_BIT
) ) {
1305 return (enable_tex_2d( ctx
, unit
) &&
1306 update_tex_common( ctx
, unit
));
1308 else if ( texUnit
->_ReallyEnabled
& (TEXTURE_CUBE_BIT
) ) {
1309 return (enable_tex_cube( ctx
, unit
) &&
1310 update_tex_common( ctx
, unit
));
1312 else if ( texUnit
->_ReallyEnabled
) {
1316 disable_tex( ctx
, unit
);
1321 void radeonUpdateTextureState( GLcontext
*ctx
)
1323 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1326 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1327 radeonUpdateTextureUnit( ctx
, 1 ) &&
1328 radeonUpdateTextureUnit( ctx
, 2 ));
1330 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1332 if (rmesa
->TclFallback
)
1333 radeonChooseVertexState( ctx
);