1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
36 #include "main/glheader.h"
37 #include "main/imports.h"
38 #include "main/colormac.h"
39 #include "main/context.h"
40 #include "main/macros.h"
41 #include "main/teximage.h"
42 #include "main/texstate.h"
43 #include "main/texobj.h"
44 #include "main/enums.h"
45 #include "main/samplerobj.h"
47 #include "radeon_context.h"
48 #include "radeon_mipmap_tree.h"
49 #include "radeon_state.h"
50 #include "radeon_ioctl.h"
51 #include "radeon_swtcl.h"
52 #include "radeon_tex.h"
53 #include "radeon_tcl.h"
56 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
57 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
58 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
59 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
60 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
61 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
62 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
63 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
64 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
66 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
67 && (tx_table[f].format != 0xffffffff) )
70 GLuint format
, filter
;
73 /* XXX verify this table against MESA_FORMAT_x values */
74 static const struct tx_table tx_table
[] =
76 [ MESA_FORMAT_NONE
] = { 0xffffffff, 0 },
77 [ MESA_FORMAT_A8B8G8R8_UNORM
] = { RADEON_TXFORMAT_RGBA8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
78 [ MESA_FORMAT_R8G8B8A8_UNORM
] = { RADEON_TXFORMAT_RGBA8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
79 [ MESA_FORMAT_B8G8R8A8_UNORM
] = { RADEON_TXFORMAT_ARGB8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
80 [ MESA_FORMAT_A8R8G8B8_UNORM
] = { RADEON_TXFORMAT_ARGB8888
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
81 [ MESA_FORMAT_BGR_UNORM8
] = { RADEON_TXFORMAT_ARGB8888
, 0 },
82 [ MESA_FORMAT_B5G6R5_UNORM
] = { RADEON_TXFORMAT_RGB565
, 0 },
83 [ MESA_FORMAT_R5G6B5_UNORM
] = { RADEON_TXFORMAT_RGB565
, 0 },
84 [ MESA_FORMAT_B4G4R4A4_UNORM
] = { RADEON_TXFORMAT_ARGB4444
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
85 [ MESA_FORMAT_A4R4G4B4_UNORM
] = { RADEON_TXFORMAT_ARGB4444
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
86 [ MESA_FORMAT_B5G5R5A1_UNORM
] = { RADEON_TXFORMAT_ARGB1555
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
87 [ MESA_FORMAT_A1R5G5B5_UNORM
] = { RADEON_TXFORMAT_ARGB1555
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
88 [ MESA_FORMAT_L8A8_UNORM
] = { RADEON_TXFORMAT_AL88
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
89 [ MESA_FORMAT_A8L8_UNORM
] = { RADEON_TXFORMAT_AL88
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
90 [ MESA_FORMAT_A_UNORM8
] = { RADEON_TXFORMAT_A8
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
91 [ MESA_FORMAT_L_UNORM8
] = { RADEON_TXFORMAT_L8
, 0 },
92 [ MESA_FORMAT_I_UNORM8
] = { RADEON_TXFORMAT_I8
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
93 [ MESA_FORMAT_YCBCR
] = { RADEON_TXFORMAT_YCBCR
, RADEON_YUV_TO_RGB
},
94 [ MESA_FORMAT_YCBCR_REV
] = { RADEON_TXFORMAT_YCBCR_REV
, RADEON_YUV_TO_RGB
},
95 [ MESA_FORMAT_RGB_FXT1
] = { 0xffffffff, 0 },
96 [ MESA_FORMAT_RGBA_FXT1
] = { 0xffffffff, 0 },
97 [ MESA_FORMAT_RGB_DXT1
] = { RADEON_TXFORMAT_RGB_DXT1
, 0 },
98 [ MESA_FORMAT_RGBA_DXT1
] = { RADEON_TXFORMAT_RGBA_DXT1
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
99 [ MESA_FORMAT_RGBA_DXT3
] = { RADEON_TXFORMAT_RGBA_DXT3
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
100 [ MESA_FORMAT_RGBA_DXT5
] = { RADEON_TXFORMAT_RGBA_DXT5
| RADEON_TXFORMAT_ALPHA_IN_MAP
, 0 },
103 /* ================================================================
104 * Texture combine functions
107 /* GL_ARB_texture_env_combine support
110 /* The color tables have combine functions for GL_SRC_COLOR,
111 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
113 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
116 RADEON_COLOR_ARG_A_T0_COLOR
,
117 RADEON_COLOR_ARG_A_T1_COLOR
,
118 RADEON_COLOR_ARG_A_T2_COLOR
121 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
122 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
123 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
126 RADEON_COLOR_ARG_A_T0_ALPHA
,
127 RADEON_COLOR_ARG_A_T1_ALPHA
,
128 RADEON_COLOR_ARG_A_T2_ALPHA
131 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
132 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
133 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
137 static GLuint radeon_tfactor_color
[] =
139 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
140 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
141 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
142 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
145 static GLuint radeon_primary_color
[] =
147 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
148 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
149 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
150 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
153 static GLuint radeon_previous_color
[] =
155 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
156 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
157 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
158 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
161 /* GL_ZERO table - indices 0-3
162 * GL_ONE table - indices 1-4
164 static GLuint radeon_zero_color
[] =
166 RADEON_COLOR_ARG_A_ZERO
,
167 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
168 RADEON_COLOR_ARG_A_ZERO
,
169 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
170 RADEON_COLOR_ARG_A_ZERO
174 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
176 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
179 RADEON_ALPHA_ARG_A_T0_ALPHA
,
180 RADEON_ALPHA_ARG_A_T1_ALPHA
,
181 RADEON_ALPHA_ARG_A_T2_ALPHA
184 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
185 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
186 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
190 static GLuint radeon_tfactor_alpha
[] =
192 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
193 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
196 static GLuint radeon_primary_alpha
[] =
198 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
199 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
202 static GLuint radeon_previous_alpha
[] =
204 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
205 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
208 /* GL_ZERO table - indices 0-1
209 * GL_ONE table - indices 1-2
211 static GLuint radeon_zero_alpha
[] =
213 RADEON_ALPHA_ARG_A_ZERO
,
214 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
215 RADEON_ALPHA_ARG_A_ZERO
219 /* Extract the arg from slot A, shift it into the correct argument slot
220 * and set the corresponding complement bit.
222 #define RADEON_COLOR_ARG( n, arg ) \
225 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
226 << RADEON_COLOR_ARG_##arg##_SHIFT); \
228 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
229 << RADEON_COMP_ARG_##arg##_SHIFT); \
232 #define RADEON_ALPHA_ARG( n, arg ) \
235 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
236 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
238 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
239 << RADEON_COMP_ARG_##arg##_SHIFT); \
243 /* ================================================================
244 * Texture unit state management
247 static GLboolean
radeonUpdateTextureEnv( struct gl_context
*ctx
, int unit
)
249 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
250 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
251 GLuint color_combine
, alpha_combine
;
252 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
253 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
254 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
255 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
256 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
257 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
260 if ( RADEON_DEBUG
& RADEON_TEXTURE
) {
261 fprintf( stderr
, "%s( %p, %d )\n", __FUNCTION__
, (void *)ctx
, unit
);
264 /* Set the texture environment state. Isn't this nice and clean?
265 * The chip will automagically set the texture alpha to 0xff when
266 * the texture format does not include an alpha component. This
267 * reduces the amount of special-casing we have to do, alpha-only
268 * textures being a notable exception. Doesn't work for luminance
269 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
271 /* Don't cache these results.
273 rmesa
->state
.texture
.unit
[unit
].format
= 0;
274 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
276 if ( !texUnit
->_Current
) {
277 color_combine
= color_combine0
;
278 alpha_combine
= alpha_combine0
;
281 GLuint color_arg
[3], alpha_arg
[3];
283 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
284 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
285 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
286 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
290 * Extract the color and alpha combine function arguments.
292 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
293 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
294 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
299 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
300 color_arg
[i
] = radeon_zero_color
[op
];
302 color_arg
[i
] = radeon_texture_color
[op
][unit
];
305 color_arg
[i
] = radeon_tfactor_color
[op
];
307 case GL_PRIMARY_COLOR
:
308 color_arg
[i
] = radeon_primary_color
[op
];
311 color_arg
[i
] = radeon_previous_color
[op
];
314 color_arg
[i
] = radeon_zero_color
[op
];
317 color_arg
[i
] = radeon_zero_color
[op
+1];
322 GLuint txunit
= srcRGBi
- GL_TEXTURE0
;
323 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
324 color_arg
[i
] = radeon_zero_color
[op
];
326 /* implement ogl 1.4/1.5 core spec here, not specification of
327 * GL_ARB_texture_env_crossbar (which would require disabling blending
328 * instead of undefined results when referencing not enabled texunit) */
329 color_arg
[i
] = radeon_texture_color
[op
][txunit
];
337 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
338 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
339 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
344 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
345 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
347 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
350 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
352 case GL_PRIMARY_COLOR
:
353 alpha_arg
[i
] = radeon_primary_alpha
[op
];
356 alpha_arg
[i
] = radeon_previous_alpha
[op
];
359 alpha_arg
[i
] = radeon_zero_alpha
[op
];
362 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
367 GLuint txunit
= srcAi
- GL_TEXTURE0
;
368 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
369 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
371 alpha_arg
[i
] = radeon_texture_alpha
[op
][txunit
];
380 * Build up the color and alpha combine functions.
382 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
384 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
385 RADEON_COLOR_ARG_B_ZERO
|
386 RADEON_BLEND_CTL_ADD
|
388 RADEON_COLOR_ARG( 0, C
);
391 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
392 RADEON_BLEND_CTL_ADD
|
394 RADEON_COLOR_ARG( 0, A
);
395 RADEON_COLOR_ARG( 1, B
);
398 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
400 RADEON_BLEND_CTL_ADD
|
402 RADEON_COLOR_ARG( 0, A
);
403 RADEON_COLOR_ARG( 1, C
);
406 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
408 RADEON_BLEND_CTL_ADDSIGNED
|
410 RADEON_COLOR_ARG( 0, A
);
411 RADEON_COLOR_ARG( 1, C
);
414 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
416 RADEON_BLEND_CTL_SUBTRACT
|
418 RADEON_COLOR_ARG( 0, A
);
419 RADEON_COLOR_ARG( 1, C
);
422 color_combine
= (RADEON_BLEND_CTL_BLEND
|
424 RADEON_COLOR_ARG( 0, B
);
425 RADEON_COLOR_ARG( 1, A
);
426 RADEON_COLOR_ARG( 2, C
);
429 case GL_DOT3_RGB_EXT
:
430 case GL_DOT3_RGBA_EXT
:
431 /* The EXT version of the DOT3 extension does not support the
432 * scale factor, but the ARB version (and the version in OpenGL
440 /* The R100 / RV200 only support a 1X multiplier in hardware
443 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
448 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
449 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
450 /* is it necessary to set this or will it be ignored anyway? */
454 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
455 RADEON_BLEND_CTL_DOT3
|
457 RADEON_COLOR_ARG( 0, A
);
458 RADEON_COLOR_ARG( 1, B
);
461 case GL_MODULATE_ADD_ATI
:
462 color_combine
= (RADEON_BLEND_CTL_ADD
|
464 RADEON_COLOR_ARG( 0, A
);
465 RADEON_COLOR_ARG( 1, C
);
466 RADEON_COLOR_ARG( 2, B
);
468 case GL_MODULATE_SIGNED_ADD_ATI
:
469 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
471 RADEON_COLOR_ARG( 0, A
);
472 RADEON_COLOR_ARG( 1, C
);
473 RADEON_COLOR_ARG( 2, B
);
475 case GL_MODULATE_SUBTRACT_ATI
:
476 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
478 RADEON_COLOR_ARG( 0, A
);
479 RADEON_COLOR_ARG( 1, C
);
480 RADEON_COLOR_ARG( 2, B
);
486 switch ( texUnit
->_CurrentCombine
->ModeA
) {
488 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
489 RADEON_ALPHA_ARG_B_ZERO
|
490 RADEON_BLEND_CTL_ADD
|
492 RADEON_ALPHA_ARG( 0, C
);
495 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
496 RADEON_BLEND_CTL_ADD
|
498 RADEON_ALPHA_ARG( 0, A
);
499 RADEON_ALPHA_ARG( 1, B
);
502 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
504 RADEON_BLEND_CTL_ADD
|
506 RADEON_ALPHA_ARG( 0, A
);
507 RADEON_ALPHA_ARG( 1, C
);
510 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
512 RADEON_BLEND_CTL_ADDSIGNED
|
514 RADEON_ALPHA_ARG( 0, A
);
515 RADEON_ALPHA_ARG( 1, C
);
518 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
520 RADEON_BLEND_CTL_SUBTRACT
|
522 RADEON_ALPHA_ARG( 0, A
);
523 RADEON_ALPHA_ARG( 1, C
);
526 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
528 RADEON_ALPHA_ARG( 0, B
);
529 RADEON_ALPHA_ARG( 1, A
);
530 RADEON_ALPHA_ARG( 2, C
);
533 case GL_MODULATE_ADD_ATI
:
534 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
536 RADEON_ALPHA_ARG( 0, A
);
537 RADEON_ALPHA_ARG( 1, C
);
538 RADEON_ALPHA_ARG( 2, B
);
540 case GL_MODULATE_SIGNED_ADD_ATI
:
541 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
543 RADEON_ALPHA_ARG( 0, A
);
544 RADEON_ALPHA_ARG( 1, C
);
545 RADEON_ALPHA_ARG( 2, B
);
547 case GL_MODULATE_SUBTRACT_ATI
:
548 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
550 RADEON_ALPHA_ARG( 0, A
);
551 RADEON_ALPHA_ARG( 1, C
);
552 RADEON_ALPHA_ARG( 2, B
);
558 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
559 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
560 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
564 * Apply the scale factor.
566 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
567 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
573 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
574 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
575 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
576 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
577 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
583 void radeonSetTexBuffer2(__DRIcontext
*pDRICtx
, GLint target
, GLint texture_format
,
584 __DRIdrawable
*dPriv
)
586 struct gl_texture_object
*texObj
;
587 struct gl_texture_image
*texImage
;
588 struct radeon_renderbuffer
*rb
;
589 radeon_texture_image
*rImage
;
590 radeonContextPtr radeon
;
591 struct radeon_framebuffer
*rfb
;
594 mesa_format texFormat
;
596 radeon
= pDRICtx
->driverPrivate
;
598 rfb
= dPriv
->driverPrivate
;
599 texObj
= _mesa_get_current_tex_object(&radeon
->glCtx
, target
);
600 texImage
= _mesa_get_tex_image(&radeon
->glCtx
, texObj
, target
, 0);
602 rImage
= get_radeon_texture_image(texImage
);
603 t
= radeon_tex_obj(texObj
);
608 radeon_update_renderbuffers(pDRICtx
, dPriv
, GL_TRUE
);
609 rb
= rfb
->color_rb
[0];
610 if (rb
->bo
== NULL
) {
611 /* Failed to BO for the buffer */
615 _mesa_lock_texture(&radeon
->glCtx
, texObj
);
617 radeon_bo_unref(t
->bo
);
621 radeon_bo_unref(rImage
->bo
);
625 radeon_miptree_unreference(&t
->mt
);
626 radeon_miptree_unreference(&rImage
->mt
);
629 radeon_bo_ref(rImage
->bo
);
631 radeon_bo_ref(t
->bo
);
633 t
->image_override
= GL_TRUE
;
634 t
->override_offset
= 0;
637 if (texture_format
== __DRI_TEXTURE_FORMAT_RGB
) {
638 t
->pp_txformat
= tx_table
[MESA_FORMAT_BGR_UNORM8
].format
;
639 texFormat
= MESA_FORMAT_BGR_UNORM8
;
642 t
->pp_txformat
= tx_table
[MESA_FORMAT_B8G8R8A8_UNORM
].format
;
643 texFormat
= MESA_FORMAT_B8G8R8A8_UNORM
;
645 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_B8G8R8A8_UNORM
].filter
;
649 texFormat
= MESA_FORMAT_BGR_UNORM8
;
650 t
->pp_txformat
= tx_table
[MESA_FORMAT_BGR_UNORM8
].format
;
651 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_BGR_UNORM8
].filter
;
654 texFormat
= MESA_FORMAT_B5G6R5_UNORM
;
655 t
->pp_txformat
= tx_table
[MESA_FORMAT_B5G6R5_UNORM
].format
;
656 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_B5G6R5_UNORM
].filter
;
660 _mesa_init_teximage_fields(&radeon
->glCtx
, texImage
,
661 rb
->base
.Base
.Width
, rb
->base
.Base
.Height
,
664 rImage
->base
.RowStride
= rb
->pitch
/ rb
->cpp
;
666 t
->pp_txpitch
&= (1 << 13) -1;
667 pitch_val
= rb
->pitch
;
669 t
->pp_txsize
= ((rb
->base
.Base
.Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
670 | ((rb
->base
.Base
.Height
- 1) << RADEON_TEX_VSIZE_SHIFT
);
671 if (target
== GL_TEXTURE_RECTANGLE_NV
) {
672 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
673 t
->pp_txpitch
= pitch_val
;
676 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
677 RADEON_TXFORMAT_HEIGHT_MASK
|
678 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
679 RADEON_TXFORMAT_F5_WIDTH_MASK
|
680 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
681 t
->pp_txformat
|= ((texImage
->WidthLog2
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
682 (texImage
->HeightLog2
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
684 t
->validated
= GL_TRUE
;
685 _mesa_unlock_texture(&radeon
->glCtx
, texObj
);
690 void radeonSetTexBuffer(__DRIcontext
*pDRICtx
, GLint target
, __DRIdrawable
*dPriv
)
692 radeonSetTexBuffer2(pDRICtx
, target
, __DRI_TEXTURE_FORMAT_RGBA
, dPriv
);
696 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
697 RADEON_MIN_FILTER_MASK | \
698 RADEON_MAG_FILTER_MASK | \
699 RADEON_MAX_ANISO_MASK | \
700 RADEON_YUV_TO_RGB | \
701 RADEON_YUV_TEMPERATURE_MASK | \
702 RADEON_CLAMP_S_MASK | \
703 RADEON_CLAMP_T_MASK | \
704 RADEON_BORDER_MODE_D3D )
706 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
707 RADEON_TXFORMAT_HEIGHT_MASK | \
708 RADEON_TXFORMAT_FORMAT_MASK | \
709 RADEON_TXFORMAT_F5_WIDTH_MASK | \
710 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
711 RADEON_TXFORMAT_ALPHA_IN_MAP | \
712 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
713 RADEON_TXFORMAT_NON_POWER2)
716 static void disable_tex_obj_state( r100ContextPtr rmesa
,
719 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
721 RADEON_STATECHANGE( rmesa
, tcl
);
722 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_ST_BIT(unit
) |
725 if (rmesa
->radeon
.TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
726 TCL_FALLBACK( &rmesa
->radeon
.glCtx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
727 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
730 if (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE
) {
731 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
732 cubic_map bit on unit 2 when the unit is disabled, otherwise every
733 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
734 units, better be safe than sorry though).*/
735 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
736 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE
;
740 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
741 GLuint tmp
= rmesa
->TexGenEnabled
;
743 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
744 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
745 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
746 rmesa
->TexGenNeedNormals
[unit
] = 0;
747 rmesa
->TexGenEnabled
|=
748 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
750 if (tmp
!= rmesa
->TexGenEnabled
) {
751 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
752 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
757 static void import_tex_obj_state( r100ContextPtr rmesa
,
759 radeonTexObjPtr texobj
)
761 /* do not use RADEON_DB_STATE to avoid stale texture caches */
762 uint32_t *cmd
= &rmesa
->hw
.tex
[unit
].cmd
[TEX_CMD_0
];
763 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
765 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
767 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
768 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
769 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
770 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
771 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
773 if (texobj
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
774 uint32_t *txr_cmd
= &rmesa
->hw
.txr
[unit
].cmd
[TXR_CMD_0
];
775 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
776 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
777 RADEON_STATECHANGE( rmesa
, txr
[unit
] );
780 if (texobj
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
781 se_coord_fmt
|= RADEON_VTX_ST0_NONPARAMETRIC
<< unit
;
784 se_coord_fmt
&= ~(RADEON_VTX_ST0_NONPARAMETRIC
<< unit
);
786 if (texobj
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
787 uint32_t *cube_cmd
= &rmesa
->hw
.cube
[unit
].cmd
[CUBE_CMD_0
];
789 RADEON_STATECHANGE( rmesa
, cube
[unit
] );
790 cube_cmd
[CUBE_PP_CUBIC_FACES
] = texobj
->pp_cubic_faces
;
791 /* state filled out in the cube_emit */
795 if (se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
]) {
796 RADEON_STATECHANGE( rmesa
, set
);
797 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
800 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
804 static void set_texgen_matrix( r100ContextPtr rmesa
,
806 const GLfloat
*s_plane
,
807 const GLfloat
*t_plane
,
808 const GLfloat
*r_plane
,
809 const GLfloat
*q_plane
)
811 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
812 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
813 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
814 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
816 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
817 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
818 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
819 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
821 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
822 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
823 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
824 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
826 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
827 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
828 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
829 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
831 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
832 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
835 /* Returns GL_FALSE if fallback required.
837 static GLboolean
radeon_validate_texgen( struct gl_context
*ctx
, GLuint unit
)
839 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
840 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
841 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
842 GLuint tmp
= rmesa
->TexGenEnabled
;
843 static const GLfloat reflect
[16] = {
849 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
850 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
851 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
852 rmesa
->TexGenNeedNormals
[unit
] = 0;
854 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
855 /* Disabled, no fallback:
857 rmesa
->TexGenEnabled
|=
858 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
861 /* the r100 cannot do texgen for some coords and not for others
862 * we do not detect such cases (certainly can't do it here) and just
863 * ASSUME that when S and T are texgen enabled we do not need other
864 * non-texgen enabled coords, no matter if the R and Q bits are texgen
865 * enabled. Still check for mixed mode texgen for all coords.
867 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
868 (texUnit
->TexGenEnabled
& T_BIT
) &&
869 (texUnit
->GenS
.Mode
== texUnit
->GenT
.Mode
) ) {
870 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
871 (texUnit
->GenS
.Mode
!= texUnit
->GenR
.Mode
)) ||
872 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
873 (texUnit
->GenS
.Mode
!= texUnit
->GenQ
.Mode
)) ) {
874 /* Mixed modes, fallback:
876 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
877 fprintf(stderr
, "fallback mixed texgen\n");
880 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
883 /* some texgen mode not including both S and T bits */
884 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
885 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
889 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
890 /* need this here for vtxfmt presumably. Argh we need to set
891 this from way too many places, would be much easier if we could leave
892 tcl q coord always enabled as on r200) */
893 RADEON_STATECHANGE( rmesa
, tcl
);
894 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_Q_BIT(unit
);
897 switch (texUnit
->GenS
.Mode
) {
898 case GL_OBJECT_LINEAR
:
899 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
900 set_texgen_matrix( rmesa
, unit
,
901 texUnit
->GenS
.ObjectPlane
,
902 texUnit
->GenT
.ObjectPlane
,
903 texUnit
->GenR
.ObjectPlane
,
904 texUnit
->GenQ
.ObjectPlane
);
908 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
909 set_texgen_matrix( rmesa
, unit
,
910 texUnit
->GenS
.EyePlane
,
911 texUnit
->GenT
.EyePlane
,
912 texUnit
->GenR
.EyePlane
,
913 texUnit
->GenQ
.EyePlane
);
916 case GL_REFLECTION_MAP_NV
:
917 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
918 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
919 /* TODO: unknown if this is needed/correct */
920 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
921 reflect
+ 8, reflect
+ 12 );
924 case GL_NORMAL_MAP_NV
:
925 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
926 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
930 /* the mode which everyone uses :-( */
932 /* Unsupported mode, fallback:
934 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
935 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
939 if (tmp
!= rmesa
->TexGenEnabled
) {
940 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
947 * Compute the cached hardware register values for the given texture object.
949 * \param rmesa Context pointer
950 * \param t the r300 texture object
952 static GLboolean
setup_hardware_state(r100ContextPtr rmesa
, radeonTexObj
*t
, int unit
)
954 const struct gl_texture_image
*firstImage
;
955 GLint log2Width
, log2Height
, texelBytes
;
961 firstImage
= t
->base
.Image
[0][t
->minLod
];
963 log2Width
= firstImage
->WidthLog2
;
964 log2Height
= firstImage
->HeightLog2
;
965 texelBytes
= _mesa_get_format_bytes(firstImage
->TexFormat
);
967 if (!t
->image_override
) {
968 if (VALID_FORMAT(firstImage
->TexFormat
)) {
969 const struct tx_table
*table
= tx_table
;
971 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
972 RADEON_TXFORMAT_ALPHA_IN_MAP
);
973 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
975 t
->pp_txformat
|= table
[ firstImage
->TexFormat
].format
;
976 t
->pp_txfilter
|= table
[ firstImage
->TexFormat
].filter
;
978 _mesa_problem(NULL
, "unexpected texture format in %s",
984 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
985 t
->pp_txfilter
|= (t
->maxLod
- t
->minLod
) << RADEON_MAX_MIP_LEVEL_SHIFT
;
987 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
988 RADEON_TXFORMAT_HEIGHT_MASK
|
989 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
990 RADEON_TXFORMAT_F5_WIDTH_MASK
|
991 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
992 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
993 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
997 if (t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
998 ASSERT(log2Width
== log2Height
);
999 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_F5_WIDTH_SHIFT
) |
1000 (log2Height
<< RADEON_TXFORMAT_F5_HEIGHT_SHIFT
) |
1001 /* don't think we need this bit, if it exists at all - fglrx does not set it */
1002 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE
));
1003 t
->pp_cubic_faces
= ((log2Width
<< RADEON_FACE_WIDTH_1_SHIFT
) |
1004 (log2Height
<< RADEON_FACE_HEIGHT_1_SHIFT
) |
1005 (log2Width
<< RADEON_FACE_WIDTH_2_SHIFT
) |
1006 (log2Height
<< RADEON_FACE_HEIGHT_2_SHIFT
) |
1007 (log2Width
<< RADEON_FACE_WIDTH_3_SHIFT
) |
1008 (log2Height
<< RADEON_FACE_HEIGHT_3_SHIFT
) |
1009 (log2Width
<< RADEON_FACE_WIDTH_4_SHIFT
) |
1010 (log2Height
<< RADEON_FACE_HEIGHT_4_SHIFT
));
1013 t
->pp_txsize
= (((firstImage
->Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
1014 | ((firstImage
->Height
- 1) << RADEON_TEX_VSIZE_SHIFT
));
1016 if ( !t
->image_override
) {
1017 if (_mesa_is_format_compressed(firstImage
->TexFormat
))
1018 t
->pp_txpitch
= (firstImage
->Width
+ 63) & ~(63);
1020 t
->pp_txpitch
= ((firstImage
->Width
* texelBytes
) + 63) & ~(63);
1021 t
->pp_txpitch
-= 32;
1024 if (t
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
1025 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
1031 static GLboolean
radeon_validate_texture(struct gl_context
*ctx
, struct gl_texture_object
*texObj
, int unit
)
1033 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1034 radeonTexObj
*t
= radeon_tex_obj(texObj
);
1037 if (!radeon_validate_texture_miptree(ctx
, _mesa_get_samplerobj(ctx
, unit
), texObj
))
1040 ret
= setup_hardware_state(rmesa
, t
, unit
);
1041 if (ret
== GL_FALSE
)
1044 /* yuv conversion only works in first unit */
1045 if (unit
!= 0 && (t
->pp_txfilter
& RADEON_YUV_TO_RGB
))
1048 RADEON_STATECHANGE( rmesa
, ctx
);
1049 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1050 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1051 RADEON_STATECHANGE( rmesa
, tcl
);
1052 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_ST_BIT(unit
);
1054 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1056 radeonTexUpdateParameters(ctx
, unit
);
1057 import_tex_obj_state( rmesa
, unit
, t
);
1059 if (rmesa
->recheck_texgen
[unit
]) {
1060 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1061 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1062 rmesa
->recheck_texgen
[unit
] = 0;
1063 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
1066 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1069 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1071 t
->validated
= GL_TRUE
;
1072 return !t
->border_fallback
;
1075 static GLboolean
radeonUpdateTextureUnit( struct gl_context
*ctx
, int unit
)
1077 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1079 if (ctx
->Texture
.Unit
[unit
]._Current
&&
1080 ctx
->Texture
.Unit
[unit
]._Current
->Target
== GL_TEXTURE_3D
) {
1081 disable_tex_obj_state(rmesa
, unit
);
1082 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1086 if (!ctx
->Texture
.Unit
[unit
]._Current
) {
1087 /* disable the unit */
1088 disable_tex_obj_state(rmesa
, unit
);
1089 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1093 if (!radeon_validate_texture(ctx
, ctx
->Texture
.Unit
[unit
]._Current
, unit
)) {
1095 "failed to validate texture for unit %d.\n",
1097 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1100 rmesa
->state
.texture
.unit
[unit
].texobj
= radeon_tex_obj(ctx
->Texture
.Unit
[unit
]._Current
);
1104 void radeonUpdateTextureState( struct gl_context
*ctx
)
1106 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1109 /* set the ctx all textures off */
1110 RADEON_STATECHANGE( rmesa
, ctx
);
1111 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~((RADEON_TEX_ENABLE_MASK
) | (RADEON_TEX_BLEND_ENABLE_MASK
));
1113 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1114 radeonUpdateTextureUnit( ctx
, 1 ) &&
1115 radeonUpdateTextureUnit( ctx
, 2 ));
1117 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1119 if (rmesa
->radeon
.TclFallback
)
1120 radeonChooseVertexState( ctx
);