1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_texstate.c,v 1.6 2002/12/16 16:18:59 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 VA Linux Systems Inc., Fremont, California.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Kevin E. Martin <martin@valinux.com>
34 * Gareth Hughes <gareth@valinux.com>
42 #include "texformat.h"
45 #include "radeon_context.h"
46 #include "radeon_state.h"
47 #include "radeon_ioctl.h"
48 #include "radeon_swtcl.h"
49 #include "radeon_tex.h"
50 #include "radeon_tcl.h"
53 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
54 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
55 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
56 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
57 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
58 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
59 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
60 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
61 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
64 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
65 #define _COLOR_REV(f) \
66 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
68 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
69 #define _ALPHA_REV(f) \
70 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
72 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
74 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
75 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
76 && (tx_table[f].format != 0xffffffff) )
79 GLuint format
, filter
;
115 * This function computes the number of bytes of storage needed for
116 * the given texture object (all mipmap levels, all cube faces).
117 * The \c image[face][level].x/y/width/height parameters for upload/blitting
118 * are computed here. \c pp_txfilter, \c pp_txformat, etc. will be set here
121 * \param rmesa Context pointer
122 * \param tObj GL texture object whose images are to be posted to
125 static void radeonSetTexImages( radeonContextPtr rmesa
,
126 struct gl_texture_object
*tObj
)
128 radeonTexObjPtr t
= (radeonTexObjPtr
)tObj
->DriverData
;
129 const struct gl_texture_image
*baseImage
= tObj
->Image
[0][tObj
->BaseLevel
];
130 GLint curOffset
, blitWidth
;
133 GLint log2Width
, log2Height
, log2Depth
;
135 /* Set the hardware texture format
138 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
139 RADEON_TXFORMAT_ALPHA_IN_MAP
);
140 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
142 if ( VALID_FORMAT( baseImage
->TexFormat
->MesaFormat
) ) {
143 t
->pp_txformat
|= tx_table
[ baseImage
->TexFormat
->MesaFormat
].format
;
144 t
->pp_txfilter
|= tx_table
[ baseImage
->TexFormat
->MesaFormat
].filter
;
147 _mesa_problem(NULL
, "unexpected texture format in %s", __FUNCTION__
);
151 texelBytes
= baseImage
->TexFormat
->TexelBytes
;
153 /* Compute which mipmap levels we really want to send to the hardware.
156 driCalculateTextureFirstLastLevel( (driTextureObject
*) t
);
157 log2Width
= tObj
->Image
[0][t
->base
.firstLevel
]->WidthLog2
;
158 log2Height
= tObj
->Image
[0][t
->base
.firstLevel
]->HeightLog2
;
159 log2Depth
= tObj
->Image
[0][t
->base
.firstLevel
]->DepthLog2
;
161 numLevels
= t
->base
.lastLevel
- t
->base
.firstLevel
+ 1;
163 assert(numLevels
<= RADEON_MAX_TEXTURE_LEVELS
);
165 /* Calculate mipmap offsets and dimensions for blitting (uploading)
166 * The idea is that we lay out the mipmap levels within a block of
167 * memory organized as a rectangle of width BLIT_WIDTH_BYTES.
170 blitWidth
= BLIT_WIDTH_BYTES
;
173 /* figure out if this texture is suitable for tiling. */
174 if (texelBytes
&& (tObj
->Target
!= GL_TEXTURE_RECTANGLE_NV
)) {
175 if (rmesa
->texmicrotile
&& (baseImage
->Height
> 1)) {
176 /* allow 32 (bytes) x 1 mip (which will use two times the space
177 the non-tiled version would use) max if base texture is large enough */
178 if ((numLevels
== 1) ||
179 (((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 32) &&
180 (baseImage
->Width
* texelBytes
> 64)) ||
181 ((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 16)) {
182 /* R100 has two microtile bits (only the txoffset reg, not the blitter)
183 weird: X2 + OPT: 32bit correct, 16bit completely hosed
184 X2: 32bit correct, 16bit correct
185 OPT: 32bit large mips correct, small mips hosed, 16bit completely hosed */
186 t
->tile_bits
|= RADEON_TXO_MICRO_TILE_X2
/*| RADEON_TXO_MICRO_TILE_OPT*/;
189 if ((baseImage
->Width
* texelBytes
>= 256) && (baseImage
->Height
>= 16)) {
190 /* R100 disables macro tiling only if mip width is smaller than 256 bytes, and not
191 in the case if height is smaller than 16 (not 100% sure), as does the r200,
192 so need to disable macro tiling in that case */
193 if ((numLevels
== 1) || ((baseImage
->Width
* texelBytes
/ baseImage
->Height
) <= 4)) {
194 t
->tile_bits
|= RADEON_TXO_MACRO_TILE
;
199 for (i
= 0; i
< numLevels
; i
++) {
200 const struct gl_texture_image
*texImage
;
203 texImage
= tObj
->Image
[0][i
+ t
->base
.firstLevel
];
207 /* find image size in bytes */
208 if (texImage
->IsCompressed
) {
209 /* need to calculate the size AFTER padding even though the texture is
210 submitted without padding.
211 Only handle pot textures currently - don't know if npot is even possible,
212 size calculation would certainly need (trivial) adjustments.
213 Align (and later pad) to 32byte, not sure what that 64byte blit width is
215 if ((t
->pp_txformat
& RADEON_TXFORMAT_FORMAT_MASK
) == RADEON_TXFORMAT_DXT1
) {
216 /* RGB_DXT1/RGBA_DXT1, 8 bytes per block */
217 if ((texImage
->Width
+ 3) < 8) /* width one block */
218 size
= texImage
->CompressedSize
* 4;
219 else if ((texImage
->Width
+ 3) < 16)
220 size
= texImage
->CompressedSize
* 2;
221 else size
= texImage
->CompressedSize
;
223 else /* DXT3/5, 16 bytes per block */
224 if ((texImage
->Width
+ 3) < 8)
225 size
= texImage
->CompressedSize
* 2;
226 else size
= texImage
->CompressedSize
;
228 else if (tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
229 size
= ((texImage
->Width
* texelBytes
+ 63) & ~63) * texImage
->Height
;
231 else if (t
->tile_bits
& RADEON_TXO_MICRO_TILE_X2
) {
232 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
233 though the actual offset may be different (if texture is less than
234 32 bytes width) to the untiled case */
235 int w
= (texImage
->Width
* texelBytes
* 2 + 31) & ~31;
236 size
= (w
* ((texImage
->Height
+ 1) / 2)) * texImage
->Depth
;
237 blitWidth
= MAX2(texImage
->Width
, 64 / texelBytes
);
240 int w
= (texImage
->Width
* texelBytes
+ 31) & ~31;
241 size
= w
* texImage
->Height
* texImage
->Depth
;
242 blitWidth
= MAX2(texImage
->Width
, 64 / texelBytes
);
246 /* Align to 32-byte offset. It is faster to do this unconditionally
247 * (no branch penalty).
250 curOffset
= (curOffset
+ 0x1f) & ~0x1f;
253 t
->image
[0][i
].x
= curOffset
; /* fix x and y coords up later together with offset */
254 t
->image
[0][i
].y
= 0;
255 t
->image
[0][i
].width
= MIN2(size
/ texelBytes
, blitWidth
);
256 t
->image
[0][i
].height
= (size
/ texelBytes
) / t
->image
[0][i
].width
;
259 t
->image
[0][i
].x
= curOffset
% BLIT_WIDTH_BYTES
;
260 t
->image
[0][i
].y
= curOffset
/ BLIT_WIDTH_BYTES
;
261 t
->image
[0][i
].width
= MIN2(size
, BLIT_WIDTH_BYTES
);
262 t
->image
[0][i
].height
= size
/ t
->image
[0][i
].width
;
266 /* for debugging only and only applicable to non-rectangle targets */
267 assert(size
% t
->image
[0][i
].width
== 0);
268 assert(t
->image
[0][i
].x
== 0
269 || (size
< BLIT_WIDTH_BYTES
&& t
->image
[0][i
].height
== 1));
274 "level %d: %dx%d x=%d y=%d w=%d h=%d size=%d at %d\n",
275 i
, texImage
->Width
, texImage
->Height
,
276 t
->image
[0][i
].x
, t
->image
[0][i
].y
,
277 t
->image
[0][i
].width
, t
->image
[0][i
].height
, size
, curOffset
);
283 /* Align the total size of texture memory block.
285 t
->base
.totalSize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
289 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
290 t
->pp_txfilter
|= (numLevels
- 1) << RADEON_MAX_MIP_LEVEL_SHIFT
;
292 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
293 RADEON_TXFORMAT_HEIGHT_MASK
|
294 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
);
295 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
296 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
298 t
->pp_txsize
= (((tObj
->Image
[0][t
->base
.firstLevel
]->Width
- 1) << 0) |
299 ((tObj
->Image
[0][t
->base
.firstLevel
]->Height
- 1) << 16));
301 /* Only need to round to nearest 32 for textures, but the blitter
302 * requires 64-byte aligned pitches, and we may/may not need the
303 * blitter. NPOT only!
305 if (baseImage
->IsCompressed
)
306 t
->pp_txpitch
= (tObj
->Image
[0][t
->base
.firstLevel
]->Width
+ 63) & ~(63);
308 t
->pp_txpitch
= ((tObj
->Image
[0][t
->base
.firstLevel
]->Width
* texelBytes
) + 63) & ~(63);
311 t
->dirty_state
= TEX_ALL
;
313 /* FYI: radeonUploadTexImages( rmesa, t ); used to be called here */
318 /* ================================================================
319 * Texture combine functions
322 /* GL_ARB_texture_env_combine support
325 /* The color tables have combine functions for GL_SRC_COLOR,
326 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
328 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
331 RADEON_COLOR_ARG_A_T0_COLOR
,
332 RADEON_COLOR_ARG_A_T1_COLOR
,
333 RADEON_COLOR_ARG_A_T2_COLOR
336 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
337 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
338 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
341 RADEON_COLOR_ARG_A_T0_ALPHA
,
342 RADEON_COLOR_ARG_A_T1_ALPHA
,
343 RADEON_COLOR_ARG_A_T2_ALPHA
346 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
347 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
348 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
352 static GLuint radeon_tfactor_color
[] =
354 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
355 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
356 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
357 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
360 static GLuint radeon_primary_color
[] =
362 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
363 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
364 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
365 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
368 static GLuint radeon_previous_color
[] =
370 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
371 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
372 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
373 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
376 /* GL_ZERO table - indices 0-3
377 * GL_ONE table - indices 1-4
379 static GLuint radeon_zero_color
[] =
381 RADEON_COLOR_ARG_A_ZERO
,
382 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
383 RADEON_COLOR_ARG_A_ZERO
,
384 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
385 RADEON_COLOR_ARG_A_ZERO
389 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
391 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
394 RADEON_ALPHA_ARG_A_T0_ALPHA
,
395 RADEON_ALPHA_ARG_A_T1_ALPHA
,
396 RADEON_ALPHA_ARG_A_T2_ALPHA
399 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
400 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
401 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
405 static GLuint radeon_tfactor_alpha
[] =
407 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
408 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
411 static GLuint radeon_primary_alpha
[] =
413 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
414 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
417 static GLuint radeon_previous_alpha
[] =
419 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
420 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
423 /* GL_ZERO table - indices 0-1
424 * GL_ONE table - indices 1-2
426 static GLuint radeon_zero_alpha
[] =
428 RADEON_ALPHA_ARG_A_ZERO
,
429 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
430 RADEON_ALPHA_ARG_A_ZERO
434 /* Extract the arg from slot A, shift it into the correct argument slot
435 * and set the corresponding complement bit.
437 #define RADEON_COLOR_ARG( n, arg ) \
440 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
441 << RADEON_COLOR_ARG_##arg##_SHIFT); \
443 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
444 << RADEON_COMP_ARG_##arg##_SHIFT); \
447 #define RADEON_ALPHA_ARG( n, arg ) \
450 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
451 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
453 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
454 << RADEON_COMP_ARG_##arg##_SHIFT); \
458 /* ================================================================
459 * Texture unit state management
462 static GLboolean
radeonUpdateTextureEnv( GLcontext
*ctx
, int unit
)
464 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
465 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
466 GLuint color_combine
, alpha_combine
;
467 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
468 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
469 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
470 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
471 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
472 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
475 /* texUnit->_Current can be NULL if and only if the texture unit is
476 * not actually enabled.
478 assert( (texUnit
->_ReallyEnabled
== 0)
479 || (texUnit
->_Current
!= NULL
) );
481 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
482 fprintf( stderr
, "%s( %p, %d )\n", __FUNCTION__
, (void *)ctx
, unit
);
485 /* Set the texture environment state. Isn't this nice and clean?
486 * The chip will automagically set the texture alpha to 0xff when
487 * the texture format does not include an alpha component. This
488 * reduces the amount of special-casing we have to do, alpha-only
489 * textures being a notable exception.
491 /* Don't cache these results.
493 rmesa
->state
.texture
.unit
[unit
].format
= 0;
494 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
496 if ( !texUnit
->_ReallyEnabled
) {
497 color_combine
= color_combine0
;
498 alpha_combine
= alpha_combine0
;
501 GLuint color_arg
[3], alpha_arg
[3];
503 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
504 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
505 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
506 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
510 * Extract the color and alpha combine function arguments.
512 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
513 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
514 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
519 color_arg
[i
] = radeon_texture_color
[op
][unit
];
522 color_arg
[i
] = radeon_tfactor_color
[op
];
524 case GL_PRIMARY_COLOR
:
525 color_arg
[i
] = radeon_primary_color
[op
];
528 color_arg
[i
] = radeon_previous_color
[op
];
531 color_arg
[i
] = radeon_zero_color
[op
];
534 color_arg
[i
] = radeon_zero_color
[op
+1];
539 /* implement ogl 1.4/1.5 core spec here, not specification of
540 * GL_ARB_texture_env_crossbar (which would require disabling blending
541 * instead of undefined results when referencing not enabled texunit) */
542 color_arg
[i
] = radeon_texture_color
[op
][srcRGBi
- GL_TEXTURE0
];
549 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
550 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
551 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
556 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
559 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
561 case GL_PRIMARY_COLOR
:
562 alpha_arg
[i
] = radeon_primary_alpha
[op
];
565 alpha_arg
[i
] = radeon_previous_alpha
[op
];
568 alpha_arg
[i
] = radeon_zero_alpha
[op
];
571 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
576 alpha_arg
[i
] = radeon_texture_alpha
[op
][srcAi
- GL_TEXTURE0
];
584 * Build up the color and alpha combine functions.
586 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
588 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
589 RADEON_COLOR_ARG_B_ZERO
|
590 RADEON_BLEND_CTL_ADD
|
592 RADEON_COLOR_ARG( 0, C
);
595 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
596 RADEON_BLEND_CTL_ADD
|
598 RADEON_COLOR_ARG( 0, A
);
599 RADEON_COLOR_ARG( 1, B
);
602 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
604 RADEON_BLEND_CTL_ADD
|
606 RADEON_COLOR_ARG( 0, A
);
607 RADEON_COLOR_ARG( 1, C
);
610 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
612 RADEON_BLEND_CTL_ADDSIGNED
|
614 RADEON_COLOR_ARG( 0, A
);
615 RADEON_COLOR_ARG( 1, C
);
618 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
620 RADEON_BLEND_CTL_SUBTRACT
|
622 RADEON_COLOR_ARG( 0, A
);
623 RADEON_COLOR_ARG( 1, C
);
626 color_combine
= (RADEON_BLEND_CTL_BLEND
|
628 RADEON_COLOR_ARG( 0, B
);
629 RADEON_COLOR_ARG( 1, A
);
630 RADEON_COLOR_ARG( 2, C
);
633 case GL_DOT3_RGB_EXT
:
634 case GL_DOT3_RGBA_EXT
:
635 /* The EXT version of the DOT3 extension does not support the
636 * scale factor, but the ARB version (and the version in OpenGL
644 /* The R100 / RV200 only support a 1X multiplier in hardware
647 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
652 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
653 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
654 /* is it necessary to set this or will it be ignored anyway? */
658 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
659 RADEON_BLEND_CTL_DOT3
|
661 RADEON_COLOR_ARG( 0, A
);
662 RADEON_COLOR_ARG( 1, B
);
665 case GL_MODULATE_ADD_ATI
:
666 color_combine
= (RADEON_BLEND_CTL_ADD
|
668 RADEON_COLOR_ARG( 0, A
);
669 RADEON_COLOR_ARG( 1, C
);
670 RADEON_COLOR_ARG( 2, B
);
672 case GL_MODULATE_SIGNED_ADD_ATI
:
673 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
675 RADEON_COLOR_ARG( 0, A
);
676 RADEON_COLOR_ARG( 1, C
);
677 RADEON_COLOR_ARG( 2, B
);
679 case GL_MODULATE_SUBTRACT_ATI
:
680 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
682 RADEON_COLOR_ARG( 0, A
);
683 RADEON_COLOR_ARG( 1, C
);
684 RADEON_COLOR_ARG( 2, B
);
690 switch ( texUnit
->_CurrentCombine
->ModeA
) {
692 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
693 RADEON_ALPHA_ARG_B_ZERO
|
694 RADEON_BLEND_CTL_ADD
|
696 RADEON_ALPHA_ARG( 0, C
);
699 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
700 RADEON_BLEND_CTL_ADD
|
702 RADEON_ALPHA_ARG( 0, A
);
703 RADEON_ALPHA_ARG( 1, B
);
706 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
708 RADEON_BLEND_CTL_ADD
|
710 RADEON_ALPHA_ARG( 0, A
);
711 RADEON_ALPHA_ARG( 1, C
);
714 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
716 RADEON_BLEND_CTL_ADDSIGNED
|
718 RADEON_ALPHA_ARG( 0, A
);
719 RADEON_ALPHA_ARG( 1, C
);
722 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
724 RADEON_BLEND_CTL_SUBTRACT
|
726 RADEON_ALPHA_ARG( 0, A
);
727 RADEON_ALPHA_ARG( 1, C
);
730 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
732 RADEON_ALPHA_ARG( 0, B
);
733 RADEON_ALPHA_ARG( 1, A
);
734 RADEON_ALPHA_ARG( 2, C
);
737 case GL_MODULATE_ADD_ATI
:
738 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
740 RADEON_ALPHA_ARG( 0, A
);
741 RADEON_ALPHA_ARG( 1, C
);
742 RADEON_ALPHA_ARG( 2, B
);
744 case GL_MODULATE_SIGNED_ADD_ATI
:
745 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
747 RADEON_ALPHA_ARG( 0, A
);
748 RADEON_ALPHA_ARG( 1, C
);
749 RADEON_ALPHA_ARG( 2, B
);
751 case GL_MODULATE_SUBTRACT_ATI
:
752 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
754 RADEON_ALPHA_ARG( 0, A
);
755 RADEON_ALPHA_ARG( 1, C
);
756 RADEON_ALPHA_ARG( 2, B
);
762 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
763 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
764 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
768 * Apply the scale factor.
770 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
771 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
777 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
778 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
779 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
780 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
781 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
787 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
788 RADEON_MIN_FILTER_MASK | \
789 RADEON_MAG_FILTER_MASK | \
790 RADEON_MAX_ANISO_MASK | \
791 RADEON_YUV_TO_RGB | \
792 RADEON_YUV_TEMPERATURE_MASK | \
793 RADEON_CLAMP_S_MASK | \
794 RADEON_CLAMP_T_MASK | \
795 RADEON_BORDER_MODE_D3D )
797 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
798 RADEON_TXFORMAT_HEIGHT_MASK | \
799 RADEON_TXFORMAT_FORMAT_MASK | \
800 RADEON_TXFORMAT_F5_WIDTH_MASK | \
801 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
802 RADEON_TXFORMAT_ALPHA_IN_MAP | \
803 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
804 RADEON_TXFORMAT_NON_POWER2)
807 static void import_tex_obj_state( radeonContextPtr rmesa
,
809 radeonTexObjPtr texobj
)
811 GLuint
*cmd
= RADEON_DB_STATE( tex
[unit
] );
813 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
814 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
815 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
816 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
817 cmd
[TEX_PP_TXOFFSET
] = texobj
->pp_txoffset
;
818 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
819 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.tex
[unit
] );
821 if (texobj
->base
.tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
) {
822 GLuint
*txr_cmd
= RADEON_DB_STATE( txr
[unit
] );
823 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
824 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
825 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.txr
[unit
] );
828 texobj
->dirty_state
&= ~(1<<unit
);
834 static void set_texgen_matrix( radeonContextPtr rmesa
,
836 const GLfloat
*s_plane
,
837 const GLfloat
*t_plane
,
838 const GLfloat
*r_plane
,
839 const GLfloat
*q_plane
)
841 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
842 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
843 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
844 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
846 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
847 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
848 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
849 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
851 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
852 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
853 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
854 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
856 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
857 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
858 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
859 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
861 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
862 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
865 /* Returns GL_FALSE if fallback required.
867 static GLboolean
radeon_validate_texgen( GLcontext
*ctx
, GLuint unit
)
869 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
870 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
871 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
872 GLuint tmp
= rmesa
->TexGenEnabled
;
873 static const GLfloat reflect
[16] = {
879 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
880 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
881 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
882 rmesa
->TexGenNeedNormals
[unit
] = 0;
884 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
885 /* Disabled, no fallback:
887 rmesa
->TexGenEnabled
|=
888 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
891 /* the r100 cannot do texgen for some coords and not for others
892 * we do not detect such cases (certainly can't do it here) and just
893 * ASSUME that when S and T are texgen enabled we do not need other
894 * non-texgen enabled coords, no matter if the R and Q bits are texgen
895 * enabled. Still check for mixed mode texgen for all coords.
897 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
898 (texUnit
->TexGenEnabled
& T_BIT
) &&
899 (texUnit
->GenModeS
== texUnit
->GenModeT
) ) {
900 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
901 (texUnit
->GenModeS
!= texUnit
->GenModeR
)) ||
902 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
903 (texUnit
->GenModeS
!= texUnit
->GenModeQ
)) ) {
904 /* Mixed modes, fallback:
906 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
907 fprintf(stderr
, "fallback mixed texgen\n");
910 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
913 /* some texgen mode not including both S and T bits */
914 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
915 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
919 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
920 /* need this here for vtxfmt presumably. Argh we need to set
921 this from way too many places, would be much easier if we could leave
922 tcl q coord always enabled as on r200) */
923 RADEON_STATECHANGE( rmesa
, tcl
);
925 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_Q0
;
927 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_Q1
;
930 switch (texUnit
->GenModeS
) {
931 case GL_OBJECT_LINEAR
:
932 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
933 set_texgen_matrix( rmesa
, unit
,
934 texUnit
->ObjectPlaneS
,
935 texUnit
->ObjectPlaneT
,
936 texUnit
->ObjectPlaneR
,
937 texUnit
->ObjectPlaneQ
);
941 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
942 set_texgen_matrix( rmesa
, unit
,
949 case GL_REFLECTION_MAP_NV
:
950 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
951 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
952 /* TODO: unknown if this is needed/correct */
953 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
954 reflect
+ 8, reflect
+ 12 );
957 case GL_NORMAL_MAP_NV
:
958 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
959 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
963 /* the mode which everyone uses :-( */
965 /* Unsupported mode, fallback:
967 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
968 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
972 if (tmp
!= rmesa
->TexGenEnabled
) {
973 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
980 static void disable_tex( GLcontext
*ctx
, int unit
)
982 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
984 if (rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & (RADEON_TEX_0_ENABLE
<<unit
)) {
985 /* Texture unit disabled */
986 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= NULL
) {
987 /* The old texture is no longer bound to this texture unit.
991 rmesa
->state
.texture
.unit
[unit
].texobj
->base
.bound
&= ~(1UL << unit
);
992 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
995 RADEON_STATECHANGE( rmesa
, ctx
);
996 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &=
997 ~((RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
);
999 RADEON_STATECHANGE( rmesa
, tcl
);
1002 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_TCL_VTX_ST0
|
1006 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_TCL_VTX_ST1
|
1014 if (rmesa
->TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
1015 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
1016 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1022 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
1023 GLuint tmp
= rmesa
->TexGenEnabled
;
1025 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
1026 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
1027 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
1028 rmesa
->TexGenNeedNormals
[unit
] = 0;
1029 rmesa
->TexGenEnabled
|=
1030 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
1032 if (tmp
!= rmesa
->TexGenEnabled
) {
1033 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1034 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1040 static GLboolean
enable_tex_2d( GLcontext
*ctx
, int unit
)
1042 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1043 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1044 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1045 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1047 /* Need to load the 2d images associated with this unit.
1049 if (t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
1050 t
->pp_txformat
&= ~RADEON_TXFORMAT_NON_POWER2
;
1051 t
->base
.dirty_images
[0] = ~0;
1054 ASSERT(tObj
->Target
== GL_TEXTURE_2D
|| tObj
->Target
== GL_TEXTURE_1D
);
1056 if ( t
->base
.dirty_images
[0] ) {
1057 RADEON_FIREVERTICES( rmesa
);
1058 radeonSetTexImages( rmesa
, tObj
);
1059 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, 0 );
1060 if ( !t
->base
.memBlock
)
1067 static GLboolean
enable_tex_rect( GLcontext
*ctx
, int unit
)
1069 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1070 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1071 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1072 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1074 if (!(t
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
)) {
1075 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
1076 t
->base
.dirty_images
[0] = ~0;
1079 ASSERT(tObj
->Target
== GL_TEXTURE_RECTANGLE_NV
);
1081 if ( t
->base
.dirty_images
[0] ) {
1082 RADEON_FIREVERTICES( rmesa
);
1083 radeonSetTexImages( rmesa
, tObj
);
1084 radeonUploadTexImages( rmesa
, (radeonTexObjPtr
) tObj
->DriverData
, 0 );
1085 if ( !t
->base
.memBlock
/* && !rmesa->prefer_gart_client_texturing FIXME */ ) {
1086 fprintf(stderr
, "%s: upload failed\n", __FUNCTION__
);
1095 static GLboolean
update_tex_common( GLcontext
*ctx
, int unit
)
1097 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1098 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1099 struct gl_texture_object
*tObj
= texUnit
->_Current
;
1100 radeonTexObjPtr t
= (radeonTexObjPtr
) tObj
->DriverData
;
1103 /* Fallback if there's a texture border */
1104 if ( tObj
->Image
[0][tObj
->BaseLevel
]->Border
> 0 ) {
1105 fprintf(stderr
, "%s: border\n", __FUNCTION__
);
1109 /* Update state if this is a different texture object to last
1112 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= t
) {
1113 if ( rmesa
->state
.texture
.unit
[unit
].texobj
!= NULL
) {
1114 /* The old texture is no longer bound to this texture unit.
1118 rmesa
->state
.texture
.unit
[unit
].texobj
->base
.bound
&=
1122 rmesa
->state
.texture
.unit
[unit
].texobj
= t
;
1123 t
->base
.bound
|= (1UL << unit
);
1124 t
->dirty_state
|= 1<<unit
;
1125 driUpdateTextureLRU( (driTextureObject
*) t
); /* XXX: should be locked! */
1131 if ( !(rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] & (RADEON_TEX_0_ENABLE
<<unit
))) {
1132 RADEON_STATECHANGE( rmesa
, ctx
);
1133 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1134 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1136 RADEON_STATECHANGE( rmesa
, tcl
);
1139 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_ST0
;
1141 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_TCL_VTX_ST1
;
1143 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1146 if (t
->dirty_state
& (1<<unit
)) {
1147 import_tex_obj_state( rmesa
, unit
, t
);
1148 /* may need to update texture matrix (for texrect adjustments) */
1149 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1152 if (rmesa
->recheck_texgen
[unit
]) {
1153 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1154 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1155 rmesa
->recheck_texgen
[unit
] = 0;
1156 rmesa
->NewGLState
|= _NEW_TEXTURE_MATRIX
;
1159 format
= tObj
->Image
[0][tObj
->BaseLevel
]->_BaseFormat
;
1160 if ( rmesa
->state
.texture
.unit
[unit
].format
!= format
||
1161 rmesa
->state
.texture
.unit
[unit
].envMode
!= texUnit
->EnvMode
) {
1162 rmesa
->state
.texture
.unit
[unit
].format
= format
;
1163 rmesa
->state
.texture
.unit
[unit
].envMode
= texUnit
->EnvMode
;
1164 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1169 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1170 return !t
->border_fallback
;
1175 static GLboolean
radeonUpdateTextureUnit( GLcontext
*ctx
, int unit
)
1177 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1179 if ( texUnit
->_ReallyEnabled
& (TEXTURE_RECT_BIT
) ) {
1180 return (enable_tex_rect( ctx
, unit
) &&
1181 update_tex_common( ctx
, unit
));
1183 else if ( texUnit
->_ReallyEnabled
& (TEXTURE_1D_BIT
| TEXTURE_2D_BIT
) ) {
1184 return (enable_tex_2d( ctx
, unit
) &&
1185 update_tex_common( ctx
, unit
));
1187 else if ( texUnit
->_ReallyEnabled
) {
1191 disable_tex( ctx
, unit
);
1196 void radeonUpdateTextureState( GLcontext
*ctx
)
1198 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
1201 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1202 radeonUpdateTextureUnit( ctx
, 1 ));
1204 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1206 if (rmesa
->TclFallback
)
1207 radeonChooseVertexState( ctx
);