mesa: separate legacy stuff from gl_texture_unit into gl_fixedfunc_texture_unit
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_texstate.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5
6 All Rights Reserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
34 */
35
36 #include "main/glheader.h"
37 #include "main/imports.h"
38 #include "main/context.h"
39 #include "main/macros.h"
40 #include "main/teximage.h"
41 #include "main/texstate.h"
42 #include "main/texobj.h"
43 #include "main/enums.h"
44 #include "main/samplerobj.h"
45
46 #include "radeon_context.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_state.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_tex.h"
52 #include "radeon_tcl.h"
53
54
55 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
56 && (tx_table[f].format != 0xffffffff) )
57
58 /* ================================================================
59 * Texture combine functions
60 */
61
62 /* GL_ARB_texture_env_combine support
63 */
64
65 /* The color tables have combine functions for GL_SRC_COLOR,
66 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
67 */
68 static GLuint radeon_texture_color[][RADEON_MAX_TEXTURE_UNITS] =
69 {
70 {
71 RADEON_COLOR_ARG_A_T0_COLOR,
72 RADEON_COLOR_ARG_A_T1_COLOR,
73 RADEON_COLOR_ARG_A_T2_COLOR
74 },
75 {
76 RADEON_COLOR_ARG_A_T0_COLOR | RADEON_COMP_ARG_A,
77 RADEON_COLOR_ARG_A_T1_COLOR | RADEON_COMP_ARG_A,
78 RADEON_COLOR_ARG_A_T2_COLOR | RADEON_COMP_ARG_A
79 },
80 {
81 RADEON_COLOR_ARG_A_T0_ALPHA,
82 RADEON_COLOR_ARG_A_T1_ALPHA,
83 RADEON_COLOR_ARG_A_T2_ALPHA
84 },
85 {
86 RADEON_COLOR_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
87 RADEON_COLOR_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
88 RADEON_COLOR_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
89 },
90 };
91
92 static GLuint radeon_tfactor_color[] =
93 {
94 RADEON_COLOR_ARG_A_TFACTOR_COLOR,
95 RADEON_COLOR_ARG_A_TFACTOR_COLOR | RADEON_COMP_ARG_A,
96 RADEON_COLOR_ARG_A_TFACTOR_ALPHA,
97 RADEON_COLOR_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
98 };
99
100 static GLuint radeon_primary_color[] =
101 {
102 RADEON_COLOR_ARG_A_DIFFUSE_COLOR,
103 RADEON_COLOR_ARG_A_DIFFUSE_COLOR | RADEON_COMP_ARG_A,
104 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA,
105 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
106 };
107
108 static GLuint radeon_previous_color[] =
109 {
110 RADEON_COLOR_ARG_A_CURRENT_COLOR,
111 RADEON_COLOR_ARG_A_CURRENT_COLOR | RADEON_COMP_ARG_A,
112 RADEON_COLOR_ARG_A_CURRENT_ALPHA,
113 RADEON_COLOR_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
114 };
115
116 /* GL_ZERO table - indices 0-3
117 * GL_ONE table - indices 1-4
118 */
119 static GLuint radeon_zero_color[] =
120 {
121 RADEON_COLOR_ARG_A_ZERO,
122 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
123 RADEON_COLOR_ARG_A_ZERO,
124 RADEON_COLOR_ARG_A_ZERO | RADEON_COMP_ARG_A,
125 RADEON_COLOR_ARG_A_ZERO
126 };
127
128
129 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
130 */
131 static GLuint radeon_texture_alpha[][RADEON_MAX_TEXTURE_UNITS] =
132 {
133 {
134 RADEON_ALPHA_ARG_A_T0_ALPHA,
135 RADEON_ALPHA_ARG_A_T1_ALPHA,
136 RADEON_ALPHA_ARG_A_T2_ALPHA
137 },
138 {
139 RADEON_ALPHA_ARG_A_T0_ALPHA | RADEON_COMP_ARG_A,
140 RADEON_ALPHA_ARG_A_T1_ALPHA | RADEON_COMP_ARG_A,
141 RADEON_ALPHA_ARG_A_T2_ALPHA | RADEON_COMP_ARG_A
142 },
143 };
144
145 static GLuint radeon_tfactor_alpha[] =
146 {
147 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA,
148 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA | RADEON_COMP_ARG_A
149 };
150
151 static GLuint radeon_primary_alpha[] =
152 {
153 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA,
154 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA | RADEON_COMP_ARG_A
155 };
156
157 static GLuint radeon_previous_alpha[] =
158 {
159 RADEON_ALPHA_ARG_A_CURRENT_ALPHA,
160 RADEON_ALPHA_ARG_A_CURRENT_ALPHA | RADEON_COMP_ARG_A
161 };
162
163 /* GL_ZERO table - indices 0-1
164 * GL_ONE table - indices 1-2
165 */
166 static GLuint radeon_zero_alpha[] =
167 {
168 RADEON_ALPHA_ARG_A_ZERO,
169 RADEON_ALPHA_ARG_A_ZERO | RADEON_COMP_ARG_A,
170 RADEON_ALPHA_ARG_A_ZERO
171 };
172
173
174 /* Extract the arg from slot A, shift it into the correct argument slot
175 * and set the corresponding complement bit.
176 */
177 #define RADEON_COLOR_ARG( n, arg ) \
178 do { \
179 color_combine |= \
180 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
181 << RADEON_COLOR_ARG_##arg##_SHIFT); \
182 color_combine |= \
183 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
184 << RADEON_COMP_ARG_##arg##_SHIFT); \
185 } while (0)
186
187 #define RADEON_ALPHA_ARG( n, arg ) \
188 do { \
189 alpha_combine |= \
190 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
191 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
192 alpha_combine |= \
193 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
194 << RADEON_COMP_ARG_##arg##_SHIFT); \
195 } while (0)
196
197
198 /* ================================================================
199 * Texture unit state management
200 */
201
202 static GLenum
203 texture_base_format(const struct gl_texture_object *t)
204 {
205 return t->Image[0][t->BaseLevel]->_BaseFormat;
206 }
207
208 static GLboolean radeonUpdateTextureEnv( struct gl_context *ctx, int unit )
209 {
210 r100ContextPtr rmesa = R100_CONTEXT(ctx);
211 const struct gl_texture_unit *rtexUnit = &ctx->Texture.Unit[unit];
212 const struct gl_fixedfunc_texture_unit *texUnit =
213 &ctx->Texture.FixedFuncUnit[unit];
214 GLuint color_combine, alpha_combine;
215 const GLuint color_combine0 = RADEON_COLOR_ARG_A_ZERO | RADEON_COLOR_ARG_B_ZERO
216 | RADEON_COLOR_ARG_C_CURRENT_COLOR | RADEON_BLEND_CTL_ADD
217 | RADEON_SCALE_1X | RADEON_CLAMP_TX;
218 const GLuint alpha_combine0 = RADEON_ALPHA_ARG_A_ZERO | RADEON_ALPHA_ARG_B_ZERO
219 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA | RADEON_BLEND_CTL_ADD
220 | RADEON_SCALE_1X | RADEON_CLAMP_TX;
221
222
223 if ( RADEON_DEBUG & RADEON_TEXTURE ) {
224 fprintf( stderr, "%s( %p, %d )\n", __func__, (void *)ctx, unit );
225 }
226
227 /* Set the texture environment state. Isn't this nice and clean?
228 * The chip will automagically set the texture alpha to 0xff when
229 * the texture format does not include an alpha component. This
230 * reduces the amount of special-casing we have to do, alpha-only
231 * textures being a notable exception. Doesn't work for luminance
232 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
233 */
234 /* Don't cache these results.
235 */
236 rmesa->state.texture.unit[unit].format = 0;
237 rmesa->state.texture.unit[unit].envMode = 0;
238
239 if ( !rtexUnit->_Current ) {
240 color_combine = color_combine0;
241 alpha_combine = alpha_combine0;
242 }
243 else {
244 GLuint color_arg[3], alpha_arg[3];
245 GLuint i;
246 const GLuint numColorArgs = texUnit->_CurrentCombine->_NumArgsRGB;
247 const GLuint numAlphaArgs = texUnit->_CurrentCombine->_NumArgsA;
248 GLuint RGBshift = texUnit->_CurrentCombine->ScaleShiftRGB;
249 GLuint Ashift = texUnit->_CurrentCombine->ScaleShiftA;
250
251
252 /* Step 1:
253 * Extract the color and alpha combine function arguments.
254 */
255 for ( i = 0 ; i < numColorArgs ; i++ ) {
256 const GLint op = texUnit->_CurrentCombine->OperandRGB[i] - GL_SRC_COLOR;
257 const GLuint srcRGBi = texUnit->_CurrentCombine->SourceRGB[i];
258 assert(op >= 0);
259 assert(op <= 3);
260 switch ( srcRGBi ) {
261 case GL_TEXTURE:
262 if (texture_base_format(rtexUnit->_Current) == GL_ALPHA)
263 color_arg[i] = radeon_zero_color[op];
264 else
265 color_arg[i] = radeon_texture_color[op][unit];
266 break;
267 case GL_CONSTANT:
268 color_arg[i] = radeon_tfactor_color[op];
269 break;
270 case GL_PRIMARY_COLOR:
271 color_arg[i] = radeon_primary_color[op];
272 break;
273 case GL_PREVIOUS:
274 color_arg[i] = radeon_previous_color[op];
275 break;
276 case GL_ZERO:
277 color_arg[i] = radeon_zero_color[op];
278 break;
279 case GL_ONE:
280 color_arg[i] = radeon_zero_color[op+1];
281 break;
282 case GL_TEXTURE0:
283 case GL_TEXTURE1:
284 case GL_TEXTURE2: {
285 GLuint txunit = srcRGBi - GL_TEXTURE0;
286 if (texture_base_format(ctx->Texture.Unit[txunit]._Current) == GL_ALPHA)
287 color_arg[i] = radeon_zero_color[op];
288 else
289 /* implement ogl 1.4/1.5 core spec here, not specification of
290 * GL_ARB_texture_env_crossbar (which would require disabling blending
291 * instead of undefined results when referencing not enabled texunit) */
292 color_arg[i] = radeon_texture_color[op][txunit];
293 }
294 break;
295 default:
296 return GL_FALSE;
297 }
298 }
299
300 for ( i = 0 ; i < numAlphaArgs ; i++ ) {
301 const GLint op = texUnit->_CurrentCombine->OperandA[i] - GL_SRC_ALPHA;
302 const GLuint srcAi = texUnit->_CurrentCombine->SourceA[i];
303 assert(op >= 0);
304 assert(op <= 1);
305 switch ( srcAi ) {
306 case GL_TEXTURE:
307 if (texture_base_format(rtexUnit->_Current) == GL_LUMINANCE)
308 alpha_arg[i] = radeon_zero_alpha[op+1];
309 else
310 alpha_arg[i] = radeon_texture_alpha[op][unit];
311 break;
312 case GL_CONSTANT:
313 alpha_arg[i] = radeon_tfactor_alpha[op];
314 break;
315 case GL_PRIMARY_COLOR:
316 alpha_arg[i] = radeon_primary_alpha[op];
317 break;
318 case GL_PREVIOUS:
319 alpha_arg[i] = radeon_previous_alpha[op];
320 break;
321 case GL_ZERO:
322 alpha_arg[i] = radeon_zero_alpha[op];
323 break;
324 case GL_ONE:
325 alpha_arg[i] = radeon_zero_alpha[op+1];
326 break;
327 case GL_TEXTURE0:
328 case GL_TEXTURE1:
329 case GL_TEXTURE2: {
330 GLuint txunit = srcAi - GL_TEXTURE0;
331 if (texture_base_format(ctx->Texture.Unit[txunit]._Current) == GL_LUMINANCE)
332 alpha_arg[i] = radeon_zero_alpha[op+1];
333 else
334 alpha_arg[i] = radeon_texture_alpha[op][txunit];
335 }
336 break;
337 default:
338 return GL_FALSE;
339 }
340 }
341
342 /* Step 2:
343 * Build up the color and alpha combine functions.
344 */
345 switch ( texUnit->_CurrentCombine->ModeRGB ) {
346 case GL_REPLACE:
347 color_combine = (RADEON_COLOR_ARG_A_ZERO |
348 RADEON_COLOR_ARG_B_ZERO |
349 RADEON_BLEND_CTL_ADD |
350 RADEON_CLAMP_TX);
351 RADEON_COLOR_ARG( 0, C );
352 break;
353 case GL_MODULATE:
354 color_combine = (RADEON_COLOR_ARG_C_ZERO |
355 RADEON_BLEND_CTL_ADD |
356 RADEON_CLAMP_TX);
357 RADEON_COLOR_ARG( 0, A );
358 RADEON_COLOR_ARG( 1, B );
359 break;
360 case GL_ADD:
361 color_combine = (RADEON_COLOR_ARG_B_ZERO |
362 RADEON_COMP_ARG_B |
363 RADEON_BLEND_CTL_ADD |
364 RADEON_CLAMP_TX);
365 RADEON_COLOR_ARG( 0, A );
366 RADEON_COLOR_ARG( 1, C );
367 break;
368 case GL_ADD_SIGNED:
369 color_combine = (RADEON_COLOR_ARG_B_ZERO |
370 RADEON_COMP_ARG_B |
371 RADEON_BLEND_CTL_ADDSIGNED |
372 RADEON_CLAMP_TX);
373 RADEON_COLOR_ARG( 0, A );
374 RADEON_COLOR_ARG( 1, C );
375 break;
376 case GL_SUBTRACT:
377 color_combine = (RADEON_COLOR_ARG_B_ZERO |
378 RADEON_COMP_ARG_B |
379 RADEON_BLEND_CTL_SUBTRACT |
380 RADEON_CLAMP_TX);
381 RADEON_COLOR_ARG( 0, A );
382 RADEON_COLOR_ARG( 1, C );
383 break;
384 case GL_INTERPOLATE:
385 color_combine = (RADEON_BLEND_CTL_BLEND |
386 RADEON_CLAMP_TX);
387 RADEON_COLOR_ARG( 0, B );
388 RADEON_COLOR_ARG( 1, A );
389 RADEON_COLOR_ARG( 2, C );
390 break;
391
392 case GL_DOT3_RGB_EXT:
393 case GL_DOT3_RGBA_EXT:
394 /* The EXT version of the DOT3 extension does not support the
395 * scale factor, but the ARB version (and the version in OpenGL
396 * 1.3) does.
397 */
398 RGBshift = 0;
399 /* FALLTHROUGH */
400
401 case GL_DOT3_RGB:
402 case GL_DOT3_RGBA:
403 /* The R100 / RV200 only support a 1X multiplier in hardware
404 * w/the ARB version.
405 */
406 if ( RGBshift != (RADEON_SCALE_1X >> RADEON_SCALE_SHIFT) ) {
407 return GL_FALSE;
408 }
409
410 RGBshift += 2;
411 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA_EXT)
412 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGBA) ) {
413 /* is it necessary to set this or will it be ignored anyway? */
414 Ashift = RGBshift;
415 }
416
417 color_combine = (RADEON_COLOR_ARG_C_ZERO |
418 RADEON_BLEND_CTL_DOT3 |
419 RADEON_CLAMP_TX);
420 RADEON_COLOR_ARG( 0, A );
421 RADEON_COLOR_ARG( 1, B );
422 break;
423
424 case GL_MODULATE_ADD_ATI:
425 color_combine = (RADEON_BLEND_CTL_ADD |
426 RADEON_CLAMP_TX);
427 RADEON_COLOR_ARG( 0, A );
428 RADEON_COLOR_ARG( 1, C );
429 RADEON_COLOR_ARG( 2, B );
430 break;
431 case GL_MODULATE_SIGNED_ADD_ATI:
432 color_combine = (RADEON_BLEND_CTL_ADDSIGNED |
433 RADEON_CLAMP_TX);
434 RADEON_COLOR_ARG( 0, A );
435 RADEON_COLOR_ARG( 1, C );
436 RADEON_COLOR_ARG( 2, B );
437 break;
438 case GL_MODULATE_SUBTRACT_ATI:
439 color_combine = (RADEON_BLEND_CTL_SUBTRACT |
440 RADEON_CLAMP_TX);
441 RADEON_COLOR_ARG( 0, A );
442 RADEON_COLOR_ARG( 1, C );
443 RADEON_COLOR_ARG( 2, B );
444 break;
445 default:
446 return GL_FALSE;
447 }
448
449 switch ( texUnit->_CurrentCombine->ModeA ) {
450 case GL_REPLACE:
451 alpha_combine = (RADEON_ALPHA_ARG_A_ZERO |
452 RADEON_ALPHA_ARG_B_ZERO |
453 RADEON_BLEND_CTL_ADD |
454 RADEON_CLAMP_TX);
455 RADEON_ALPHA_ARG( 0, C );
456 break;
457 case GL_MODULATE:
458 alpha_combine = (RADEON_ALPHA_ARG_C_ZERO |
459 RADEON_BLEND_CTL_ADD |
460 RADEON_CLAMP_TX);
461 RADEON_ALPHA_ARG( 0, A );
462 RADEON_ALPHA_ARG( 1, B );
463 break;
464 case GL_ADD:
465 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
466 RADEON_COMP_ARG_B |
467 RADEON_BLEND_CTL_ADD |
468 RADEON_CLAMP_TX);
469 RADEON_ALPHA_ARG( 0, A );
470 RADEON_ALPHA_ARG( 1, C );
471 break;
472 case GL_ADD_SIGNED:
473 alpha_combine = (RADEON_ALPHA_ARG_B_ZERO |
474 RADEON_COMP_ARG_B |
475 RADEON_BLEND_CTL_ADDSIGNED |
476 RADEON_CLAMP_TX);
477 RADEON_ALPHA_ARG( 0, A );
478 RADEON_ALPHA_ARG( 1, C );
479 break;
480 case GL_SUBTRACT:
481 alpha_combine = (RADEON_COLOR_ARG_B_ZERO |
482 RADEON_COMP_ARG_B |
483 RADEON_BLEND_CTL_SUBTRACT |
484 RADEON_CLAMP_TX);
485 RADEON_ALPHA_ARG( 0, A );
486 RADEON_ALPHA_ARG( 1, C );
487 break;
488 case GL_INTERPOLATE:
489 alpha_combine = (RADEON_BLEND_CTL_BLEND |
490 RADEON_CLAMP_TX);
491 RADEON_ALPHA_ARG( 0, B );
492 RADEON_ALPHA_ARG( 1, A );
493 RADEON_ALPHA_ARG( 2, C );
494 break;
495
496 case GL_MODULATE_ADD_ATI:
497 alpha_combine = (RADEON_BLEND_CTL_ADD |
498 RADEON_CLAMP_TX);
499 RADEON_ALPHA_ARG( 0, A );
500 RADEON_ALPHA_ARG( 1, C );
501 RADEON_ALPHA_ARG( 2, B );
502 break;
503 case GL_MODULATE_SIGNED_ADD_ATI:
504 alpha_combine = (RADEON_BLEND_CTL_ADDSIGNED |
505 RADEON_CLAMP_TX);
506 RADEON_ALPHA_ARG( 0, A );
507 RADEON_ALPHA_ARG( 1, C );
508 RADEON_ALPHA_ARG( 2, B );
509 break;
510 case GL_MODULATE_SUBTRACT_ATI:
511 alpha_combine = (RADEON_BLEND_CTL_SUBTRACT |
512 RADEON_CLAMP_TX);
513 RADEON_ALPHA_ARG( 0, A );
514 RADEON_ALPHA_ARG( 1, C );
515 RADEON_ALPHA_ARG( 2, B );
516 break;
517 default:
518 return GL_FALSE;
519 }
520
521 if ( (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB_EXT)
522 || (texUnit->_CurrentCombine->ModeRGB == GL_DOT3_RGB) ) {
523 alpha_combine |= RADEON_DOT_ALPHA_DONT_REPLICATE;
524 }
525
526 /* Step 3:
527 * Apply the scale factor.
528 */
529 color_combine |= (RGBshift << RADEON_SCALE_SHIFT);
530 alpha_combine |= (Ashift << RADEON_SCALE_SHIFT);
531
532 /* All done!
533 */
534 }
535
536 if ( rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] != color_combine ||
537 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] != alpha_combine ) {
538 RADEON_STATECHANGE( rmesa, tex[unit] );
539 rmesa->hw.tex[unit].cmd[TEX_PP_TXCBLEND] = color_combine;
540 rmesa->hw.tex[unit].cmd[TEX_PP_TXABLEND] = alpha_combine;
541 }
542
543 return GL_TRUE;
544 }
545
546 void radeonSetTexBuffer2(__DRIcontext *pDRICtx, GLint target, GLint texture_format,
547 __DRIdrawable *dPriv)
548 {
549 struct gl_texture_object *texObj;
550 struct gl_texture_image *texImage;
551 struct radeon_renderbuffer *rb;
552 radeon_texture_image *rImage;
553 radeonContextPtr radeon;
554 struct radeon_framebuffer *rfb;
555 radeonTexObjPtr t;
556 uint32_t pitch_val;
557 mesa_format texFormat;
558
559 radeon = pDRICtx->driverPrivate;
560
561 rfb = dPriv->driverPrivate;
562 texObj = _mesa_get_current_tex_object(&radeon->glCtx, target);
563 texImage = _mesa_get_tex_image(&radeon->glCtx, texObj, target, 0);
564
565 rImage = get_radeon_texture_image(texImage);
566 t = radeon_tex_obj(texObj);
567 if (t == NULL) {
568 return;
569 }
570
571 radeon_update_renderbuffers(pDRICtx, dPriv, GL_TRUE);
572 rb = rfb->color_rb[0];
573 if (rb->bo == NULL) {
574 /* Failed to BO for the buffer */
575 return;
576 }
577
578 _mesa_lock_texture(&radeon->glCtx, texObj);
579 if (t->bo) {
580 radeon_bo_unref(t->bo);
581 t->bo = NULL;
582 }
583 if (rImage->bo) {
584 radeon_bo_unref(rImage->bo);
585 rImage->bo = NULL;
586 }
587
588 radeon_miptree_unreference(&t->mt);
589 radeon_miptree_unreference(&rImage->mt);
590
591 rImage->bo = rb->bo;
592 radeon_bo_ref(rImage->bo);
593 t->bo = rb->bo;
594 radeon_bo_ref(t->bo);
595 t->tile_bits = 0;
596 t->image_override = GL_TRUE;
597 t->override_offset = 0;
598 switch (rb->cpp) {
599 case 4:
600 if (texture_format == __DRI_TEXTURE_FORMAT_RGB) {
601 t->pp_txformat = tx_table[MESA_FORMAT_BGR_UNORM8].format;
602 texFormat = MESA_FORMAT_BGR_UNORM8;
603 }
604 else {
605 t->pp_txformat = tx_table[MESA_FORMAT_B8G8R8A8_UNORM].format;
606 texFormat = MESA_FORMAT_B8G8R8A8_UNORM;
607 }
608 t->pp_txfilter |= tx_table[MESA_FORMAT_B8G8R8A8_UNORM].filter;
609 break;
610 case 3:
611 default:
612 texFormat = MESA_FORMAT_BGR_UNORM8;
613 t->pp_txformat = tx_table[MESA_FORMAT_BGR_UNORM8].format;
614 t->pp_txfilter |= tx_table[MESA_FORMAT_BGR_UNORM8].filter;
615 break;
616 case 2:
617 texFormat = MESA_FORMAT_B5G6R5_UNORM;
618 t->pp_txformat = tx_table[MESA_FORMAT_B5G6R5_UNORM].format;
619 t->pp_txfilter |= tx_table[MESA_FORMAT_B5G6R5_UNORM].filter;
620 break;
621 }
622
623 _mesa_init_teximage_fields(&radeon->glCtx, texImage,
624 rb->base.Base.Width, rb->base.Base.Height,
625 1, 0,
626 rb->cpp, texFormat);
627 rImage->base.RowStride = rb->pitch / rb->cpp;
628
629 t->pp_txpitch &= (1 << 13) -1;
630 pitch_val = rb->pitch;
631
632 t->pp_txsize = ((rb->base.Base.Width - 1) << RADEON_TEX_USIZE_SHIFT)
633 | ((rb->base.Base.Height - 1) << RADEON_TEX_VSIZE_SHIFT);
634 if (target == GL_TEXTURE_RECTANGLE_NV) {
635 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
636 t->pp_txpitch = pitch_val;
637 t->pp_txpitch -= 32;
638 } else {
639 t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK |
640 RADEON_TXFORMAT_HEIGHT_MASK |
641 RADEON_TXFORMAT_CUBIC_MAP_ENABLE |
642 RADEON_TXFORMAT_F5_WIDTH_MASK |
643 RADEON_TXFORMAT_F5_HEIGHT_MASK);
644 t->pp_txformat |= ((texImage->WidthLog2 << RADEON_TXFORMAT_WIDTH_SHIFT) |
645 (texImage->HeightLog2 << RADEON_TXFORMAT_HEIGHT_SHIFT));
646 }
647 t->validated = GL_TRUE;
648 _mesa_unlock_texture(&radeon->glCtx, texObj);
649 return;
650 }
651
652
653 void radeonSetTexBuffer(__DRIcontext *pDRICtx, GLint target, __DRIdrawable *dPriv)
654 {
655 radeonSetTexBuffer2(pDRICtx, target, __DRI_TEXTURE_FORMAT_RGBA, dPriv);
656 }
657
658
659 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
660 RADEON_MIN_FILTER_MASK | \
661 RADEON_MAG_FILTER_MASK | \
662 RADEON_MAX_ANISO_MASK | \
663 RADEON_YUV_TO_RGB | \
664 RADEON_YUV_TEMPERATURE_MASK | \
665 RADEON_CLAMP_S_MASK | \
666 RADEON_CLAMP_T_MASK | \
667 RADEON_BORDER_MODE_D3D )
668
669 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
670 RADEON_TXFORMAT_HEIGHT_MASK | \
671 RADEON_TXFORMAT_FORMAT_MASK | \
672 RADEON_TXFORMAT_F5_WIDTH_MASK | \
673 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
674 RADEON_TXFORMAT_ALPHA_IN_MAP | \
675 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
676 RADEON_TXFORMAT_NON_POWER2)
677
678
679 static void disable_tex_obj_state( r100ContextPtr rmesa,
680 int unit )
681 {
682 RADEON_STATECHANGE( rmesa, tex[unit] );
683
684 RADEON_STATECHANGE( rmesa, tcl );
685 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &= ~(RADEON_ST_BIT(unit) |
686 RADEON_Q_BIT(unit));
687
688 if (rmesa->radeon.TclFallback & (RADEON_TCL_FALLBACK_TEXGEN_0<<unit)) {
689 TCL_FALLBACK( &rmesa->radeon.glCtx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), GL_FALSE);
690 rmesa->recheck_texgen[unit] = GL_TRUE;
691 }
692
693 if (rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) {
694 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
695 cubic_map bit on unit 2 when the unit is disabled, otherwise every
696 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
697 units, better be safe than sorry though).*/
698 RADEON_STATECHANGE( rmesa, tex[unit] );
699 rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE;
700 }
701
702 {
703 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
704 GLuint tmp = rmesa->TexGenEnabled;
705
706 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE<<unit);
707 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE<<unit);
708 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK<<inputshift);
709 rmesa->TexGenNeedNormals[unit] = 0;
710 rmesa->TexGenEnabled |=
711 (RADEON_TEXGEN_INPUT_TEXCOORD_0+unit) << inputshift;
712
713 if (tmp != rmesa->TexGenEnabled) {
714 rmesa->recheck_texgen[unit] = GL_TRUE;
715 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
716 }
717 }
718 }
719
720 static void import_tex_obj_state( r100ContextPtr rmesa,
721 int unit,
722 radeonTexObjPtr texobj )
723 {
724 /* do not use RADEON_DB_STATE to avoid stale texture caches */
725 uint32_t *cmd = &rmesa->hw.tex[unit].cmd[TEX_CMD_0];
726 GLuint se_coord_fmt = rmesa->hw.set.cmd[SET_SE_COORDFMT];
727
728 RADEON_STATECHANGE( rmesa, tex[unit] );
729
730 cmd[TEX_PP_TXFILTER] &= ~TEXOBJ_TXFILTER_MASK;
731 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK;
732 cmd[TEX_PP_TXFORMAT] &= ~TEXOBJ_TXFORMAT_MASK;
733 cmd[TEX_PP_TXFORMAT] |= texobj->pp_txformat & TEXOBJ_TXFORMAT_MASK;
734 cmd[TEX_PP_BORDER_COLOR] = texobj->pp_border_color;
735
736 if (texobj->pp_txformat & RADEON_TXFORMAT_NON_POWER2) {
737 uint32_t *txr_cmd = &rmesa->hw.txr[unit].cmd[TXR_CMD_0];
738 txr_cmd[TXR_PP_TEX_SIZE] = texobj->pp_txsize; /* NPOT only! */
739 txr_cmd[TXR_PP_TEX_PITCH] = texobj->pp_txpitch; /* NPOT only! */
740 RADEON_STATECHANGE( rmesa, txr[unit] );
741 }
742
743 if (texobj->base.Target == GL_TEXTURE_RECTANGLE_NV) {
744 se_coord_fmt |= RADEON_VTX_ST0_NONPARAMETRIC << unit;
745 }
746 else {
747 se_coord_fmt &= ~(RADEON_VTX_ST0_NONPARAMETRIC << unit);
748
749 if (texobj->base.Target == GL_TEXTURE_CUBE_MAP) {
750 uint32_t *cube_cmd = &rmesa->hw.cube[unit].cmd[CUBE_CMD_0];
751
752 RADEON_STATECHANGE( rmesa, cube[unit] );
753 cube_cmd[CUBE_PP_CUBIC_FACES] = texobj->pp_cubic_faces;
754 /* state filled out in the cube_emit */
755 }
756 }
757
758 if (se_coord_fmt != rmesa->hw.set.cmd[SET_SE_COORDFMT]) {
759 RADEON_STATECHANGE( rmesa, set );
760 rmesa->hw.set.cmd[SET_SE_COORDFMT] = se_coord_fmt;
761 }
762
763 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
764 }
765
766
767 static void set_texgen_matrix( r100ContextPtr rmesa,
768 GLuint unit,
769 const GLfloat *s_plane,
770 const GLfloat *t_plane,
771 const GLfloat *r_plane,
772 const GLfloat *q_plane )
773 {
774 rmesa->TexGenMatrix[unit].m[0] = s_plane[0];
775 rmesa->TexGenMatrix[unit].m[4] = s_plane[1];
776 rmesa->TexGenMatrix[unit].m[8] = s_plane[2];
777 rmesa->TexGenMatrix[unit].m[12] = s_plane[3];
778
779 rmesa->TexGenMatrix[unit].m[1] = t_plane[0];
780 rmesa->TexGenMatrix[unit].m[5] = t_plane[1];
781 rmesa->TexGenMatrix[unit].m[9] = t_plane[2];
782 rmesa->TexGenMatrix[unit].m[13] = t_plane[3];
783
784 rmesa->TexGenMatrix[unit].m[2] = r_plane[0];
785 rmesa->TexGenMatrix[unit].m[6] = r_plane[1];
786 rmesa->TexGenMatrix[unit].m[10] = r_plane[2];
787 rmesa->TexGenMatrix[unit].m[14] = r_plane[3];
788
789 rmesa->TexGenMatrix[unit].m[3] = q_plane[0];
790 rmesa->TexGenMatrix[unit].m[7] = q_plane[1];
791 rmesa->TexGenMatrix[unit].m[11] = q_plane[2];
792 rmesa->TexGenMatrix[unit].m[15] = q_plane[3];
793
794 rmesa->TexGenEnabled |= RADEON_TEXMAT_0_ENABLE << unit;
795 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
796 }
797
798 /* Returns GL_FALSE if fallback required.
799 */
800 static GLboolean radeon_validate_texgen( struct gl_context *ctx, GLuint unit )
801 {
802 r100ContextPtr rmesa = R100_CONTEXT(ctx);
803 struct gl_fixedfunc_texture_unit *texUnit =
804 &ctx->Texture.FixedFuncUnit[unit];
805 GLuint inputshift = RADEON_TEXGEN_0_INPUT_SHIFT + unit*4;
806 GLuint tmp = rmesa->TexGenEnabled;
807 static const GLfloat reflect[16] = {
808 -1, 0, 0, 0,
809 0, -1, 0, 0,
810 0, 0, -1, 0,
811 0, 0, 0, 1 };
812
813 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE << unit);
814 rmesa->TexGenEnabled &= ~(RADEON_TEXMAT_0_ENABLE << unit);
815 rmesa->TexGenEnabled &= ~(RADEON_TEXGEN_INPUT_MASK << inputshift);
816 rmesa->TexGenNeedNormals[unit] = 0;
817
818 if ((texUnit->TexGenEnabled & (S_BIT|T_BIT|R_BIT|Q_BIT)) == 0) {
819 /* Disabled, no fallback:
820 */
821 rmesa->TexGenEnabled |=
822 (RADEON_TEXGEN_INPUT_TEXCOORD_0 + unit) << inputshift;
823 return GL_TRUE;
824 }
825 /* the r100 cannot do texgen for some coords and not for others
826 * we do not detect such cases (certainly can't do it here) and just
827 * ASSUME that when S and T are texgen enabled we do not need other
828 * non-texgen enabled coords, no matter if the R and Q bits are texgen
829 * enabled. Still check for mixed mode texgen for all coords.
830 */
831 else if ( (texUnit->TexGenEnabled & S_BIT) &&
832 (texUnit->TexGenEnabled & T_BIT) &&
833 (texUnit->GenS.Mode == texUnit->GenT.Mode) ) {
834 if ( ((texUnit->TexGenEnabled & R_BIT) &&
835 (texUnit->GenS.Mode != texUnit->GenR.Mode)) ||
836 ((texUnit->TexGenEnabled & Q_BIT) &&
837 (texUnit->GenS.Mode != texUnit->GenQ.Mode)) ) {
838 /* Mixed modes, fallback:
839 */
840 if (RADEON_DEBUG & RADEON_FALLBACKS)
841 fprintf(stderr, "fallback mixed texgen\n");
842 return GL_FALSE;
843 }
844 rmesa->TexGenEnabled |= RADEON_TEXGEN_TEXMAT_0_ENABLE << unit;
845 }
846 else {
847 /* some texgen mode not including both S and T bits */
848 if (RADEON_DEBUG & RADEON_FALLBACKS)
849 fprintf(stderr, "fallback mixed texgen/nontexgen\n");
850 return GL_FALSE;
851 }
852
853 if ((texUnit->TexGenEnabled & (R_BIT | Q_BIT)) != 0) {
854 /* need this here for vtxfmt presumably. Argh we need to set
855 this from way too many places, would be much easier if we could leave
856 tcl q coord always enabled as on r200) */
857 RADEON_STATECHANGE( rmesa, tcl );
858 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_Q_BIT(unit);
859 }
860
861 switch (texUnit->GenS.Mode) {
862 case GL_OBJECT_LINEAR:
863 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_OBJ << inputshift;
864 set_texgen_matrix( rmesa, unit,
865 texUnit->GenS.ObjectPlane,
866 texUnit->GenT.ObjectPlane,
867 texUnit->GenR.ObjectPlane,
868 texUnit->GenQ.ObjectPlane);
869 break;
870
871 case GL_EYE_LINEAR:
872 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE << inputshift;
873 set_texgen_matrix( rmesa, unit,
874 texUnit->GenS.EyePlane,
875 texUnit->GenT.EyePlane,
876 texUnit->GenR.EyePlane,
877 texUnit->GenQ.EyePlane);
878 break;
879
880 case GL_REFLECTION_MAP_NV:
881 rmesa->TexGenNeedNormals[unit] = GL_TRUE;
882 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_REFLECT << inputshift;
883 /* TODO: unknown if this is needed/correct */
884 set_texgen_matrix( rmesa, unit, reflect, reflect + 4,
885 reflect + 8, reflect + 12 );
886 break;
887
888 case GL_NORMAL_MAP_NV:
889 rmesa->TexGenNeedNormals[unit] = GL_TRUE;
890 rmesa->TexGenEnabled |= RADEON_TEXGEN_INPUT_EYE_NORMAL << inputshift;
891 break;
892
893 case GL_SPHERE_MAP:
894 /* the mode which everyone uses :-( */
895 default:
896 /* Unsupported mode, fallback:
897 */
898 if (RADEON_DEBUG & RADEON_FALLBACKS)
899 fprintf(stderr, "fallback GL_SPHERE_MAP\n");
900 return GL_FALSE;
901 }
902
903 if (tmp != rmesa->TexGenEnabled) {
904 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
905 }
906
907 return GL_TRUE;
908 }
909
910 /**
911 * Compute the cached hardware register values for the given texture object.
912 *
913 * \param rmesa Context pointer
914 * \param t the r300 texture object
915 */
916 static GLboolean setup_hardware_state(r100ContextPtr rmesa, radeonTexObj *t, int unit)
917 {
918 const struct gl_texture_image *firstImage;
919 GLint log2Width, log2Height, texelBytes;
920
921 if ( t->bo ) {
922 return GL_TRUE;
923 }
924
925 firstImage = t->base.Image[0][t->minLod];
926
927 log2Width = firstImage->WidthLog2;
928 log2Height = firstImage->HeightLog2;
929 texelBytes = _mesa_get_format_bytes(firstImage->TexFormat);
930
931 if (!t->image_override) {
932 if (VALID_FORMAT(firstImage->TexFormat)) {
933 const struct tx_table *table = tx_table;
934
935 t->pp_txformat &= ~(RADEON_TXFORMAT_FORMAT_MASK |
936 RADEON_TXFORMAT_ALPHA_IN_MAP);
937 t->pp_txfilter &= ~RADEON_YUV_TO_RGB;
938
939 t->pp_txformat |= table[ firstImage->TexFormat ].format;
940 t->pp_txfilter |= table[ firstImage->TexFormat ].filter;
941 } else {
942 _mesa_problem(NULL, "unexpected texture format in %s",
943 __func__);
944 return GL_FALSE;
945 }
946 }
947
948 t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK;
949 t->pp_txfilter |= (t->maxLod - t->minLod) << RADEON_MAX_MIP_LEVEL_SHIFT;
950
951 t->pp_txformat &= ~(RADEON_TXFORMAT_WIDTH_MASK |
952 RADEON_TXFORMAT_HEIGHT_MASK |
953 RADEON_TXFORMAT_CUBIC_MAP_ENABLE |
954 RADEON_TXFORMAT_F5_WIDTH_MASK |
955 RADEON_TXFORMAT_F5_HEIGHT_MASK);
956 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_WIDTH_SHIFT) |
957 (log2Height << RADEON_TXFORMAT_HEIGHT_SHIFT));
958
959 t->tile_bits = 0;
960
961 if (t->base.Target == GL_TEXTURE_CUBE_MAP) {
962 assert(log2Width == log2Height);
963 t->pp_txformat |= ((log2Width << RADEON_TXFORMAT_F5_WIDTH_SHIFT) |
964 (log2Height << RADEON_TXFORMAT_F5_HEIGHT_SHIFT) |
965 /* don't think we need this bit, if it exists at all - fglrx does not set it */
966 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE));
967 t->pp_cubic_faces = ((log2Width << RADEON_FACE_WIDTH_1_SHIFT) |
968 (log2Height << RADEON_FACE_HEIGHT_1_SHIFT) |
969 (log2Width << RADEON_FACE_WIDTH_2_SHIFT) |
970 (log2Height << RADEON_FACE_HEIGHT_2_SHIFT) |
971 (log2Width << RADEON_FACE_WIDTH_3_SHIFT) |
972 (log2Height << RADEON_FACE_HEIGHT_3_SHIFT) |
973 (log2Width << RADEON_FACE_WIDTH_4_SHIFT) |
974 (log2Height << RADEON_FACE_HEIGHT_4_SHIFT));
975 }
976
977 t->pp_txsize = (((firstImage->Width - 1) << RADEON_TEX_USIZE_SHIFT)
978 | ((firstImage->Height - 1) << RADEON_TEX_VSIZE_SHIFT));
979
980 if ( !t->image_override ) {
981 if (_mesa_is_format_compressed(firstImage->TexFormat))
982 t->pp_txpitch = (firstImage->Width + 63) & ~(63);
983 else
984 t->pp_txpitch = ((firstImage->Width * texelBytes) + 63) & ~(63);
985 t->pp_txpitch -= 32;
986 }
987
988 if (t->base.Target == GL_TEXTURE_RECTANGLE_NV) {
989 t->pp_txformat |= RADEON_TXFORMAT_NON_POWER2;
990 }
991
992 return GL_TRUE;
993 }
994
995 static GLboolean radeon_validate_texture(struct gl_context *ctx, struct gl_texture_object *texObj, int unit)
996 {
997 r100ContextPtr rmesa = R100_CONTEXT(ctx);
998 radeonTexObj *t = radeon_tex_obj(texObj);
999 int ret;
1000
1001 if (!radeon_validate_texture_miptree(ctx, _mesa_get_samplerobj(ctx, unit), texObj))
1002 return GL_FALSE;
1003
1004 ret = setup_hardware_state(rmesa, t, unit);
1005 if (ret == GL_FALSE)
1006 return GL_FALSE;
1007
1008 /* yuv conversion only works in first unit */
1009 if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB))
1010 return GL_FALSE;
1011
1012 RADEON_STATECHANGE( rmesa, ctx );
1013 rmesa->hw.ctx.cmd[CTX_PP_CNTL] |=
1014 (RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE) << unit;
1015 RADEON_STATECHANGE( rmesa, tcl );
1016 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] |= RADEON_ST_BIT(unit);
1017
1018 rmesa->recheck_texgen[unit] = GL_TRUE;
1019
1020 radeonTexUpdateParameters(ctx, unit);
1021 import_tex_obj_state( rmesa, unit, t );
1022
1023 if (rmesa->recheck_texgen[unit]) {
1024 GLboolean fallback = !radeon_validate_texgen( ctx, unit );
1025 TCL_FALLBACK( ctx, (RADEON_TCL_FALLBACK_TEXGEN_0<<unit), fallback);
1026 rmesa->recheck_texgen[unit] = 0;
1027 rmesa->radeon.NewGLState |= _NEW_TEXTURE_MATRIX;
1028 }
1029
1030 if ( ! radeonUpdateTextureEnv( ctx, unit ) ) {
1031 return GL_FALSE;
1032 }
1033 FALLBACK( rmesa, RADEON_FALLBACK_BORDER_MODE, t->border_fallback );
1034
1035 t->validated = GL_TRUE;
1036 return !t->border_fallback;
1037 }
1038
1039 static GLboolean radeonUpdateTextureUnit( struct gl_context *ctx, int unit )
1040 {
1041 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1042
1043 if (ctx->Texture.Unit[unit]._Current &&
1044 ctx->Texture.Unit[unit]._Current->Target == GL_TEXTURE_3D) {
1045 disable_tex_obj_state(rmesa, unit);
1046 rmesa->state.texture.unit[unit].texobj = NULL;
1047 return GL_FALSE;
1048 }
1049
1050 if (!ctx->Texture.Unit[unit]._Current) {
1051 /* disable the unit */
1052 disable_tex_obj_state(rmesa, unit);
1053 rmesa->state.texture.unit[unit].texobj = NULL;
1054 return GL_TRUE;
1055 }
1056
1057 if (!radeon_validate_texture(ctx, ctx->Texture.Unit[unit]._Current, unit)) {
1058 _mesa_warning(ctx,
1059 "failed to validate texture for unit %d.\n",
1060 unit);
1061 rmesa->state.texture.unit[unit].texobj = NULL;
1062 return GL_FALSE;
1063 }
1064 rmesa->state.texture.unit[unit].texobj = radeon_tex_obj(ctx->Texture.Unit[unit]._Current);
1065 return GL_TRUE;
1066 }
1067
1068 void radeonUpdateTextureState( struct gl_context *ctx )
1069 {
1070 r100ContextPtr rmesa = R100_CONTEXT(ctx);
1071 GLboolean ok;
1072
1073 /* set the ctx all textures off */
1074 RADEON_STATECHANGE( rmesa, ctx );
1075 rmesa->hw.ctx.cmd[CTX_PP_CNTL] &= ~((RADEON_TEX_ENABLE_MASK) | (RADEON_TEX_BLEND_ENABLE_MASK));
1076
1077 ok = (radeonUpdateTextureUnit( ctx, 0 ) &&
1078 radeonUpdateTextureUnit( ctx, 1 ) &&
1079 radeonUpdateTextureUnit( ctx, 2 ));
1080
1081 FALLBACK( rmesa, RADEON_FALLBACK_TEXTURE, !ok );
1082
1083 if (rmesa->radeon.TclFallback)
1084 radeonChooseVertexState( ctx );
1085 }