1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
36 #include "main/glheader.h"
37 #include "main/imports.h"
38 #include "main/colormac.h"
39 #include "main/context.h"
40 #include "main/macros.h"
41 #include "main/teximage.h"
42 #include "main/texstate.h"
43 #include "main/texobj.h"
44 #include "main/enums.h"
46 #include "radeon_context.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_state.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_tex.h"
52 #include "radeon_tcl.h"
55 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
56 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
57 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
58 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
59 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
60 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
61 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
62 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
63 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
66 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
67 #define _COLOR_REV(f) \
68 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
70 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
71 #define _ALPHA_REV(f) \
72 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
74 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
76 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
77 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
78 && (tx_table[f].format != 0xffffffff) )
81 GLuint format
, filter
;
84 /* XXX verify this table against MESA_FORMAT_x values */
85 static const struct tx_table tx_table
[] =
87 _INVALID(NONE
), /* MESA_FORMAT_NONE */
92 [ MESA_FORMAT_RGB888
] = { RADEON_TXFORMAT_ARGB8888
, 0 },
118 /* ================================================================
119 * Texture combine functions
122 /* GL_ARB_texture_env_combine support
125 /* The color tables have combine functions for GL_SRC_COLOR,
126 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
128 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
131 RADEON_COLOR_ARG_A_T0_COLOR
,
132 RADEON_COLOR_ARG_A_T1_COLOR
,
133 RADEON_COLOR_ARG_A_T2_COLOR
136 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
137 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
138 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
141 RADEON_COLOR_ARG_A_T0_ALPHA
,
142 RADEON_COLOR_ARG_A_T1_ALPHA
,
143 RADEON_COLOR_ARG_A_T2_ALPHA
146 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
147 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
148 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
152 static GLuint radeon_tfactor_color
[] =
154 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
155 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
156 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
157 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
160 static GLuint radeon_primary_color
[] =
162 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
163 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
164 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
165 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
168 static GLuint radeon_previous_color
[] =
170 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
171 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
172 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
173 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
176 /* GL_ZERO table - indices 0-3
177 * GL_ONE table - indices 1-4
179 static GLuint radeon_zero_color
[] =
181 RADEON_COLOR_ARG_A_ZERO
,
182 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
183 RADEON_COLOR_ARG_A_ZERO
,
184 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
185 RADEON_COLOR_ARG_A_ZERO
189 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
191 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
194 RADEON_ALPHA_ARG_A_T0_ALPHA
,
195 RADEON_ALPHA_ARG_A_T1_ALPHA
,
196 RADEON_ALPHA_ARG_A_T2_ALPHA
199 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
200 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
201 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
205 static GLuint radeon_tfactor_alpha
[] =
207 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
208 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
211 static GLuint radeon_primary_alpha
[] =
213 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
214 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
217 static GLuint radeon_previous_alpha
[] =
219 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
220 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
223 /* GL_ZERO table - indices 0-1
224 * GL_ONE table - indices 1-2
226 static GLuint radeon_zero_alpha
[] =
228 RADEON_ALPHA_ARG_A_ZERO
,
229 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
230 RADEON_ALPHA_ARG_A_ZERO
234 /* Extract the arg from slot A, shift it into the correct argument slot
235 * and set the corresponding complement bit.
237 #define RADEON_COLOR_ARG( n, arg ) \
240 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
241 << RADEON_COLOR_ARG_##arg##_SHIFT); \
243 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
244 << RADEON_COMP_ARG_##arg##_SHIFT); \
247 #define RADEON_ALPHA_ARG( n, arg ) \
250 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
251 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
253 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
254 << RADEON_COMP_ARG_##arg##_SHIFT); \
258 /* ================================================================
259 * Texture unit state management
262 static GLboolean
radeonUpdateTextureEnv( struct gl_context
*ctx
, int unit
)
264 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
265 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
266 GLuint color_combine
, alpha_combine
;
267 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
268 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
269 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
270 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
271 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
272 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
275 /* texUnit->_Current can be NULL if and only if the texture unit is
276 * not actually enabled.
278 assert( (texUnit
->_ReallyEnabled
== 0)
279 || (texUnit
->_Current
!= NULL
) );
281 if ( RADEON_DEBUG
& RADEON_TEXTURE
) {
282 fprintf( stderr
, "%s( %p, %d )\n", __FUNCTION__
, (void *)ctx
, unit
);
285 /* Set the texture environment state. Isn't this nice and clean?
286 * The chip will automagically set the texture alpha to 0xff when
287 * the texture format does not include an alpha component. This
288 * reduces the amount of special-casing we have to do, alpha-only
289 * textures being a notable exception. Doesn't work for luminance
290 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
292 /* Don't cache these results.
294 rmesa
->state
.texture
.unit
[unit
].format
= 0;
295 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
297 if ( !texUnit
->_ReallyEnabled
) {
298 color_combine
= color_combine0
;
299 alpha_combine
= alpha_combine0
;
302 GLuint color_arg
[3], alpha_arg
[3];
304 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
305 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
306 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
307 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
311 * Extract the color and alpha combine function arguments.
313 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
314 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
315 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
320 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
321 color_arg
[i
] = radeon_zero_color
[op
];
323 color_arg
[i
] = radeon_texture_color
[op
][unit
];
326 color_arg
[i
] = radeon_tfactor_color
[op
];
328 case GL_PRIMARY_COLOR
:
329 color_arg
[i
] = radeon_primary_color
[op
];
332 color_arg
[i
] = radeon_previous_color
[op
];
335 color_arg
[i
] = radeon_zero_color
[op
];
338 color_arg
[i
] = radeon_zero_color
[op
+1];
343 GLuint txunit
= srcRGBi
- GL_TEXTURE0
;
344 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
345 color_arg
[i
] = radeon_zero_color
[op
];
347 /* implement ogl 1.4/1.5 core spec here, not specification of
348 * GL_ARB_texture_env_crossbar (which would require disabling blending
349 * instead of undefined results when referencing not enabled texunit) */
350 color_arg
[i
] = radeon_texture_color
[op
][txunit
];
358 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
359 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
360 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
365 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
366 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
368 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
371 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
373 case GL_PRIMARY_COLOR
:
374 alpha_arg
[i
] = radeon_primary_alpha
[op
];
377 alpha_arg
[i
] = radeon_previous_alpha
[op
];
380 alpha_arg
[i
] = radeon_zero_alpha
[op
];
383 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
388 GLuint txunit
= srcAi
- GL_TEXTURE0
;
389 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
390 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
392 alpha_arg
[i
] = radeon_texture_alpha
[op
][txunit
];
401 * Build up the color and alpha combine functions.
403 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
405 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
406 RADEON_COLOR_ARG_B_ZERO
|
407 RADEON_BLEND_CTL_ADD
|
409 RADEON_COLOR_ARG( 0, C
);
412 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
413 RADEON_BLEND_CTL_ADD
|
415 RADEON_COLOR_ARG( 0, A
);
416 RADEON_COLOR_ARG( 1, B
);
419 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
421 RADEON_BLEND_CTL_ADD
|
423 RADEON_COLOR_ARG( 0, A
);
424 RADEON_COLOR_ARG( 1, C
);
427 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
429 RADEON_BLEND_CTL_ADDSIGNED
|
431 RADEON_COLOR_ARG( 0, A
);
432 RADEON_COLOR_ARG( 1, C
);
435 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
437 RADEON_BLEND_CTL_SUBTRACT
|
439 RADEON_COLOR_ARG( 0, A
);
440 RADEON_COLOR_ARG( 1, C
);
443 color_combine
= (RADEON_BLEND_CTL_BLEND
|
445 RADEON_COLOR_ARG( 0, B
);
446 RADEON_COLOR_ARG( 1, A
);
447 RADEON_COLOR_ARG( 2, C
);
450 case GL_DOT3_RGB_EXT
:
451 case GL_DOT3_RGBA_EXT
:
452 /* The EXT version of the DOT3 extension does not support the
453 * scale factor, but the ARB version (and the version in OpenGL
461 /* The R100 / RV200 only support a 1X multiplier in hardware
464 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
469 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
470 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
471 /* is it necessary to set this or will it be ignored anyway? */
475 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
476 RADEON_BLEND_CTL_DOT3
|
478 RADEON_COLOR_ARG( 0, A
);
479 RADEON_COLOR_ARG( 1, B
);
482 case GL_MODULATE_ADD_ATI
:
483 color_combine
= (RADEON_BLEND_CTL_ADD
|
485 RADEON_COLOR_ARG( 0, A
);
486 RADEON_COLOR_ARG( 1, C
);
487 RADEON_COLOR_ARG( 2, B
);
489 case GL_MODULATE_SIGNED_ADD_ATI
:
490 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
492 RADEON_COLOR_ARG( 0, A
);
493 RADEON_COLOR_ARG( 1, C
);
494 RADEON_COLOR_ARG( 2, B
);
496 case GL_MODULATE_SUBTRACT_ATI
:
497 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
499 RADEON_COLOR_ARG( 0, A
);
500 RADEON_COLOR_ARG( 1, C
);
501 RADEON_COLOR_ARG( 2, B
);
507 switch ( texUnit
->_CurrentCombine
->ModeA
) {
509 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
510 RADEON_ALPHA_ARG_B_ZERO
|
511 RADEON_BLEND_CTL_ADD
|
513 RADEON_ALPHA_ARG( 0, C
);
516 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
517 RADEON_BLEND_CTL_ADD
|
519 RADEON_ALPHA_ARG( 0, A
);
520 RADEON_ALPHA_ARG( 1, B
);
523 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
525 RADEON_BLEND_CTL_ADD
|
527 RADEON_ALPHA_ARG( 0, A
);
528 RADEON_ALPHA_ARG( 1, C
);
531 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
533 RADEON_BLEND_CTL_ADDSIGNED
|
535 RADEON_ALPHA_ARG( 0, A
);
536 RADEON_ALPHA_ARG( 1, C
);
539 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
541 RADEON_BLEND_CTL_SUBTRACT
|
543 RADEON_ALPHA_ARG( 0, A
);
544 RADEON_ALPHA_ARG( 1, C
);
547 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
549 RADEON_ALPHA_ARG( 0, B
);
550 RADEON_ALPHA_ARG( 1, A
);
551 RADEON_ALPHA_ARG( 2, C
);
554 case GL_MODULATE_ADD_ATI
:
555 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
557 RADEON_ALPHA_ARG( 0, A
);
558 RADEON_ALPHA_ARG( 1, C
);
559 RADEON_ALPHA_ARG( 2, B
);
561 case GL_MODULATE_SIGNED_ADD_ATI
:
562 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
564 RADEON_ALPHA_ARG( 0, A
);
565 RADEON_ALPHA_ARG( 1, C
);
566 RADEON_ALPHA_ARG( 2, B
);
568 case GL_MODULATE_SUBTRACT_ATI
:
569 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
571 RADEON_ALPHA_ARG( 0, A
);
572 RADEON_ALPHA_ARG( 1, C
);
573 RADEON_ALPHA_ARG( 2, B
);
579 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
580 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
581 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
585 * Apply the scale factor.
587 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
588 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
594 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
595 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
596 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
597 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
598 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
604 void radeonSetTexBuffer2(__DRIcontext
*pDRICtx
, GLint target
, GLint texture_format
,
605 __DRIdrawable
*dPriv
)
607 struct gl_texture_unit
*texUnit
;
608 struct gl_texture_object
*texObj
;
609 struct gl_texture_image
*texImage
;
610 struct radeon_renderbuffer
*rb
;
611 radeon_texture_image
*rImage
;
612 radeonContextPtr radeon
;
613 struct radeon_framebuffer
*rfb
;
618 radeon
= pDRICtx
->driverPrivate
;
620 rfb
= dPriv
->driverPrivate
;
621 texUnit
= _mesa_get_current_tex_unit(radeon
->glCtx
);
622 texObj
= _mesa_select_tex_object(radeon
->glCtx
, texUnit
, target
);
623 texImage
= _mesa_get_tex_image(radeon
->glCtx
, texObj
, target
, 0);
625 rImage
= get_radeon_texture_image(texImage
);
626 t
= radeon_tex_obj(texObj
);
631 radeon_update_renderbuffers(pDRICtx
, dPriv
, GL_TRUE
);
632 rb
= rfb
->color_rb
[0];
633 if (rb
->bo
== NULL
) {
634 /* Failed to BO for the buffer */
638 _mesa_lock_texture(radeon
->glCtx
, texObj
);
640 radeon_bo_unref(t
->bo
);
644 radeon_bo_unref(rImage
->bo
);
648 radeon_miptree_unreference(&t
->mt
);
649 radeon_miptree_unreference(&rImage
->mt
);
652 radeon_bo_ref(rImage
->bo
);
654 radeon_bo_ref(t
->bo
);
656 t
->image_override
= GL_TRUE
;
657 t
->override_offset
= 0;
660 if (texture_format
== __DRI_TEXTURE_FORMAT_RGB
) {
661 t
->pp_txformat
= tx_table
[MESA_FORMAT_RGB888
].format
;
662 texFormat
= MESA_FORMAT_RGB888
;
665 t
->pp_txformat
= tx_table
[MESA_FORMAT_ARGB8888
].format
;
666 texFormat
= MESA_FORMAT_ARGB8888
;
668 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_ARGB8888
].filter
;
672 texFormat
= MESA_FORMAT_RGB888
;
673 t
->pp_txformat
= tx_table
[MESA_FORMAT_RGB888
].format
;
674 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_RGB888
].filter
;
677 texFormat
= MESA_FORMAT_RGB565
;
678 t
->pp_txformat
= tx_table
[MESA_FORMAT_RGB565
].format
;
679 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_RGB565
].filter
;
683 _mesa_init_teximage_fields(radeon
->glCtx
, texImage
,
684 rb
->base
.Width
, rb
->base
.Height
, 1, 0,
686 rImage
->base
.RowStride
= rb
->pitch
/ rb
->cpp
;
688 t
->pp_txpitch
&= (1 << 13) -1;
689 pitch_val
= rb
->pitch
;
691 t
->pp_txsize
= ((rb
->base
.Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
692 | ((rb
->base
.Height
- 1) << RADEON_TEX_VSIZE_SHIFT
);
693 if (target
== GL_TEXTURE_RECTANGLE_NV
) {
694 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
695 t
->pp_txpitch
= pitch_val
;
698 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
699 RADEON_TXFORMAT_HEIGHT_MASK
|
700 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
701 RADEON_TXFORMAT_F5_WIDTH_MASK
|
702 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
703 t
->pp_txformat
|= ((texImage
->WidthLog2
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
704 (texImage
->HeightLog2
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
706 t
->validated
= GL_TRUE
;
707 _mesa_unlock_texture(radeon
->glCtx
, texObj
);
712 void radeonSetTexBuffer(__DRIcontext
*pDRICtx
, GLint target
, __DRIdrawable
*dPriv
)
714 radeonSetTexBuffer2(pDRICtx
, target
, __DRI_TEXTURE_FORMAT_RGBA
, dPriv
);
718 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
719 RADEON_MIN_FILTER_MASK | \
720 RADEON_MAG_FILTER_MASK | \
721 RADEON_MAX_ANISO_MASK | \
722 RADEON_YUV_TO_RGB | \
723 RADEON_YUV_TEMPERATURE_MASK | \
724 RADEON_CLAMP_S_MASK | \
725 RADEON_CLAMP_T_MASK | \
726 RADEON_BORDER_MODE_D3D )
728 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
729 RADEON_TXFORMAT_HEIGHT_MASK | \
730 RADEON_TXFORMAT_FORMAT_MASK | \
731 RADEON_TXFORMAT_F5_WIDTH_MASK | \
732 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
733 RADEON_TXFORMAT_ALPHA_IN_MAP | \
734 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
735 RADEON_TXFORMAT_NON_POWER2)
738 static void disable_tex_obj_state( r100ContextPtr rmesa
,
741 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
743 RADEON_STATECHANGE( rmesa
, tcl
);
744 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_ST_BIT(unit
) |
747 if (rmesa
->radeon
.TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
748 TCL_FALLBACK( rmesa
->radeon
.glCtx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
749 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
752 if (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE
) {
753 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
754 cubic_map bit on unit 2 when the unit is disabled, otherwise every
755 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
756 units, better be safe than sorry though).*/
757 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
758 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE
;
762 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
763 GLuint tmp
= rmesa
->TexGenEnabled
;
765 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
766 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
767 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
768 rmesa
->TexGenNeedNormals
[unit
] = 0;
769 rmesa
->TexGenEnabled
|=
770 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
772 if (tmp
!= rmesa
->TexGenEnabled
) {
773 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
774 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
779 static void import_tex_obj_state( r100ContextPtr rmesa
,
781 radeonTexObjPtr texobj
)
783 /* do not use RADEON_DB_STATE to avoid stale texture caches */
784 uint32_t *cmd
= &rmesa
->hw
.tex
[unit
].cmd
[TEX_CMD_0
];
785 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
787 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
789 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
790 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
791 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
792 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
793 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
795 if (texobj
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
796 uint32_t *txr_cmd
= &rmesa
->hw
.txr
[unit
].cmd
[TXR_CMD_0
];
797 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
798 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
799 RADEON_STATECHANGE( rmesa
, txr
[unit
] );
802 if (texobj
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
803 se_coord_fmt
|= RADEON_VTX_ST0_NONPARAMETRIC
<< unit
;
806 se_coord_fmt
&= ~(RADEON_VTX_ST0_NONPARAMETRIC
<< unit
);
808 if (texobj
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
809 uint32_t *cube_cmd
= &rmesa
->hw
.cube
[unit
].cmd
[CUBE_CMD_0
];
811 RADEON_STATECHANGE( rmesa
, cube
[unit
] );
812 cube_cmd
[CUBE_PP_CUBIC_FACES
] = texobj
->pp_cubic_faces
;
813 /* state filled out in the cube_emit */
817 if (se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
]) {
818 RADEON_STATECHANGE( rmesa
, set
);
819 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
822 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
826 static void set_texgen_matrix( r100ContextPtr rmesa
,
828 const GLfloat
*s_plane
,
829 const GLfloat
*t_plane
,
830 const GLfloat
*r_plane
,
831 const GLfloat
*q_plane
)
833 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
834 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
835 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
836 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
838 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
839 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
840 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
841 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
843 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
844 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
845 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
846 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
848 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
849 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
850 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
851 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
853 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
854 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
857 /* Returns GL_FALSE if fallback required.
859 static GLboolean
radeon_validate_texgen( struct gl_context
*ctx
, GLuint unit
)
861 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
862 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
863 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
864 GLuint tmp
= rmesa
->TexGenEnabled
;
865 static const GLfloat reflect
[16] = {
871 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
872 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
873 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
874 rmesa
->TexGenNeedNormals
[unit
] = 0;
876 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
877 /* Disabled, no fallback:
879 rmesa
->TexGenEnabled
|=
880 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
883 /* the r100 cannot do texgen for some coords and not for others
884 * we do not detect such cases (certainly can't do it here) and just
885 * ASSUME that when S and T are texgen enabled we do not need other
886 * non-texgen enabled coords, no matter if the R and Q bits are texgen
887 * enabled. Still check for mixed mode texgen for all coords.
889 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
890 (texUnit
->TexGenEnabled
& T_BIT
) &&
891 (texUnit
->GenS
.Mode
== texUnit
->GenT
.Mode
) ) {
892 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
893 (texUnit
->GenS
.Mode
!= texUnit
->GenR
.Mode
)) ||
894 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
895 (texUnit
->GenS
.Mode
!= texUnit
->GenQ
.Mode
)) ) {
896 /* Mixed modes, fallback:
898 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
899 fprintf(stderr
, "fallback mixed texgen\n");
902 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
905 /* some texgen mode not including both S and T bits */
906 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
907 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
911 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
912 /* need this here for vtxfmt presumably. Argh we need to set
913 this from way too many places, would be much easier if we could leave
914 tcl q coord always enabled as on r200) */
915 RADEON_STATECHANGE( rmesa
, tcl
);
916 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_Q_BIT(unit
);
919 switch (texUnit
->GenS
.Mode
) {
920 case GL_OBJECT_LINEAR
:
921 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
922 set_texgen_matrix( rmesa
, unit
,
923 texUnit
->GenS
.ObjectPlane
,
924 texUnit
->GenT
.ObjectPlane
,
925 texUnit
->GenR
.ObjectPlane
,
926 texUnit
->GenQ
.ObjectPlane
);
930 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
931 set_texgen_matrix( rmesa
, unit
,
932 texUnit
->GenS
.EyePlane
,
933 texUnit
->GenT
.EyePlane
,
934 texUnit
->GenR
.EyePlane
,
935 texUnit
->GenQ
.EyePlane
);
938 case GL_REFLECTION_MAP_NV
:
939 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
940 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
941 /* TODO: unknown if this is needed/correct */
942 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
943 reflect
+ 8, reflect
+ 12 );
946 case GL_NORMAL_MAP_NV
:
947 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
948 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
952 /* the mode which everyone uses :-( */
954 /* Unsupported mode, fallback:
956 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
957 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
961 if (tmp
!= rmesa
->TexGenEnabled
) {
962 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
969 * Compute the cached hardware register values for the given texture object.
971 * \param rmesa Context pointer
972 * \param t the r300 texture object
974 static GLboolean
setup_hardware_state(r100ContextPtr rmesa
, radeonTexObj
*t
, int unit
)
976 const struct gl_texture_image
*firstImage
;
977 GLint log2Width
, log2Height
, texelBytes
;
983 firstImage
= t
->base
.Image
[0][t
->minLod
];
985 log2Width
= firstImage
->WidthLog2
;
986 log2Height
= firstImage
->HeightLog2
;
987 texelBytes
= _mesa_get_format_bytes(firstImage
->TexFormat
);
989 if (!t
->image_override
) {
990 if (VALID_FORMAT(firstImage
->TexFormat
)) {
991 const struct tx_table
*table
= tx_table
;
993 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
994 RADEON_TXFORMAT_ALPHA_IN_MAP
);
995 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
997 t
->pp_txformat
|= table
[ firstImage
->TexFormat
].format
;
998 t
->pp_txfilter
|= table
[ firstImage
->TexFormat
].filter
;
1000 _mesa_problem(NULL
, "unexpected texture format in %s",
1006 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
1007 t
->pp_txfilter
|= (t
->maxLod
- t
->minLod
) << RADEON_MAX_MIP_LEVEL_SHIFT
;
1009 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
1010 RADEON_TXFORMAT_HEIGHT_MASK
|
1011 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
1012 RADEON_TXFORMAT_F5_WIDTH_MASK
|
1013 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
1014 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
1015 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
1019 if (t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
1020 ASSERT(log2Width
== log2Height
);
1021 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_F5_WIDTH_SHIFT
) |
1022 (log2Height
<< RADEON_TXFORMAT_F5_HEIGHT_SHIFT
) |
1023 /* don't think we need this bit, if it exists at all - fglrx does not set it */
1024 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE
));
1025 t
->pp_cubic_faces
= ((log2Width
<< RADEON_FACE_WIDTH_1_SHIFT
) |
1026 (log2Height
<< RADEON_FACE_HEIGHT_1_SHIFT
) |
1027 (log2Width
<< RADEON_FACE_WIDTH_2_SHIFT
) |
1028 (log2Height
<< RADEON_FACE_HEIGHT_2_SHIFT
) |
1029 (log2Width
<< RADEON_FACE_WIDTH_3_SHIFT
) |
1030 (log2Height
<< RADEON_FACE_HEIGHT_3_SHIFT
) |
1031 (log2Width
<< RADEON_FACE_WIDTH_4_SHIFT
) |
1032 (log2Height
<< RADEON_FACE_HEIGHT_4_SHIFT
));
1035 t
->pp_txsize
= (((firstImage
->Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
1036 | ((firstImage
->Height
- 1) << RADEON_TEX_VSIZE_SHIFT
));
1038 if ( !t
->image_override
) {
1039 if (_mesa_is_format_compressed(firstImage
->TexFormat
))
1040 t
->pp_txpitch
= (firstImage
->Width
+ 63) & ~(63);
1042 t
->pp_txpitch
= ((firstImage
->Width
* texelBytes
) + 63) & ~(63);
1043 t
->pp_txpitch
-= 32;
1046 if (t
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
1047 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
1053 static GLboolean
radeon_validate_texture(struct gl_context
*ctx
, struct gl_texture_object
*texObj
, int unit
)
1055 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1056 radeonTexObj
*t
= radeon_tex_obj(texObj
);
1059 if (!radeon_validate_texture_miptree(ctx
, texObj
))
1062 ret
= setup_hardware_state(rmesa
, t
, unit
);
1063 if (ret
== GL_FALSE
)
1066 /* yuv conversion only works in first unit */
1067 if (unit
!= 0 && (t
->pp_txfilter
& RADEON_YUV_TO_RGB
))
1070 RADEON_STATECHANGE( rmesa
, ctx
);
1071 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1072 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1073 RADEON_STATECHANGE( rmesa
, tcl
);
1074 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_ST_BIT(unit
);
1076 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1078 import_tex_obj_state( rmesa
, unit
, t
);
1080 if (rmesa
->recheck_texgen
[unit
]) {
1081 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1082 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1083 rmesa
->recheck_texgen
[unit
] = 0;
1084 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
1087 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1090 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1092 t
->validated
= GL_TRUE
;
1093 return !t
->border_fallback
;
1096 static GLboolean
radeonUpdateTextureUnit( struct gl_context
*ctx
, int unit
)
1098 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1100 if (ctx
->Texture
.Unit
[unit
]._ReallyEnabled
& TEXTURE_3D_BIT
) {
1101 disable_tex_obj_state(rmesa
, unit
);
1102 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1106 if (!ctx
->Texture
.Unit
[unit
]._ReallyEnabled
) {
1107 /* disable the unit */
1108 disable_tex_obj_state(rmesa
, unit
);
1109 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1113 if (!radeon_validate_texture(ctx
, ctx
->Texture
.Unit
[unit
]._Current
, unit
)) {
1115 "failed to validate texture for unit %d.\n",
1117 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1120 rmesa
->state
.texture
.unit
[unit
].texobj
= radeon_tex_obj(ctx
->Texture
.Unit
[unit
]._Current
);
1124 void radeonUpdateTextureState( struct gl_context
*ctx
)
1126 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1129 /* set the ctx all textures off */
1130 RADEON_STATECHANGE( rmesa
, ctx
);
1131 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~((RADEON_TEX_ENABLE_MASK
) | (RADEON_TEX_BLEND_ENABLE_MASK
));
1133 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1134 radeonUpdateTextureUnit( ctx
, 1 ) &&
1135 radeonUpdateTextureUnit( ctx
, 2 ));
1137 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1139 if (rmesa
->radeon
.TclFallback
)
1140 radeonChooseVertexState( ctx
);