1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
36 #include "main/glheader.h"
37 #include "main/imports.h"
38 #include "main/colormac.h"
39 #include "main/context.h"
40 #include "main/macros.h"
41 #include "main/texformat.h"
42 #include "main/teximage.h"
43 #include "main/texobj.h"
44 #include "main/enums.h"
46 #include "radeon_context.h"
47 #include "radeon_mipmap_tree.h"
48 #include "radeon_state.h"
49 #include "radeon_ioctl.h"
50 #include "radeon_swtcl.h"
51 #include "radeon_tex.h"
52 #include "radeon_tcl.h"
55 #define RADEON_TXFORMAT_A8 RADEON_TXFORMAT_I8
56 #define RADEON_TXFORMAT_L8 RADEON_TXFORMAT_I8
57 #define RADEON_TXFORMAT_AL88 RADEON_TXFORMAT_AI88
58 #define RADEON_TXFORMAT_YCBCR RADEON_TXFORMAT_YVYU422
59 #define RADEON_TXFORMAT_YCBCR_REV RADEON_TXFORMAT_VYUY422
60 #define RADEON_TXFORMAT_RGB_DXT1 RADEON_TXFORMAT_DXT1
61 #define RADEON_TXFORMAT_RGBA_DXT1 RADEON_TXFORMAT_DXT1
62 #define RADEON_TXFORMAT_RGBA_DXT3 RADEON_TXFORMAT_DXT23
63 #define RADEON_TXFORMAT_RGBA_DXT5 RADEON_TXFORMAT_DXT45
66 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, 0 }
67 #define _COLOR_REV(f) \
68 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f, 0 }
70 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
71 #define _ALPHA_REV(f) \
72 [ MESA_FORMAT_ ## f ## _REV ] = { RADEON_TXFORMAT_ ## f | RADEON_TXFORMAT_ALPHA_IN_MAP, 0 }
74 [ MESA_FORMAT_ ## f ] = { RADEON_TXFORMAT_ ## f, RADEON_YUV_TO_RGB }
76 [ MESA_FORMAT_ ## f ] = { 0xffffffff, 0 }
77 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
78 && (tx_table[f].format != 0xffffffff) )
81 GLuint format
, filter
;
84 static const struct tx_table tx_table
[] =
90 [ MESA_FORMAT_RGB888
] = { RADEON_TXFORMAT_ARGB8888
, 0 },
117 /* ================================================================
118 * Texture combine functions
121 /* GL_ARB_texture_env_combine support
124 /* The color tables have combine functions for GL_SRC_COLOR,
125 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
127 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
130 RADEON_COLOR_ARG_A_T0_COLOR
,
131 RADEON_COLOR_ARG_A_T1_COLOR
,
132 RADEON_COLOR_ARG_A_T2_COLOR
135 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
136 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
137 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
140 RADEON_COLOR_ARG_A_T0_ALPHA
,
141 RADEON_COLOR_ARG_A_T1_ALPHA
,
142 RADEON_COLOR_ARG_A_T2_ALPHA
145 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
146 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
147 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
151 static GLuint radeon_tfactor_color
[] =
153 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
154 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
155 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
156 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
159 static GLuint radeon_primary_color
[] =
161 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
162 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
163 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
164 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
167 static GLuint radeon_previous_color
[] =
169 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
170 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
171 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
172 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
175 /* GL_ZERO table - indices 0-3
176 * GL_ONE table - indices 1-4
178 static GLuint radeon_zero_color
[] =
180 RADEON_COLOR_ARG_A_ZERO
,
181 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
182 RADEON_COLOR_ARG_A_ZERO
,
183 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
184 RADEON_COLOR_ARG_A_ZERO
188 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
190 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
193 RADEON_ALPHA_ARG_A_T0_ALPHA
,
194 RADEON_ALPHA_ARG_A_T1_ALPHA
,
195 RADEON_ALPHA_ARG_A_T2_ALPHA
198 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
199 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
200 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
204 static GLuint radeon_tfactor_alpha
[] =
206 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
207 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
210 static GLuint radeon_primary_alpha
[] =
212 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
213 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
216 static GLuint radeon_previous_alpha
[] =
218 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
219 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
222 /* GL_ZERO table - indices 0-1
223 * GL_ONE table - indices 1-2
225 static GLuint radeon_zero_alpha
[] =
227 RADEON_ALPHA_ARG_A_ZERO
,
228 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
229 RADEON_ALPHA_ARG_A_ZERO
233 /* Extract the arg from slot A, shift it into the correct argument slot
234 * and set the corresponding complement bit.
236 #define RADEON_COLOR_ARG( n, arg ) \
239 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
240 << RADEON_COLOR_ARG_##arg##_SHIFT); \
242 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
243 << RADEON_COMP_ARG_##arg##_SHIFT); \
246 #define RADEON_ALPHA_ARG( n, arg ) \
249 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
250 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
252 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
253 << RADEON_COMP_ARG_##arg##_SHIFT); \
257 /* ================================================================
258 * Texture unit state management
261 static GLboolean
radeonUpdateTextureEnv( GLcontext
*ctx
, int unit
)
263 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
264 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
265 GLuint color_combine
, alpha_combine
;
266 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
267 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
268 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
269 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
270 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
271 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
274 /* texUnit->_Current can be NULL if and only if the texture unit is
275 * not actually enabled.
277 assert( (texUnit
->_ReallyEnabled
== 0)
278 || (texUnit
->_Current
!= NULL
) );
280 if ( RADEON_DEBUG
& DEBUG_TEXTURE
) {
281 fprintf( stderr
, "%s( %p, %d )\n", __FUNCTION__
, (void *)ctx
, unit
);
284 /* Set the texture environment state. Isn't this nice and clean?
285 * The chip will automagically set the texture alpha to 0xff when
286 * the texture format does not include an alpha component. This
287 * reduces the amount of special-casing we have to do, alpha-only
288 * textures being a notable exception. Doesn't work for luminance
289 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
291 /* Don't cache these results.
293 rmesa
->state
.texture
.unit
[unit
].format
= 0;
294 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
296 if ( !texUnit
->_ReallyEnabled
) {
297 color_combine
= color_combine0
;
298 alpha_combine
= alpha_combine0
;
301 GLuint color_arg
[3], alpha_arg
[3];
303 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
304 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
305 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
306 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
310 * Extract the color and alpha combine function arguments.
312 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
313 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
314 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
319 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
320 color_arg
[i
] = radeon_zero_color
[op
];
322 color_arg
[i
] = radeon_texture_color
[op
][unit
];
325 color_arg
[i
] = radeon_tfactor_color
[op
];
327 case GL_PRIMARY_COLOR
:
328 color_arg
[i
] = radeon_primary_color
[op
];
331 color_arg
[i
] = radeon_previous_color
[op
];
334 color_arg
[i
] = radeon_zero_color
[op
];
337 color_arg
[i
] = radeon_zero_color
[op
+1];
342 GLuint txunit
= srcRGBi
- GL_TEXTURE0
;
343 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
344 color_arg
[i
] = radeon_zero_color
[op
];
346 /* implement ogl 1.4/1.5 core spec here, not specification of
347 * GL_ARB_texture_env_crossbar (which would require disabling blending
348 * instead of undefined results when referencing not enabled texunit) */
349 color_arg
[i
] = radeon_texture_color
[op
][txunit
];
357 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
358 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
359 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
364 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
365 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
367 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
370 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
372 case GL_PRIMARY_COLOR
:
373 alpha_arg
[i
] = radeon_primary_alpha
[op
];
376 alpha_arg
[i
] = radeon_previous_alpha
[op
];
379 alpha_arg
[i
] = radeon_zero_alpha
[op
];
382 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
387 GLuint txunit
= srcAi
- GL_TEXTURE0
;
388 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
389 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
391 alpha_arg
[i
] = radeon_texture_alpha
[op
][txunit
];
400 * Build up the color and alpha combine functions.
402 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
404 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
405 RADEON_COLOR_ARG_B_ZERO
|
406 RADEON_BLEND_CTL_ADD
|
408 RADEON_COLOR_ARG( 0, C
);
411 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
412 RADEON_BLEND_CTL_ADD
|
414 RADEON_COLOR_ARG( 0, A
);
415 RADEON_COLOR_ARG( 1, B
);
418 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
420 RADEON_BLEND_CTL_ADD
|
422 RADEON_COLOR_ARG( 0, A
);
423 RADEON_COLOR_ARG( 1, C
);
426 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
428 RADEON_BLEND_CTL_ADDSIGNED
|
430 RADEON_COLOR_ARG( 0, A
);
431 RADEON_COLOR_ARG( 1, C
);
434 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
436 RADEON_BLEND_CTL_SUBTRACT
|
438 RADEON_COLOR_ARG( 0, A
);
439 RADEON_COLOR_ARG( 1, C
);
442 color_combine
= (RADEON_BLEND_CTL_BLEND
|
444 RADEON_COLOR_ARG( 0, B
);
445 RADEON_COLOR_ARG( 1, A
);
446 RADEON_COLOR_ARG( 2, C
);
449 case GL_DOT3_RGB_EXT
:
450 case GL_DOT3_RGBA_EXT
:
451 /* The EXT version of the DOT3 extension does not support the
452 * scale factor, but the ARB version (and the version in OpenGL
460 /* The R100 / RV200 only support a 1X multiplier in hardware
463 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
468 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
469 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
470 /* is it necessary to set this or will it be ignored anyway? */
474 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
475 RADEON_BLEND_CTL_DOT3
|
477 RADEON_COLOR_ARG( 0, A
);
478 RADEON_COLOR_ARG( 1, B
);
481 case GL_MODULATE_ADD_ATI
:
482 color_combine
= (RADEON_BLEND_CTL_ADD
|
484 RADEON_COLOR_ARG( 0, A
);
485 RADEON_COLOR_ARG( 1, C
);
486 RADEON_COLOR_ARG( 2, B
);
488 case GL_MODULATE_SIGNED_ADD_ATI
:
489 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
491 RADEON_COLOR_ARG( 0, A
);
492 RADEON_COLOR_ARG( 1, C
);
493 RADEON_COLOR_ARG( 2, B
);
495 case GL_MODULATE_SUBTRACT_ATI
:
496 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
498 RADEON_COLOR_ARG( 0, A
);
499 RADEON_COLOR_ARG( 1, C
);
500 RADEON_COLOR_ARG( 2, B
);
506 switch ( texUnit
->_CurrentCombine
->ModeA
) {
508 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
509 RADEON_ALPHA_ARG_B_ZERO
|
510 RADEON_BLEND_CTL_ADD
|
512 RADEON_ALPHA_ARG( 0, C
);
515 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
516 RADEON_BLEND_CTL_ADD
|
518 RADEON_ALPHA_ARG( 0, A
);
519 RADEON_ALPHA_ARG( 1, B
);
522 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
524 RADEON_BLEND_CTL_ADD
|
526 RADEON_ALPHA_ARG( 0, A
);
527 RADEON_ALPHA_ARG( 1, C
);
530 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
532 RADEON_BLEND_CTL_ADDSIGNED
|
534 RADEON_ALPHA_ARG( 0, A
);
535 RADEON_ALPHA_ARG( 1, C
);
538 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
540 RADEON_BLEND_CTL_SUBTRACT
|
542 RADEON_ALPHA_ARG( 0, A
);
543 RADEON_ALPHA_ARG( 1, C
);
546 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
548 RADEON_ALPHA_ARG( 0, B
);
549 RADEON_ALPHA_ARG( 1, A
);
550 RADEON_ALPHA_ARG( 2, C
);
553 case GL_MODULATE_ADD_ATI
:
554 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
556 RADEON_ALPHA_ARG( 0, A
);
557 RADEON_ALPHA_ARG( 1, C
);
558 RADEON_ALPHA_ARG( 2, B
);
560 case GL_MODULATE_SIGNED_ADD_ATI
:
561 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
563 RADEON_ALPHA_ARG( 0, A
);
564 RADEON_ALPHA_ARG( 1, C
);
565 RADEON_ALPHA_ARG( 2, B
);
567 case GL_MODULATE_SUBTRACT_ATI
:
568 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
570 RADEON_ALPHA_ARG( 0, A
);
571 RADEON_ALPHA_ARG( 1, C
);
572 RADEON_ALPHA_ARG( 2, B
);
578 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
579 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
580 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
584 * Apply the scale factor.
586 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
587 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
593 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
594 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
595 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
596 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
597 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
603 void radeonSetTexOffset(__DRIcontext
* pDRICtx
, GLint texname
,
604 unsigned long long offset
, GLint depth
, GLuint pitch
)
606 r100ContextPtr rmesa
= pDRICtx
->driverPrivate
;
607 struct gl_texture_object
*tObj
=
608 _mesa_lookup_texture(rmesa
->radeon
.glCtx
, texname
);
609 radeonTexObjPtr t
= radeon_tex_obj(tObj
);
614 t
->image_override
= GL_TRUE
;
620 t
->override_offset
= offset
;
621 t
->pp_txpitch
= pitch
- 32;
625 t
->pp_txformat
= tx_table
[MESA_FORMAT_ARGB8888
].format
;
626 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_ARGB8888
].filter
;
630 t
->pp_txformat
= tx_table
[MESA_FORMAT_RGB888
].format
;
631 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_RGB888
].filter
;
634 t
->pp_txformat
= tx_table
[MESA_FORMAT_RGB565
].format
;
635 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_RGB565
].filter
;
640 void radeonSetTexBuffer(__DRIcontext
*pDRICtx
, GLint target
, __DRIdrawable
*dPriv
)
642 struct gl_texture_unit
*texUnit
;
643 struct gl_texture_object
*texObj
;
644 struct gl_texture_image
*texImage
;
645 struct radeon_renderbuffer
*rb
;
646 radeon_texture_image
*rImage
;
647 radeonContextPtr radeon
;
648 r100ContextPtr rmesa
;
649 struct radeon_framebuffer
*rfb
;
653 target
= GL_TEXTURE_RECTANGLE_ARB
;
655 radeon
= pDRICtx
->driverPrivate
;
656 rmesa
= pDRICtx
->driverPrivate
;
658 rfb
= dPriv
->driverPrivate
;
659 texUnit
= &radeon
->glCtx
->Texture
.Unit
[radeon
->glCtx
->Texture
.CurrentUnit
];
660 texObj
= _mesa_select_tex_object(radeon
->glCtx
, texUnit
, target
);
661 texImage
= _mesa_get_tex_image(radeon
->glCtx
, texObj
, target
, 0);
663 rImage
= get_radeon_texture_image(texImage
);
664 t
= radeon_tex_obj(texObj
);
669 radeon_update_renderbuffers(pDRICtx
, dPriv
);
670 /* back & depth buffer are useless free them right away */
671 rb
= (void*)rfb
->base
.Attachment
[BUFFER_DEPTH
].Renderbuffer
;
673 radeon_bo_unref(rb
->bo
);
676 rb
= (void*)rfb
->base
.Attachment
[BUFFER_BACK_LEFT
].Renderbuffer
;
678 radeon_bo_unref(rb
->bo
);
681 rb
= (void*)rfb
->base
.Attachment
[BUFFER_FRONT_LEFT
].Renderbuffer
;
682 if (rb
->bo
== NULL
) {
683 /* Failed to BO for the buffer */
687 _mesa_lock_texture(radeon
->glCtx
, texObj
);
689 radeon_bo_unref(t
->bo
);
693 radeon_bo_unref(rImage
->bo
);
697 radeon_miptree_unreference(t
->mt
);
701 radeon_miptree_unreference(rImage
->mt
);
704 fprintf(stderr
,"settexbuf %d %dx%d@%d\n", rb
->pitch
, rb
->width
, rb
->height
, rb
->cpp
);
705 _mesa_init_teximage_fields(radeon
->glCtx
, target
, texImage
,
706 rb
->width
, rb
->height
, 1, 0, rb
->cpp
);
707 texImage
->TexFormat
= &_mesa_texformat_rgba8888_rev
;
709 radeon_bo_ref(rImage
->bo
);
711 radeon_bo_ref(t
->bo
);
713 t
->image_override
= GL_TRUE
;
714 t
->override_offset
= 0;
715 t
->pp_txpitch
&= (1 << 13) -1;
716 pitch_val
= rb
->pitch
;
719 t
->pp_txformat
= tx_table
[MESA_FORMAT_ARGB8888
].format
;
720 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_ARGB8888
].filter
;
725 t
->pp_txformat
= tx_table
[MESA_FORMAT_RGB888
].format
;
726 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_RGB888
].filter
;
730 t
->pp_txformat
= tx_table
[MESA_FORMAT_RGB565
].format
;
731 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_RGB565
].filter
;
735 t
->pp_txsize
= ((rb
->width
- 1) << RADEON_TEX_USIZE_SHIFT
)
736 | ((rb
->height
- 1) << RADEON_TEX_VSIZE_SHIFT
);
737 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
738 t
->pp_txpitch
= pitch_val
;
741 t
->validated
= GL_TRUE
;
742 _mesa_unlock_texture(radeon
->glCtx
, texObj
);
746 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
747 RADEON_MIN_FILTER_MASK | \
748 RADEON_MAG_FILTER_MASK | \
749 RADEON_MAX_ANISO_MASK | \
750 RADEON_YUV_TO_RGB | \
751 RADEON_YUV_TEMPERATURE_MASK | \
752 RADEON_CLAMP_S_MASK | \
753 RADEON_CLAMP_T_MASK | \
754 RADEON_BORDER_MODE_D3D )
756 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
757 RADEON_TXFORMAT_HEIGHT_MASK | \
758 RADEON_TXFORMAT_FORMAT_MASK | \
759 RADEON_TXFORMAT_F5_WIDTH_MASK | \
760 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
761 RADEON_TXFORMAT_ALPHA_IN_MAP | \
762 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
763 RADEON_TXFORMAT_NON_POWER2)
766 static void disable_tex_obj_state( r100ContextPtr rmesa
,
769 /* do not use RADEON_DB_STATE to avoid stale texture caches */
770 uint32_t *cmd
= &rmesa
->hw
.tex
[unit
].cmd
[TEX_CMD_0
];
771 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
772 GLuint
*txr_cmd
= RADEON_DB_STATE( txr
[unit
] );
774 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
776 RADEON_STATECHANGE( rmesa
, tcl
);
777 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_ST_BIT(unit
) |
780 if (rmesa
->radeon
.TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
781 TCL_FALLBACK( rmesa
->radeon
.glCtx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
782 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
785 if (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE
) {
786 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
787 cubic_map bit on unit 2 when the unit is disabled, otherwise every
788 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
789 units, better be safe than sorry though).*/
790 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
791 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE
;
795 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
796 GLuint tmp
= rmesa
->TexGenEnabled
;
798 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
799 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
800 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
801 rmesa
->TexGenNeedNormals
[unit
] = 0;
802 rmesa
->TexGenEnabled
|=
803 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
805 if (tmp
!= rmesa
->TexGenEnabled
) {
806 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
807 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
812 static void import_tex_obj_state( r100ContextPtr rmesa
,
814 radeonTexObjPtr texobj
)
816 /* do not use RADEON_DB_STATE to avoid stale texture caches */
817 uint32_t *cmd
= &rmesa
->hw
.tex
[unit
].cmd
[TEX_CMD_0
];
818 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
820 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
822 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
823 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
824 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
825 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
826 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
828 if (texobj
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
829 GLuint
*txr_cmd
= RADEON_DB_STATE( txr
[unit
] );
830 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
831 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
832 RADEON_DB_STATECHANGE( rmesa
, &rmesa
->hw
.txr
[unit
] );
833 se_coord_fmt
|= RADEON_VTX_ST0_NONPARAMETRIC
<< unit
;
836 se_coord_fmt
&= ~(RADEON_VTX_ST0_NONPARAMETRIC
<< unit
);
838 if (texobj
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
839 uint32_t *cube_cmd
= &rmesa
->hw
.cube
[unit
].cmd
[CUBE_CMD_0
];
841 RADEON_STATECHANGE( rmesa
, cube
[unit
] );
842 cube_cmd
[CUBE_PP_CUBIC_FACES
] = texobj
->pp_cubic_faces
;
843 /* state filled out in the cube_emit */
847 if (se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
]) {
848 RADEON_STATECHANGE( rmesa
, set
);
849 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
852 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
856 static void set_texgen_matrix( r100ContextPtr rmesa
,
858 const GLfloat
*s_plane
,
859 const GLfloat
*t_plane
,
860 const GLfloat
*r_plane
,
861 const GLfloat
*q_plane
)
863 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
864 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
865 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
866 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
868 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
869 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
870 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
871 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
873 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
874 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
875 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
876 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
878 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
879 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
880 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
881 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
883 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
884 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
887 /* Returns GL_FALSE if fallback required.
889 static GLboolean
radeon_validate_texgen( GLcontext
*ctx
, GLuint unit
)
891 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
892 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
893 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
894 GLuint tmp
= rmesa
->TexGenEnabled
;
895 static const GLfloat reflect
[16] = {
901 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
902 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
903 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
904 rmesa
->TexGenNeedNormals
[unit
] = 0;
906 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
907 /* Disabled, no fallback:
909 rmesa
->TexGenEnabled
|=
910 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
913 /* the r100 cannot do texgen for some coords and not for others
914 * we do not detect such cases (certainly can't do it here) and just
915 * ASSUME that when S and T are texgen enabled we do not need other
916 * non-texgen enabled coords, no matter if the R and Q bits are texgen
917 * enabled. Still check for mixed mode texgen for all coords.
919 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
920 (texUnit
->TexGenEnabled
& T_BIT
) &&
921 (texUnit
->GenModeS
== texUnit
->GenModeT
) ) {
922 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
923 (texUnit
->GenModeS
!= texUnit
->GenModeR
)) ||
924 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
925 (texUnit
->GenModeS
!= texUnit
->GenModeQ
)) ) {
926 /* Mixed modes, fallback:
928 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
929 fprintf(stderr
, "fallback mixed texgen\n");
932 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
935 /* some texgen mode not including both S and T bits */
936 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
937 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
941 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
942 /* need this here for vtxfmt presumably. Argh we need to set
943 this from way too many places, would be much easier if we could leave
944 tcl q coord always enabled as on r200) */
945 RADEON_STATECHANGE( rmesa
, tcl
);
946 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_Q_BIT(unit
);
949 switch (texUnit
->GenModeS
) {
950 case GL_OBJECT_LINEAR
:
951 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
952 set_texgen_matrix( rmesa
, unit
,
953 texUnit
->ObjectPlaneS
,
954 texUnit
->ObjectPlaneT
,
955 texUnit
->ObjectPlaneR
,
956 texUnit
->ObjectPlaneQ
);
960 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
961 set_texgen_matrix( rmesa
, unit
,
968 case GL_REFLECTION_MAP_NV
:
969 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
970 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
971 /* TODO: unknown if this is needed/correct */
972 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
973 reflect
+ 8, reflect
+ 12 );
976 case GL_NORMAL_MAP_NV
:
977 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
978 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
982 /* the mode which everyone uses :-( */
984 /* Unsupported mode, fallback:
986 if (RADEON_DEBUG
& DEBUG_FALLBACKS
)
987 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
991 if (tmp
!= rmesa
->TexGenEnabled
) {
992 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
999 * Compute the cached hardware register values for the given texture object.
1001 * \param rmesa Context pointer
1002 * \param t the r300 texture object
1004 static GLboolean
setup_hardware_state(r100ContextPtr rmesa
, radeonTexObj
*t
, int unit
)
1006 const struct gl_texture_image
*firstImage
;
1007 GLint log2Width
, log2Height
, log2Depth
, texelBytes
;
1009 if ( t
->image_override
) {
1013 firstImage
= t
->base
.Image
[0][t
->mt
->firstLevel
];
1015 if (firstImage
->Border
> 0) {
1016 fprintf(stderr
, "%s: border\n", __FUNCTION__
);
1020 log2Width
= firstImage
->WidthLog2
;
1021 log2Height
= firstImage
->HeightLog2
;
1022 log2Depth
= firstImage
->DepthLog2
;
1023 texelBytes
= firstImage
->TexFormat
->TexelBytes
;
1025 if (!t
->image_override
) {
1026 if (VALID_FORMAT(firstImage
->TexFormat
->MesaFormat
)) {
1027 const struct tx_table
*table
= tx_table
;
1029 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
1030 RADEON_TXFORMAT_ALPHA_IN_MAP
);
1031 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
1033 t
->pp_txformat
|= table
[ firstImage
->TexFormat
->MesaFormat
].format
;
1034 t
->pp_txfilter
|= table
[ firstImage
->TexFormat
->MesaFormat
].filter
;
1036 _mesa_problem(NULL
, "unexpected texture format in %s",
1042 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
1043 t
->pp_txfilter
|= (t
->mt
->lastLevel
- t
->mt
->firstLevel
) << RADEON_MAX_MIP_LEVEL_SHIFT
;
1045 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
1046 RADEON_TXFORMAT_HEIGHT_MASK
|
1047 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
1048 RADEON_TXFORMAT_F5_WIDTH_MASK
|
1049 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
1050 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
1051 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
1055 if (t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
1056 ASSERT(log2Width
== log2Height
);
1057 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_F5_WIDTH_SHIFT
) |
1058 (log2Height
<< RADEON_TXFORMAT_F5_HEIGHT_SHIFT
) |
1059 /* don't think we need this bit, if it exists at all - fglrx does not set it */
1060 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE
));
1061 t
->pp_cubic_faces
= ((log2Width
<< RADEON_FACE_WIDTH_1_SHIFT
) |
1062 (log2Height
<< RADEON_FACE_HEIGHT_1_SHIFT
) |
1063 (log2Width
<< RADEON_FACE_WIDTH_2_SHIFT
) |
1064 (log2Height
<< RADEON_FACE_HEIGHT_2_SHIFT
) |
1065 (log2Width
<< RADEON_FACE_WIDTH_3_SHIFT
) |
1066 (log2Height
<< RADEON_FACE_HEIGHT_3_SHIFT
) |
1067 (log2Width
<< RADEON_FACE_WIDTH_4_SHIFT
) |
1068 (log2Height
<< RADEON_FACE_HEIGHT_4_SHIFT
));
1071 t
->pp_txsize
= (((firstImage
->Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
1072 | ((firstImage
->Height
- 1) << RADEON_TEX_VSIZE_SHIFT
));
1074 if ( !t
->image_override
) {
1075 if (firstImage
->IsCompressed
)
1076 t
->pp_txpitch
= (firstImage
->Width
+ 63) & ~(63);
1078 t
->pp_txpitch
= ((firstImage
->Width
* texelBytes
) + 63) & ~(63);
1079 t
->pp_txpitch
-= 32;
1082 if (t
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
1083 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
1089 static GLboolean
radeon_validate_texture(GLcontext
*ctx
, struct gl_texture_object
*texObj
, int unit
)
1091 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1092 radeonTexObj
*t
= radeon_tex_obj(texObj
);
1095 if (!radeon_validate_texture_miptree(ctx
, texObj
))
1098 ret
= setup_hardware_state(rmesa
, t
, unit
);
1099 if (ret
== GL_FALSE
)
1102 /* yuv conversion only works in first unit */
1103 if (unit
!= 0 && (t
->pp_txfilter
& RADEON_YUV_TO_RGB
))
1106 RADEON_STATECHANGE( rmesa
, ctx
);
1107 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1108 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1110 RADEON_STATECHANGE( rmesa
, tcl
);
1111 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_ST_BIT(unit
);
1113 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1115 import_tex_obj_state( rmesa
, unit
, t
);
1117 if (rmesa
->recheck_texgen
[unit
]) {
1118 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1119 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1120 rmesa
->recheck_texgen
[unit
] = 0;
1121 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
1124 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1127 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1129 t
->validated
= GL_TRUE
;
1130 return !t
->border_fallback
;
1133 static GLboolean
radeonUpdateTextureUnit( GLcontext
*ctx
, int unit
)
1135 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1136 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
1139 if (ctx
->Texture
.Unit
[unit
]._ReallyEnabled
& TEXTURE_3D_BIT
) {
1143 if (!ctx
->Texture
.Unit
[unit
]._ReallyEnabled
) {
1144 /* disable the unit */
1145 disable_tex_obj_state(rmesa
, unit
);
1149 if (!radeon_validate_texture(ctx
, ctx
->Texture
.Unit
[unit
]._Current
, unit
)) {
1151 "failed to validate texture for unit %d.\n",
1153 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1156 rmesa
->state
.texture
.unit
[unit
].texobj
= radeon_tex_obj(ctx
->Texture
.Unit
[unit
]._Current
);
1160 void radeonUpdateTextureState( GLcontext
*ctx
)
1162 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1165 /* set the ctx all textures off */
1166 RADEON_STATECHANGE( rmesa
, ctx
);
1167 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~((RADEON_TEX_ENABLE_MASK
) | (RADEON_TEX_BLEND_ENABLE_MASK
));
1169 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1170 radeonUpdateTextureUnit( ctx
, 1 ) &&
1171 radeonUpdateTextureUnit( ctx
, 2 ));
1173 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1175 if (rmesa
->radeon
.TclFallback
)
1176 radeonChooseVertexState( ctx
);