1 /**************************************************************************
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 **************************************************************************/
32 * Kevin E. Martin <martin@valinux.com>
33 * Gareth Hughes <gareth@valinux.com>
36 #include "main/glheader.h"
37 #include "main/imports.h"
38 #include "main/colormac.h"
39 #include "main/context.h"
40 #include "main/macros.h"
41 #include "main/teximage.h"
42 #include "main/texstate.h"
43 #include "main/texobj.h"
44 #include "main/enums.h"
45 #include "main/samplerobj.h"
47 #include "radeon_context.h"
48 #include "radeon_mipmap_tree.h"
49 #include "radeon_state.h"
50 #include "radeon_ioctl.h"
51 #include "radeon_swtcl.h"
52 #include "radeon_tex.h"
53 #include "radeon_tcl.h"
56 #define VALID_FORMAT(f) ( ((f) <= MESA_FORMAT_RGBA_DXT5) \
57 && (tx_table[f].format != 0xffffffff) )
59 /* ================================================================
60 * Texture combine functions
63 /* GL_ARB_texture_env_combine support
66 /* The color tables have combine functions for GL_SRC_COLOR,
67 * GL_ONE_MINUS_SRC_COLOR, GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
69 static GLuint radeon_texture_color
[][RADEON_MAX_TEXTURE_UNITS
] =
72 RADEON_COLOR_ARG_A_T0_COLOR
,
73 RADEON_COLOR_ARG_A_T1_COLOR
,
74 RADEON_COLOR_ARG_A_T2_COLOR
77 RADEON_COLOR_ARG_A_T0_COLOR
| RADEON_COMP_ARG_A
,
78 RADEON_COLOR_ARG_A_T1_COLOR
| RADEON_COMP_ARG_A
,
79 RADEON_COLOR_ARG_A_T2_COLOR
| RADEON_COMP_ARG_A
82 RADEON_COLOR_ARG_A_T0_ALPHA
,
83 RADEON_COLOR_ARG_A_T1_ALPHA
,
84 RADEON_COLOR_ARG_A_T2_ALPHA
87 RADEON_COLOR_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
88 RADEON_COLOR_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
89 RADEON_COLOR_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
93 static GLuint radeon_tfactor_color
[] =
95 RADEON_COLOR_ARG_A_TFACTOR_COLOR
,
96 RADEON_COLOR_ARG_A_TFACTOR_COLOR
| RADEON_COMP_ARG_A
,
97 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
,
98 RADEON_COLOR_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
101 static GLuint radeon_primary_color
[] =
103 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
,
104 RADEON_COLOR_ARG_A_DIFFUSE_COLOR
| RADEON_COMP_ARG_A
,
105 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
,
106 RADEON_COLOR_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
109 static GLuint radeon_previous_color
[] =
111 RADEON_COLOR_ARG_A_CURRENT_COLOR
,
112 RADEON_COLOR_ARG_A_CURRENT_COLOR
| RADEON_COMP_ARG_A
,
113 RADEON_COLOR_ARG_A_CURRENT_ALPHA
,
114 RADEON_COLOR_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
117 /* GL_ZERO table - indices 0-3
118 * GL_ONE table - indices 1-4
120 static GLuint radeon_zero_color
[] =
122 RADEON_COLOR_ARG_A_ZERO
,
123 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
124 RADEON_COLOR_ARG_A_ZERO
,
125 RADEON_COLOR_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
126 RADEON_COLOR_ARG_A_ZERO
130 /* The alpha tables only have GL_SRC_ALPHA and GL_ONE_MINUS_SRC_ALPHA.
132 static GLuint radeon_texture_alpha
[][RADEON_MAX_TEXTURE_UNITS
] =
135 RADEON_ALPHA_ARG_A_T0_ALPHA
,
136 RADEON_ALPHA_ARG_A_T1_ALPHA
,
137 RADEON_ALPHA_ARG_A_T2_ALPHA
140 RADEON_ALPHA_ARG_A_T0_ALPHA
| RADEON_COMP_ARG_A
,
141 RADEON_ALPHA_ARG_A_T1_ALPHA
| RADEON_COMP_ARG_A
,
142 RADEON_ALPHA_ARG_A_T2_ALPHA
| RADEON_COMP_ARG_A
146 static GLuint radeon_tfactor_alpha
[] =
148 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
,
149 RADEON_ALPHA_ARG_A_TFACTOR_ALPHA
| RADEON_COMP_ARG_A
152 static GLuint radeon_primary_alpha
[] =
154 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
,
155 RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA
| RADEON_COMP_ARG_A
158 static GLuint radeon_previous_alpha
[] =
160 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
,
161 RADEON_ALPHA_ARG_A_CURRENT_ALPHA
| RADEON_COMP_ARG_A
164 /* GL_ZERO table - indices 0-1
165 * GL_ONE table - indices 1-2
167 static GLuint radeon_zero_alpha
[] =
169 RADEON_ALPHA_ARG_A_ZERO
,
170 RADEON_ALPHA_ARG_A_ZERO
| RADEON_COMP_ARG_A
,
171 RADEON_ALPHA_ARG_A_ZERO
175 /* Extract the arg from slot A, shift it into the correct argument slot
176 * and set the corresponding complement bit.
178 #define RADEON_COLOR_ARG( n, arg ) \
181 ((color_arg[n] & RADEON_COLOR_ARG_MASK) \
182 << RADEON_COLOR_ARG_##arg##_SHIFT); \
184 ((color_arg[n] >> RADEON_COMP_ARG_SHIFT) \
185 << RADEON_COMP_ARG_##arg##_SHIFT); \
188 #define RADEON_ALPHA_ARG( n, arg ) \
191 ((alpha_arg[n] & RADEON_ALPHA_ARG_MASK) \
192 << RADEON_ALPHA_ARG_##arg##_SHIFT); \
194 ((alpha_arg[n] >> RADEON_COMP_ARG_SHIFT) \
195 << RADEON_COMP_ARG_##arg##_SHIFT); \
199 /* ================================================================
200 * Texture unit state management
203 static GLboolean
radeonUpdateTextureEnv( struct gl_context
*ctx
, int unit
)
205 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
206 const struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
207 GLuint color_combine
, alpha_combine
;
208 const GLuint color_combine0
= RADEON_COLOR_ARG_A_ZERO
| RADEON_COLOR_ARG_B_ZERO
209 | RADEON_COLOR_ARG_C_CURRENT_COLOR
| RADEON_BLEND_CTL_ADD
210 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
211 const GLuint alpha_combine0
= RADEON_ALPHA_ARG_A_ZERO
| RADEON_ALPHA_ARG_B_ZERO
212 | RADEON_ALPHA_ARG_C_CURRENT_ALPHA
| RADEON_BLEND_CTL_ADD
213 | RADEON_SCALE_1X
| RADEON_CLAMP_TX
;
216 if ( RADEON_DEBUG
& RADEON_TEXTURE
) {
217 fprintf( stderr
, "%s( %p, %d )\n", __func__
, (void *)ctx
, unit
);
220 /* Set the texture environment state. Isn't this nice and clean?
221 * The chip will automagically set the texture alpha to 0xff when
222 * the texture format does not include an alpha component. This
223 * reduces the amount of special-casing we have to do, alpha-only
224 * textures being a notable exception. Doesn't work for luminance
225 * textures realized with I8 and ALPHA_IN_MAP not set neither (on r100).
227 /* Don't cache these results.
229 rmesa
->state
.texture
.unit
[unit
].format
= 0;
230 rmesa
->state
.texture
.unit
[unit
].envMode
= 0;
232 if ( !texUnit
->_Current
) {
233 color_combine
= color_combine0
;
234 alpha_combine
= alpha_combine0
;
237 GLuint color_arg
[3], alpha_arg
[3];
239 const GLuint numColorArgs
= texUnit
->_CurrentCombine
->_NumArgsRGB
;
240 const GLuint numAlphaArgs
= texUnit
->_CurrentCombine
->_NumArgsA
;
241 GLuint RGBshift
= texUnit
->_CurrentCombine
->ScaleShiftRGB
;
242 GLuint Ashift
= texUnit
->_CurrentCombine
->ScaleShiftA
;
246 * Extract the color and alpha combine function arguments.
248 for ( i
= 0 ; i
< numColorArgs
; i
++ ) {
249 const GLint op
= texUnit
->_CurrentCombine
->OperandRGB
[i
] - GL_SRC_COLOR
;
250 const GLuint srcRGBi
= texUnit
->_CurrentCombine
->SourceRGB
[i
];
255 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
256 color_arg
[i
] = radeon_zero_color
[op
];
258 color_arg
[i
] = radeon_texture_color
[op
][unit
];
261 color_arg
[i
] = radeon_tfactor_color
[op
];
263 case GL_PRIMARY_COLOR
:
264 color_arg
[i
] = radeon_primary_color
[op
];
267 color_arg
[i
] = radeon_previous_color
[op
];
270 color_arg
[i
] = radeon_zero_color
[op
];
273 color_arg
[i
] = radeon_zero_color
[op
+1];
278 GLuint txunit
= srcRGBi
- GL_TEXTURE0
;
279 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_ALPHA
)
280 color_arg
[i
] = radeon_zero_color
[op
];
282 /* implement ogl 1.4/1.5 core spec here, not specification of
283 * GL_ARB_texture_env_crossbar (which would require disabling blending
284 * instead of undefined results when referencing not enabled texunit) */
285 color_arg
[i
] = radeon_texture_color
[op
][txunit
];
293 for ( i
= 0 ; i
< numAlphaArgs
; i
++ ) {
294 const GLint op
= texUnit
->_CurrentCombine
->OperandA
[i
] - GL_SRC_ALPHA
;
295 const GLuint srcAi
= texUnit
->_CurrentCombine
->SourceA
[i
];
300 if (texUnit
->_Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
301 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
303 alpha_arg
[i
] = radeon_texture_alpha
[op
][unit
];
306 alpha_arg
[i
] = radeon_tfactor_alpha
[op
];
308 case GL_PRIMARY_COLOR
:
309 alpha_arg
[i
] = radeon_primary_alpha
[op
];
312 alpha_arg
[i
] = radeon_previous_alpha
[op
];
315 alpha_arg
[i
] = radeon_zero_alpha
[op
];
318 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
323 GLuint txunit
= srcAi
- GL_TEXTURE0
;
324 if (ctx
->Texture
.Unit
[txunit
]._Current
->Image
[0][0]->_BaseFormat
== GL_LUMINANCE
)
325 alpha_arg
[i
] = radeon_zero_alpha
[op
+1];
327 alpha_arg
[i
] = radeon_texture_alpha
[op
][txunit
];
336 * Build up the color and alpha combine functions.
338 switch ( texUnit
->_CurrentCombine
->ModeRGB
) {
340 color_combine
= (RADEON_COLOR_ARG_A_ZERO
|
341 RADEON_COLOR_ARG_B_ZERO
|
342 RADEON_BLEND_CTL_ADD
|
344 RADEON_COLOR_ARG( 0, C
);
347 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
348 RADEON_BLEND_CTL_ADD
|
350 RADEON_COLOR_ARG( 0, A
);
351 RADEON_COLOR_ARG( 1, B
);
354 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
356 RADEON_BLEND_CTL_ADD
|
358 RADEON_COLOR_ARG( 0, A
);
359 RADEON_COLOR_ARG( 1, C
);
362 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
364 RADEON_BLEND_CTL_ADDSIGNED
|
366 RADEON_COLOR_ARG( 0, A
);
367 RADEON_COLOR_ARG( 1, C
);
370 color_combine
= (RADEON_COLOR_ARG_B_ZERO
|
372 RADEON_BLEND_CTL_SUBTRACT
|
374 RADEON_COLOR_ARG( 0, A
);
375 RADEON_COLOR_ARG( 1, C
);
378 color_combine
= (RADEON_BLEND_CTL_BLEND
|
380 RADEON_COLOR_ARG( 0, B
);
381 RADEON_COLOR_ARG( 1, A
);
382 RADEON_COLOR_ARG( 2, C
);
385 case GL_DOT3_RGB_EXT
:
386 case GL_DOT3_RGBA_EXT
:
387 /* The EXT version of the DOT3 extension does not support the
388 * scale factor, but the ARB version (and the version in OpenGL
396 /* The R100 / RV200 only support a 1X multiplier in hardware
399 if ( RGBshift
!= (RADEON_SCALE_1X
>> RADEON_SCALE_SHIFT
) ) {
404 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA_EXT
)
405 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGBA
) ) {
406 /* is it necessary to set this or will it be ignored anyway? */
410 color_combine
= (RADEON_COLOR_ARG_C_ZERO
|
411 RADEON_BLEND_CTL_DOT3
|
413 RADEON_COLOR_ARG( 0, A
);
414 RADEON_COLOR_ARG( 1, B
);
417 case GL_MODULATE_ADD_ATI
:
418 color_combine
= (RADEON_BLEND_CTL_ADD
|
420 RADEON_COLOR_ARG( 0, A
);
421 RADEON_COLOR_ARG( 1, C
);
422 RADEON_COLOR_ARG( 2, B
);
424 case GL_MODULATE_SIGNED_ADD_ATI
:
425 color_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
427 RADEON_COLOR_ARG( 0, A
);
428 RADEON_COLOR_ARG( 1, C
);
429 RADEON_COLOR_ARG( 2, B
);
431 case GL_MODULATE_SUBTRACT_ATI
:
432 color_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
434 RADEON_COLOR_ARG( 0, A
);
435 RADEON_COLOR_ARG( 1, C
);
436 RADEON_COLOR_ARG( 2, B
);
442 switch ( texUnit
->_CurrentCombine
->ModeA
) {
444 alpha_combine
= (RADEON_ALPHA_ARG_A_ZERO
|
445 RADEON_ALPHA_ARG_B_ZERO
|
446 RADEON_BLEND_CTL_ADD
|
448 RADEON_ALPHA_ARG( 0, C
);
451 alpha_combine
= (RADEON_ALPHA_ARG_C_ZERO
|
452 RADEON_BLEND_CTL_ADD
|
454 RADEON_ALPHA_ARG( 0, A
);
455 RADEON_ALPHA_ARG( 1, B
);
458 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
460 RADEON_BLEND_CTL_ADD
|
462 RADEON_ALPHA_ARG( 0, A
);
463 RADEON_ALPHA_ARG( 1, C
);
466 alpha_combine
= (RADEON_ALPHA_ARG_B_ZERO
|
468 RADEON_BLEND_CTL_ADDSIGNED
|
470 RADEON_ALPHA_ARG( 0, A
);
471 RADEON_ALPHA_ARG( 1, C
);
474 alpha_combine
= (RADEON_COLOR_ARG_B_ZERO
|
476 RADEON_BLEND_CTL_SUBTRACT
|
478 RADEON_ALPHA_ARG( 0, A
);
479 RADEON_ALPHA_ARG( 1, C
);
482 alpha_combine
= (RADEON_BLEND_CTL_BLEND
|
484 RADEON_ALPHA_ARG( 0, B
);
485 RADEON_ALPHA_ARG( 1, A
);
486 RADEON_ALPHA_ARG( 2, C
);
489 case GL_MODULATE_ADD_ATI
:
490 alpha_combine
= (RADEON_BLEND_CTL_ADD
|
492 RADEON_ALPHA_ARG( 0, A
);
493 RADEON_ALPHA_ARG( 1, C
);
494 RADEON_ALPHA_ARG( 2, B
);
496 case GL_MODULATE_SIGNED_ADD_ATI
:
497 alpha_combine
= (RADEON_BLEND_CTL_ADDSIGNED
|
499 RADEON_ALPHA_ARG( 0, A
);
500 RADEON_ALPHA_ARG( 1, C
);
501 RADEON_ALPHA_ARG( 2, B
);
503 case GL_MODULATE_SUBTRACT_ATI
:
504 alpha_combine
= (RADEON_BLEND_CTL_SUBTRACT
|
506 RADEON_ALPHA_ARG( 0, A
);
507 RADEON_ALPHA_ARG( 1, C
);
508 RADEON_ALPHA_ARG( 2, B
);
514 if ( (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB_EXT
)
515 || (texUnit
->_CurrentCombine
->ModeRGB
== GL_DOT3_RGB
) ) {
516 alpha_combine
|= RADEON_DOT_ALPHA_DONT_REPLICATE
;
520 * Apply the scale factor.
522 color_combine
|= (RGBshift
<< RADEON_SCALE_SHIFT
);
523 alpha_combine
|= (Ashift
<< RADEON_SCALE_SHIFT
);
529 if ( rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] != color_combine
||
530 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] != alpha_combine
) {
531 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
532 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXCBLEND
] = color_combine
;
533 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXABLEND
] = alpha_combine
;
539 void radeonSetTexBuffer2(__DRIcontext
*pDRICtx
, GLint target
, GLint texture_format
,
540 __DRIdrawable
*dPriv
)
542 struct gl_texture_object
*texObj
;
543 struct gl_texture_image
*texImage
;
544 struct radeon_renderbuffer
*rb
;
545 radeon_texture_image
*rImage
;
546 radeonContextPtr radeon
;
547 struct radeon_framebuffer
*rfb
;
550 mesa_format texFormat
;
552 radeon
= pDRICtx
->driverPrivate
;
554 rfb
= dPriv
->driverPrivate
;
555 texObj
= _mesa_get_current_tex_object(&radeon
->glCtx
, target
);
556 texImage
= _mesa_get_tex_image(&radeon
->glCtx
, texObj
, target
, 0);
558 rImage
= get_radeon_texture_image(texImage
);
559 t
= radeon_tex_obj(texObj
);
564 radeon_update_renderbuffers(pDRICtx
, dPriv
, GL_TRUE
);
565 rb
= rfb
->color_rb
[0];
566 if (rb
->bo
== NULL
) {
567 /* Failed to BO for the buffer */
571 _mesa_lock_texture(&radeon
->glCtx
, texObj
);
573 radeon_bo_unref(t
->bo
);
577 radeon_bo_unref(rImage
->bo
);
581 radeon_miptree_unreference(&t
->mt
);
582 radeon_miptree_unreference(&rImage
->mt
);
585 radeon_bo_ref(rImage
->bo
);
587 radeon_bo_ref(t
->bo
);
589 t
->image_override
= GL_TRUE
;
590 t
->override_offset
= 0;
593 if (texture_format
== __DRI_TEXTURE_FORMAT_RGB
) {
594 t
->pp_txformat
= tx_table
[MESA_FORMAT_BGR_UNORM8
].format
;
595 texFormat
= MESA_FORMAT_BGR_UNORM8
;
598 t
->pp_txformat
= tx_table
[MESA_FORMAT_B8G8R8A8_UNORM
].format
;
599 texFormat
= MESA_FORMAT_B8G8R8A8_UNORM
;
601 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_B8G8R8A8_UNORM
].filter
;
605 texFormat
= MESA_FORMAT_BGR_UNORM8
;
606 t
->pp_txformat
= tx_table
[MESA_FORMAT_BGR_UNORM8
].format
;
607 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_BGR_UNORM8
].filter
;
610 texFormat
= MESA_FORMAT_B5G6R5_UNORM
;
611 t
->pp_txformat
= tx_table
[MESA_FORMAT_B5G6R5_UNORM
].format
;
612 t
->pp_txfilter
|= tx_table
[MESA_FORMAT_B5G6R5_UNORM
].filter
;
616 _mesa_init_teximage_fields(&radeon
->glCtx
, texImage
,
617 rb
->base
.Base
.Width
, rb
->base
.Base
.Height
,
620 rImage
->base
.RowStride
= rb
->pitch
/ rb
->cpp
;
622 t
->pp_txpitch
&= (1 << 13) -1;
623 pitch_val
= rb
->pitch
;
625 t
->pp_txsize
= ((rb
->base
.Base
.Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
626 | ((rb
->base
.Base
.Height
- 1) << RADEON_TEX_VSIZE_SHIFT
);
627 if (target
== GL_TEXTURE_RECTANGLE_NV
) {
628 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
629 t
->pp_txpitch
= pitch_val
;
632 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
633 RADEON_TXFORMAT_HEIGHT_MASK
|
634 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
635 RADEON_TXFORMAT_F5_WIDTH_MASK
|
636 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
637 t
->pp_txformat
|= ((texImage
->WidthLog2
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
638 (texImage
->HeightLog2
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
640 t
->validated
= GL_TRUE
;
641 _mesa_unlock_texture(&radeon
->glCtx
, texObj
);
646 void radeonSetTexBuffer(__DRIcontext
*pDRICtx
, GLint target
, __DRIdrawable
*dPriv
)
648 radeonSetTexBuffer2(pDRICtx
, target
, __DRI_TEXTURE_FORMAT_RGBA
, dPriv
);
652 #define TEXOBJ_TXFILTER_MASK (RADEON_MAX_MIP_LEVEL_MASK | \
653 RADEON_MIN_FILTER_MASK | \
654 RADEON_MAG_FILTER_MASK | \
655 RADEON_MAX_ANISO_MASK | \
656 RADEON_YUV_TO_RGB | \
657 RADEON_YUV_TEMPERATURE_MASK | \
658 RADEON_CLAMP_S_MASK | \
659 RADEON_CLAMP_T_MASK | \
660 RADEON_BORDER_MODE_D3D )
662 #define TEXOBJ_TXFORMAT_MASK (RADEON_TXFORMAT_WIDTH_MASK | \
663 RADEON_TXFORMAT_HEIGHT_MASK | \
664 RADEON_TXFORMAT_FORMAT_MASK | \
665 RADEON_TXFORMAT_F5_WIDTH_MASK | \
666 RADEON_TXFORMAT_F5_HEIGHT_MASK | \
667 RADEON_TXFORMAT_ALPHA_IN_MAP | \
668 RADEON_TXFORMAT_CUBIC_MAP_ENABLE | \
669 RADEON_TXFORMAT_NON_POWER2)
672 static void disable_tex_obj_state( r100ContextPtr rmesa
,
675 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
677 RADEON_STATECHANGE( rmesa
, tcl
);
678 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] &= ~(RADEON_ST_BIT(unit
) |
681 if (rmesa
->radeon
.TclFallback
& (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
)) {
682 TCL_FALLBACK( &rmesa
->radeon
.glCtx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), GL_FALSE
);
683 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
686 if (rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] & RADEON_TXFORMAT_CUBIC_MAP_ENABLE
) {
687 /* this seems to be a genuine (r100 only?) hw bug. Need to remove the
688 cubic_map bit on unit 2 when the unit is disabled, otherwise every
689 2nd (2d) mipmap on unit 0 will be broken (may not be needed for other
690 units, better be safe than sorry though).*/
691 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
692 rmesa
->hw
.tex
[unit
].cmd
[TEX_PP_TXFORMAT
] &= ~RADEON_TXFORMAT_CUBIC_MAP_ENABLE
;
696 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
697 GLuint tmp
= rmesa
->TexGenEnabled
;
699 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<<unit
);
700 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<<unit
);
701 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<<inputshift
);
702 rmesa
->TexGenNeedNormals
[unit
] = 0;
703 rmesa
->TexGenEnabled
|=
704 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+unit
) << inputshift
;
706 if (tmp
!= rmesa
->TexGenEnabled
) {
707 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
708 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
713 static void import_tex_obj_state( r100ContextPtr rmesa
,
715 radeonTexObjPtr texobj
)
717 /* do not use RADEON_DB_STATE to avoid stale texture caches */
718 uint32_t *cmd
= &rmesa
->hw
.tex
[unit
].cmd
[TEX_CMD_0
];
719 GLuint se_coord_fmt
= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
];
721 RADEON_STATECHANGE( rmesa
, tex
[unit
] );
723 cmd
[TEX_PP_TXFILTER
] &= ~TEXOBJ_TXFILTER_MASK
;
724 cmd
[TEX_PP_TXFILTER
] |= texobj
->pp_txfilter
& TEXOBJ_TXFILTER_MASK
;
725 cmd
[TEX_PP_TXFORMAT
] &= ~TEXOBJ_TXFORMAT_MASK
;
726 cmd
[TEX_PP_TXFORMAT
] |= texobj
->pp_txformat
& TEXOBJ_TXFORMAT_MASK
;
727 cmd
[TEX_PP_BORDER_COLOR
] = texobj
->pp_border_color
;
729 if (texobj
->pp_txformat
& RADEON_TXFORMAT_NON_POWER2
) {
730 uint32_t *txr_cmd
= &rmesa
->hw
.txr
[unit
].cmd
[TXR_CMD_0
];
731 txr_cmd
[TXR_PP_TEX_SIZE
] = texobj
->pp_txsize
; /* NPOT only! */
732 txr_cmd
[TXR_PP_TEX_PITCH
] = texobj
->pp_txpitch
; /* NPOT only! */
733 RADEON_STATECHANGE( rmesa
, txr
[unit
] );
736 if (texobj
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
737 se_coord_fmt
|= RADEON_VTX_ST0_NONPARAMETRIC
<< unit
;
740 se_coord_fmt
&= ~(RADEON_VTX_ST0_NONPARAMETRIC
<< unit
);
742 if (texobj
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
743 uint32_t *cube_cmd
= &rmesa
->hw
.cube
[unit
].cmd
[CUBE_CMD_0
];
745 RADEON_STATECHANGE( rmesa
, cube
[unit
] );
746 cube_cmd
[CUBE_PP_CUBIC_FACES
] = texobj
->pp_cubic_faces
;
747 /* state filled out in the cube_emit */
751 if (se_coord_fmt
!= rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
]) {
752 RADEON_STATECHANGE( rmesa
, set
);
753 rmesa
->hw
.set
.cmd
[SET_SE_COORDFMT
] = se_coord_fmt
;
756 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
760 static void set_texgen_matrix( r100ContextPtr rmesa
,
762 const GLfloat
*s_plane
,
763 const GLfloat
*t_plane
,
764 const GLfloat
*r_plane
,
765 const GLfloat
*q_plane
)
767 rmesa
->TexGenMatrix
[unit
].m
[0] = s_plane
[0];
768 rmesa
->TexGenMatrix
[unit
].m
[4] = s_plane
[1];
769 rmesa
->TexGenMatrix
[unit
].m
[8] = s_plane
[2];
770 rmesa
->TexGenMatrix
[unit
].m
[12] = s_plane
[3];
772 rmesa
->TexGenMatrix
[unit
].m
[1] = t_plane
[0];
773 rmesa
->TexGenMatrix
[unit
].m
[5] = t_plane
[1];
774 rmesa
->TexGenMatrix
[unit
].m
[9] = t_plane
[2];
775 rmesa
->TexGenMatrix
[unit
].m
[13] = t_plane
[3];
777 rmesa
->TexGenMatrix
[unit
].m
[2] = r_plane
[0];
778 rmesa
->TexGenMatrix
[unit
].m
[6] = r_plane
[1];
779 rmesa
->TexGenMatrix
[unit
].m
[10] = r_plane
[2];
780 rmesa
->TexGenMatrix
[unit
].m
[14] = r_plane
[3];
782 rmesa
->TexGenMatrix
[unit
].m
[3] = q_plane
[0];
783 rmesa
->TexGenMatrix
[unit
].m
[7] = q_plane
[1];
784 rmesa
->TexGenMatrix
[unit
].m
[11] = q_plane
[2];
785 rmesa
->TexGenMatrix
[unit
].m
[15] = q_plane
[3];
787 rmesa
->TexGenEnabled
|= RADEON_TEXMAT_0_ENABLE
<< unit
;
788 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
791 /* Returns GL_FALSE if fallback required.
793 static GLboolean
radeon_validate_texgen( struct gl_context
*ctx
, GLuint unit
)
795 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
796 struct gl_texture_unit
*texUnit
= &ctx
->Texture
.Unit
[unit
];
797 GLuint inputshift
= RADEON_TEXGEN_0_INPUT_SHIFT
+ unit
*4;
798 GLuint tmp
= rmesa
->TexGenEnabled
;
799 static const GLfloat reflect
[16] = {
805 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
);
806 rmesa
->TexGenEnabled
&= ~(RADEON_TEXMAT_0_ENABLE
<< unit
);
807 rmesa
->TexGenEnabled
&= ~(RADEON_TEXGEN_INPUT_MASK
<< inputshift
);
808 rmesa
->TexGenNeedNormals
[unit
] = 0;
810 if ((texUnit
->TexGenEnabled
& (S_BIT
|T_BIT
|R_BIT
|Q_BIT
)) == 0) {
811 /* Disabled, no fallback:
813 rmesa
->TexGenEnabled
|=
814 (RADEON_TEXGEN_INPUT_TEXCOORD_0
+ unit
) << inputshift
;
817 /* the r100 cannot do texgen for some coords and not for others
818 * we do not detect such cases (certainly can't do it here) and just
819 * ASSUME that when S and T are texgen enabled we do not need other
820 * non-texgen enabled coords, no matter if the R and Q bits are texgen
821 * enabled. Still check for mixed mode texgen for all coords.
823 else if ( (texUnit
->TexGenEnabled
& S_BIT
) &&
824 (texUnit
->TexGenEnabled
& T_BIT
) &&
825 (texUnit
->GenS
.Mode
== texUnit
->GenT
.Mode
) ) {
826 if ( ((texUnit
->TexGenEnabled
& R_BIT
) &&
827 (texUnit
->GenS
.Mode
!= texUnit
->GenR
.Mode
)) ||
828 ((texUnit
->TexGenEnabled
& Q_BIT
) &&
829 (texUnit
->GenS
.Mode
!= texUnit
->GenQ
.Mode
)) ) {
830 /* Mixed modes, fallback:
832 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
833 fprintf(stderr
, "fallback mixed texgen\n");
836 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_TEXMAT_0_ENABLE
<< unit
;
839 /* some texgen mode not including both S and T bits */
840 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
841 fprintf(stderr
, "fallback mixed texgen/nontexgen\n");
845 if ((texUnit
->TexGenEnabled
& (R_BIT
| Q_BIT
)) != 0) {
846 /* need this here for vtxfmt presumably. Argh we need to set
847 this from way too many places, would be much easier if we could leave
848 tcl q coord always enabled as on r200) */
849 RADEON_STATECHANGE( rmesa
, tcl
);
850 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_Q_BIT(unit
);
853 switch (texUnit
->GenS
.Mode
) {
854 case GL_OBJECT_LINEAR
:
855 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_OBJ
<< inputshift
;
856 set_texgen_matrix( rmesa
, unit
,
857 texUnit
->GenS
.ObjectPlane
,
858 texUnit
->GenT
.ObjectPlane
,
859 texUnit
->GenR
.ObjectPlane
,
860 texUnit
->GenQ
.ObjectPlane
);
864 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE
<< inputshift
;
865 set_texgen_matrix( rmesa
, unit
,
866 texUnit
->GenS
.EyePlane
,
867 texUnit
->GenT
.EyePlane
,
868 texUnit
->GenR
.EyePlane
,
869 texUnit
->GenQ
.EyePlane
);
872 case GL_REFLECTION_MAP_NV
:
873 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
874 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_REFLECT
<< inputshift
;
875 /* TODO: unknown if this is needed/correct */
876 set_texgen_matrix( rmesa
, unit
, reflect
, reflect
+ 4,
877 reflect
+ 8, reflect
+ 12 );
880 case GL_NORMAL_MAP_NV
:
881 rmesa
->TexGenNeedNormals
[unit
] = GL_TRUE
;
882 rmesa
->TexGenEnabled
|= RADEON_TEXGEN_INPUT_EYE_NORMAL
<< inputshift
;
886 /* the mode which everyone uses :-( */
888 /* Unsupported mode, fallback:
890 if (RADEON_DEBUG
& RADEON_FALLBACKS
)
891 fprintf(stderr
, "fallback GL_SPHERE_MAP\n");
895 if (tmp
!= rmesa
->TexGenEnabled
) {
896 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
903 * Compute the cached hardware register values for the given texture object.
905 * \param rmesa Context pointer
906 * \param t the r300 texture object
908 static GLboolean
setup_hardware_state(r100ContextPtr rmesa
, radeonTexObj
*t
, int unit
)
910 const struct gl_texture_image
*firstImage
;
911 GLint log2Width
, log2Height
, texelBytes
;
917 firstImage
= t
->base
.Image
[0][t
->minLod
];
919 log2Width
= firstImage
->WidthLog2
;
920 log2Height
= firstImage
->HeightLog2
;
921 texelBytes
= _mesa_get_format_bytes(firstImage
->TexFormat
);
923 if (!t
->image_override
) {
924 if (VALID_FORMAT(firstImage
->TexFormat
)) {
925 const struct tx_table
*table
= tx_table
;
927 t
->pp_txformat
&= ~(RADEON_TXFORMAT_FORMAT_MASK
|
928 RADEON_TXFORMAT_ALPHA_IN_MAP
);
929 t
->pp_txfilter
&= ~RADEON_YUV_TO_RGB
;
931 t
->pp_txformat
|= table
[ firstImage
->TexFormat
].format
;
932 t
->pp_txfilter
|= table
[ firstImage
->TexFormat
].filter
;
934 _mesa_problem(NULL
, "unexpected texture format in %s",
940 t
->pp_txfilter
&= ~RADEON_MAX_MIP_LEVEL_MASK
;
941 t
->pp_txfilter
|= (t
->maxLod
- t
->minLod
) << RADEON_MAX_MIP_LEVEL_SHIFT
;
943 t
->pp_txformat
&= ~(RADEON_TXFORMAT_WIDTH_MASK
|
944 RADEON_TXFORMAT_HEIGHT_MASK
|
945 RADEON_TXFORMAT_CUBIC_MAP_ENABLE
|
946 RADEON_TXFORMAT_F5_WIDTH_MASK
|
947 RADEON_TXFORMAT_F5_HEIGHT_MASK
);
948 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_WIDTH_SHIFT
) |
949 (log2Height
<< RADEON_TXFORMAT_HEIGHT_SHIFT
));
953 if (t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) {
954 assert(log2Width
== log2Height
);
955 t
->pp_txformat
|= ((log2Width
<< RADEON_TXFORMAT_F5_WIDTH_SHIFT
) |
956 (log2Height
<< RADEON_TXFORMAT_F5_HEIGHT_SHIFT
) |
957 /* don't think we need this bit, if it exists at all - fglrx does not set it */
958 (RADEON_TXFORMAT_CUBIC_MAP_ENABLE
));
959 t
->pp_cubic_faces
= ((log2Width
<< RADEON_FACE_WIDTH_1_SHIFT
) |
960 (log2Height
<< RADEON_FACE_HEIGHT_1_SHIFT
) |
961 (log2Width
<< RADEON_FACE_WIDTH_2_SHIFT
) |
962 (log2Height
<< RADEON_FACE_HEIGHT_2_SHIFT
) |
963 (log2Width
<< RADEON_FACE_WIDTH_3_SHIFT
) |
964 (log2Height
<< RADEON_FACE_HEIGHT_3_SHIFT
) |
965 (log2Width
<< RADEON_FACE_WIDTH_4_SHIFT
) |
966 (log2Height
<< RADEON_FACE_HEIGHT_4_SHIFT
));
969 t
->pp_txsize
= (((firstImage
->Width
- 1) << RADEON_TEX_USIZE_SHIFT
)
970 | ((firstImage
->Height
- 1) << RADEON_TEX_VSIZE_SHIFT
));
972 if ( !t
->image_override
) {
973 if (_mesa_is_format_compressed(firstImage
->TexFormat
))
974 t
->pp_txpitch
= (firstImage
->Width
+ 63) & ~(63);
976 t
->pp_txpitch
= ((firstImage
->Width
* texelBytes
) + 63) & ~(63);
980 if (t
->base
.Target
== GL_TEXTURE_RECTANGLE_NV
) {
981 t
->pp_txformat
|= RADEON_TXFORMAT_NON_POWER2
;
987 static GLboolean
radeon_validate_texture(struct gl_context
*ctx
, struct gl_texture_object
*texObj
, int unit
)
989 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
990 radeonTexObj
*t
= radeon_tex_obj(texObj
);
993 if (!radeon_validate_texture_miptree(ctx
, _mesa_get_samplerobj(ctx
, unit
), texObj
))
996 ret
= setup_hardware_state(rmesa
, t
, unit
);
1000 /* yuv conversion only works in first unit */
1001 if (unit
!= 0 && (t
->pp_txfilter
& RADEON_YUV_TO_RGB
))
1004 RADEON_STATECHANGE( rmesa
, ctx
);
1005 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] |=
1006 (RADEON_TEX_0_ENABLE
| RADEON_TEX_BLEND_0_ENABLE
) << unit
;
1007 RADEON_STATECHANGE( rmesa
, tcl
);
1008 rmesa
->hw
.tcl
.cmd
[TCL_OUTPUT_VTXFMT
] |= RADEON_ST_BIT(unit
);
1010 rmesa
->recheck_texgen
[unit
] = GL_TRUE
;
1012 radeonTexUpdateParameters(ctx
, unit
);
1013 import_tex_obj_state( rmesa
, unit
, t
);
1015 if (rmesa
->recheck_texgen
[unit
]) {
1016 GLboolean fallback
= !radeon_validate_texgen( ctx
, unit
);
1017 TCL_FALLBACK( ctx
, (RADEON_TCL_FALLBACK_TEXGEN_0
<<unit
), fallback
);
1018 rmesa
->recheck_texgen
[unit
] = 0;
1019 rmesa
->radeon
.NewGLState
|= _NEW_TEXTURE_MATRIX
;
1022 if ( ! radeonUpdateTextureEnv( ctx
, unit
) ) {
1025 FALLBACK( rmesa
, RADEON_FALLBACK_BORDER_MODE
, t
->border_fallback
);
1027 t
->validated
= GL_TRUE
;
1028 return !t
->border_fallback
;
1031 static GLboolean
radeonUpdateTextureUnit( struct gl_context
*ctx
, int unit
)
1033 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1035 if (ctx
->Texture
.Unit
[unit
]._Current
&&
1036 ctx
->Texture
.Unit
[unit
]._Current
->Target
== GL_TEXTURE_3D
) {
1037 disable_tex_obj_state(rmesa
, unit
);
1038 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1042 if (!ctx
->Texture
.Unit
[unit
]._Current
) {
1043 /* disable the unit */
1044 disable_tex_obj_state(rmesa
, unit
);
1045 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1049 if (!radeon_validate_texture(ctx
, ctx
->Texture
.Unit
[unit
]._Current
, unit
)) {
1051 "failed to validate texture for unit %d.\n",
1053 rmesa
->state
.texture
.unit
[unit
].texobj
= NULL
;
1056 rmesa
->state
.texture
.unit
[unit
].texobj
= radeon_tex_obj(ctx
->Texture
.Unit
[unit
]._Current
);
1060 void radeonUpdateTextureState( struct gl_context
*ctx
)
1062 r100ContextPtr rmesa
= R100_CONTEXT(ctx
);
1065 /* set the ctx all textures off */
1066 RADEON_STATECHANGE( rmesa
, ctx
);
1067 rmesa
->hw
.ctx
.cmd
[CTX_PP_CNTL
] &= ~((RADEON_TEX_ENABLE_MASK
) | (RADEON_TEX_BLEND_ENABLE_MASK
));
1069 ok
= (radeonUpdateTextureUnit( ctx
, 0 ) &&
1070 radeonUpdateTextureUnit( ctx
, 1 ) &&
1071 radeonUpdateTextureUnit( ctx
, 2 ));
1073 FALLBACK( rmesa
, RADEON_FALLBACK_TEXTURE
, !ok
);
1075 if (rmesa
->radeon
.TclFallback
)
1076 radeonChooseVertexState( ctx
);