2 * Copyright (C) 2009 Maciej Cencora.
3 * Copyright (C) 2008 Nicolai Haehnle.
4 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
6 * The Weather Channel (TM) funded Tungsten Graphics to develop the
7 * initial release of the Radeon 8500 driver under the XFree86 license.
8 * This notice must be preserved.
10 * Permission is hereby granted, free of charge, to any person obtaining
11 * a copy of this software and associated documentation files (the
12 * "Software"), to deal in the Software without restriction, including
13 * without limitation the rights to use, copy, modify, merge, publish,
14 * distribute, sublicense, and/or sell copies of the Software, and to
15 * permit persons to whom the Software is furnished to do so, subject to
16 * the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial
20 * portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
25 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
26 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 #include "main/glheader.h"
33 #include "main/imports.h"
34 #include "main/context.h"
35 #include "main/convolve.h"
36 #include "main/enums.h"
37 #include "main/mipmap.h"
38 #include "main/texcompress.h"
39 #include "main/texstore.h"
40 #include "main/teximage.h"
41 #include "main/texobj.h"
43 #include "xmlpool.h" /* for symbolic values of enum-type options */
45 #include "radeon_common.h"
47 #include "radeon_mipmap_tree.h"
50 void copy_rows(void* dst
, GLuint dststride
, const void* src
, GLuint srcstride
,
51 GLuint numrows
, GLuint rowsize
)
53 assert(rowsize
<= dststride
);
54 assert(rowsize
<= srcstride
);
56 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
57 "%s dst %p, stride %u, src %p, stride %u, "
58 "numrows %u, rowsize %u.\n",
59 __func__
, dst
, dststride
,
63 if (rowsize
== srcstride
&& rowsize
== dststride
) {
64 memcpy(dst
, src
, numrows
*rowsize
);
67 for(i
= 0; i
< numrows
; ++i
) {
68 memcpy(dst
, src
, rowsize
);
77 * Allocate an empty texture image object.
79 struct gl_texture_image
*radeonNewTextureImage(GLcontext
*ctx
)
81 return CALLOC(sizeof(radeon_texture_image
));
85 * Free memory associated with this texture image.
87 void radeonFreeTexImageData(GLcontext
*ctx
, struct gl_texture_image
*timage
)
89 radeon_texture_image
* image
= get_radeon_texture_image(timage
);
92 radeon_miptree_unreference(&image
->mt
);
93 assert(!image
->base
.Data
);
95 _mesa_free_texture_image_data(ctx
, timage
);
98 radeon_bo_unref(image
->bo
);
102 _mesa_free_texmemory(timage
->Data
);
107 /* Set Data pointer and additional data for mapped texture image */
108 static void teximage_set_map_data(radeon_texture_image
*image
)
110 radeon_mipmap_level
*lvl
;
113 radeon_warning("%s(%p) Trying to set map data without miptree.\n",
119 lvl
= &image
->mt
->levels
[image
->mtlevel
];
121 image
->base
.Data
= image
->mt
->bo
->ptr
+ lvl
->faces
[image
->mtface
].offset
;
122 image
->base
.RowStride
= lvl
->rowstride
/ _mesa_get_format_bytes(image
->base
.TexFormat
);
127 * Map a single texture image for glTexImage and friends.
129 void radeon_teximage_map(radeon_texture_image
*image
, GLboolean write_enable
)
131 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
132 "%s(img %p), write_enable %s.\n",
134 write_enable
? "true": "false");
136 assert(!image
->base
.Data
);
138 radeon_bo_map(image
->mt
->bo
, write_enable
);
139 teximage_set_map_data(image
);
144 void radeon_teximage_unmap(radeon_texture_image
*image
)
146 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
150 assert(image
->base
.Data
);
152 image
->base
.Data
= 0;
153 radeon_bo_unmap(image
->mt
->bo
);
157 static void map_override(GLcontext
*ctx
, radeonTexObj
*t
)
159 radeon_texture_image
*img
= get_radeon_texture_image(t
->base
.Image
[0][0]);
161 radeon_bo_map(t
->bo
, GL_FALSE
);
163 img
->base
.Data
= t
->bo
->ptr
;
166 static void unmap_override(GLcontext
*ctx
, radeonTexObj
*t
)
168 radeon_texture_image
*img
= get_radeon_texture_image(t
->base
.Image
[0][0]);
170 radeon_bo_unmap(t
->bo
);
172 img
->base
.Data
= NULL
;
176 * Map a validated texture for reading during software rendering.
178 void radeonMapTexture(GLcontext
*ctx
, struct gl_texture_object
*texObj
)
180 radeonTexObj
* t
= radeon_tex_obj(texObj
);
183 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
185 __func__
, ctx
, texObj
);
187 if (!radeon_validate_texture_miptree(ctx
, texObj
)) {
188 radeon_error("%s(%p, tex %p) Failed to validate miptree for "
190 __func__
, ctx
, texObj
);
194 if (t
->image_override
&& t
->bo
) {
195 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
196 "%s(%p, tex %p) Work around for missing miptree in r100.\n",
197 __func__
, ctx
, texObj
);
199 map_override(ctx
, t
);
202 /* for r100 3D sw fallbacks don't have mt */
204 radeon_warning("%s(%p, tex %p) No miptree in texture.\n",
205 __func__
, ctx
, texObj
);
209 radeon_bo_map(t
->mt
->bo
, GL_FALSE
);
210 for(face
= 0; face
< t
->mt
->faces
; ++face
) {
211 for(level
= t
->minLod
; level
<= t
->maxLod
; ++level
)
212 teximage_set_map_data(get_radeon_texture_image(texObj
->Image
[face
][level
]));
216 void radeonUnmapTexture(GLcontext
*ctx
, struct gl_texture_object
*texObj
)
218 radeonTexObj
* t
= radeon_tex_obj(texObj
);
221 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
223 __func__
, ctx
, texObj
);
225 if (t
->image_override
&& t
->bo
)
226 unmap_override(ctx
, t
);
227 /* for r100 3D sw fallbacks don't have mt */
231 for(face
= 0; face
< t
->mt
->faces
; ++face
) {
232 for(level
= t
->minLod
; level
<= t
->maxLod
; ++level
)
233 texObj
->Image
[face
][level
]->Data
= 0;
235 radeon_bo_unmap(t
->mt
->bo
);
239 * Wraps Mesa's implementation to ensure that the base level image is mapped.
241 * This relies on internal details of _mesa_generate_mipmap, in particular
242 * the fact that the memory for recreated texture images is always freed.
244 static void radeon_generate_mipmap(GLcontext
*ctx
, GLenum target
,
245 struct gl_texture_object
*texObj
)
247 radeonTexObj
* t
= radeon_tex_obj(texObj
);
248 GLuint nr_faces
= (t
->base
.Target
== GL_TEXTURE_CUBE_MAP
) ? 6 : 1;
251 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
252 "%s(%p, tex %p) Target type %s.\n",
253 __func__
, ctx
, texObj
,
254 _mesa_lookup_enum_by_nr(target
));
256 _mesa_generate_mipmap(ctx
, target
, texObj
);
258 for (face
= 0; face
< nr_faces
; face
++) {
259 for (i
= texObj
->BaseLevel
+ 1; i
< texObj
->MaxLevel
; i
++) {
260 radeon_texture_image
*image
;
262 image
= get_radeon_texture_image(texObj
->Image
[face
][i
]);
268 image
->mtface
= face
;
270 radeon_miptree_unreference(&image
->mt
);
276 void radeonGenerateMipmap(GLcontext
* ctx
, GLenum target
, struct gl_texture_object
*texObj
)
278 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
279 struct radeon_bo
*bo
;
280 GLuint face
= _mesa_tex_target_to_face(target
);
281 radeon_texture_image
*baseimage
= get_radeon_texture_image(texObj
->Image
[face
][texObj
->BaseLevel
]);
282 bo
= !baseimage
->mt
? baseimage
->bo
: baseimage
->mt
->bo
;
284 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
285 "%s(%p, target %s, tex %p)\n",
286 __func__
, ctx
, _mesa_lookup_enum_by_nr(target
),
289 if (bo
&& radeon_bo_is_referenced_by_cs(bo
, rmesa
->cmdbuf
.cs
)) {
290 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
291 "%s(%p, tex %p) Trying to generate mipmap for texture "
292 "in processing by GPU.\n",
293 __func__
, ctx
, texObj
);
294 radeon_firevertices(rmesa
);
297 radeon_teximage_map(baseimage
, GL_FALSE
);
298 radeon_generate_mipmap(ctx
, target
, texObj
);
299 radeon_teximage_unmap(baseimage
);
303 /* try to find a format which will only need a memcopy */
304 static gl_format
radeonChoose8888TexFormat(radeonContextPtr rmesa
,
306 GLenum srcType
, GLboolean fbo
)
309 const GLubyte littleEndian
= *((const GLubyte
*)&ui
);
311 /* r100 can only do this */
312 if (IS_R100_CLASS(rmesa
->radeonScreen
) || fbo
)
313 return _dri_texformat_argb8888
;
315 if ((srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_INT_8_8_8_8
) ||
316 (srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_BYTE
&& !littleEndian
) ||
317 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_INT_8_8_8_8_REV
) ||
318 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_BYTE
&& littleEndian
)) {
319 return MESA_FORMAT_RGBA8888
;
320 } else if ((srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_INT_8_8_8_8_REV
) ||
321 (srcFormat
== GL_RGBA
&& srcType
== GL_UNSIGNED_BYTE
&& littleEndian
) ||
322 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_INT_8_8_8_8
) ||
323 (srcFormat
== GL_ABGR_EXT
&& srcType
== GL_UNSIGNED_BYTE
&& !littleEndian
)) {
324 return MESA_FORMAT_RGBA8888_REV
;
325 } else if (IS_R200_CLASS(rmesa
->radeonScreen
)) {
326 return _dri_texformat_argb8888
;
327 } else if (srcFormat
== GL_BGRA
&& ((srcType
== GL_UNSIGNED_BYTE
&& !littleEndian
) ||
328 srcType
== GL_UNSIGNED_INT_8_8_8_8
)) {
329 return MESA_FORMAT_ARGB8888_REV
;
330 } else if (srcFormat
== GL_BGRA
&& ((srcType
== GL_UNSIGNED_BYTE
&& littleEndian
) ||
331 srcType
== GL_UNSIGNED_INT_8_8_8_8_REV
)) {
332 return MESA_FORMAT_ARGB8888
;
334 return _dri_texformat_argb8888
;
337 gl_format
radeonChooseTextureFormat_mesa(GLcontext
* ctx
,
338 GLint internalFormat
,
342 return radeonChooseTextureFormat(ctx
, internalFormat
, format
,
346 gl_format
radeonChooseTextureFormat(GLcontext
* ctx
,
347 GLint internalFormat
,
349 GLenum type
, GLboolean fbo
)
351 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
352 const GLboolean do32bpt
=
353 (rmesa
->texture_depth
== DRI_CONF_TEXTURE_DEPTH_32
);
354 const GLboolean force16bpt
=
355 (rmesa
->texture_depth
== DRI_CONF_TEXTURE_DEPTH_FORCE_16
);
358 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
359 "%s InternalFormat=%s(%d) type=%s format=%s\n",
361 _mesa_lookup_enum_by_nr(internalFormat
), internalFormat
,
362 _mesa_lookup_enum_by_nr(type
), _mesa_lookup_enum_by_nr(format
));
363 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
364 "%s do32bpt=%d force16bpt=%d\n",
365 __func__
, do32bpt
, force16bpt
);
367 switch (internalFormat
) {
370 case GL_COMPRESSED_RGBA
:
372 case GL_UNSIGNED_INT_10_10_10_2
:
373 case GL_UNSIGNED_INT_2_10_10_10_REV
:
374 return do32bpt
? _dri_texformat_argb8888
:
375 _dri_texformat_argb1555
;
376 case GL_UNSIGNED_SHORT_4_4_4_4
:
377 case GL_UNSIGNED_SHORT_4_4_4_4_REV
:
378 return _dri_texformat_argb4444
;
379 case GL_UNSIGNED_SHORT_5_5_5_1
:
380 case GL_UNSIGNED_SHORT_1_5_5_5_REV
:
381 return _dri_texformat_argb1555
;
383 return do32bpt
? radeonChoose8888TexFormat(rmesa
, format
, type
, fbo
) :
384 _dri_texformat_argb4444
;
389 case GL_COMPRESSED_RGB
:
391 case GL_UNSIGNED_SHORT_4_4_4_4
:
392 case GL_UNSIGNED_SHORT_4_4_4_4_REV
:
393 return _dri_texformat_argb4444
;
394 case GL_UNSIGNED_SHORT_5_5_5_1
:
395 case GL_UNSIGNED_SHORT_1_5_5_5_REV
:
396 return _dri_texformat_argb1555
;
397 case GL_UNSIGNED_SHORT_5_6_5
:
398 case GL_UNSIGNED_SHORT_5_6_5_REV
:
399 return _dri_texformat_rgb565
;
401 return do32bpt
? _dri_texformat_argb8888
:
402 _dri_texformat_rgb565
;
410 radeonChoose8888TexFormat(rmesa
, format
, type
, fbo
) :
411 _dri_texformat_argb4444
;
415 return _dri_texformat_argb4444
;
418 return _dri_texformat_argb1555
;
424 return !force16bpt
? _dri_texformat_argb8888
:
425 _dri_texformat_rgb565
;
430 return _dri_texformat_rgb565
;
437 case GL_COMPRESSED_ALPHA
:
438 /* r200: can't use a8 format since interpreting hw I8 as a8 would result
439 in wrong rgb values (same as alpha value instead of 0). */
440 if (IS_R200_CLASS(rmesa
->radeonScreen
))
441 return _dri_texformat_al88
;
443 return _dri_texformat_a8
;
450 case GL_COMPRESSED_LUMINANCE
:
451 return _dri_texformat_l8
;
454 case GL_LUMINANCE_ALPHA
:
455 case GL_LUMINANCE4_ALPHA4
:
456 case GL_LUMINANCE6_ALPHA2
:
457 case GL_LUMINANCE8_ALPHA8
:
458 case GL_LUMINANCE12_ALPHA4
:
459 case GL_LUMINANCE12_ALPHA12
:
460 case GL_LUMINANCE16_ALPHA16
:
461 case GL_COMPRESSED_LUMINANCE_ALPHA
:
462 return _dri_texformat_al88
;
469 case GL_COMPRESSED_INTENSITY
:
470 return _dri_texformat_i8
;
473 if (type
== GL_UNSIGNED_SHORT_8_8_APPLE
||
474 type
== GL_UNSIGNED_BYTE
)
475 return MESA_FORMAT_YCBCR
;
477 return MESA_FORMAT_YCBCR_REV
;
481 case GL_COMPRESSED_RGB_S3TC_DXT1_EXT
:
482 return MESA_FORMAT_RGB_DXT1
;
484 case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT
:
485 return MESA_FORMAT_RGBA_DXT1
;
489 case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT
:
490 return MESA_FORMAT_RGBA_DXT3
;
492 case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT
:
493 return MESA_FORMAT_RGBA_DXT5
;
495 case GL_ALPHA16F_ARB
:
496 return MESA_FORMAT_ALPHA_FLOAT16
;
497 case GL_ALPHA32F_ARB
:
498 return MESA_FORMAT_ALPHA_FLOAT32
;
499 case GL_LUMINANCE16F_ARB
:
500 return MESA_FORMAT_LUMINANCE_FLOAT16
;
501 case GL_LUMINANCE32F_ARB
:
502 return MESA_FORMAT_LUMINANCE_FLOAT32
;
503 case GL_LUMINANCE_ALPHA16F_ARB
:
504 return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16
;
505 case GL_LUMINANCE_ALPHA32F_ARB
:
506 return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32
;
507 case GL_INTENSITY16F_ARB
:
508 return MESA_FORMAT_INTENSITY_FLOAT16
;
509 case GL_INTENSITY32F_ARB
:
510 return MESA_FORMAT_INTENSITY_FLOAT32
;
512 return MESA_FORMAT_RGBA_FLOAT16
;
514 return MESA_FORMAT_RGBA_FLOAT32
;
516 return MESA_FORMAT_RGBA_FLOAT16
;
518 return MESA_FORMAT_RGBA_FLOAT32
;
521 case GL_DEPTH_COMPONENT
:
522 case GL_DEPTH_COMPONENT16
:
523 return MESA_FORMAT_Z16
;
524 case GL_DEPTH_COMPONENT24
:
525 case GL_DEPTH_COMPONENT32
:
526 case GL_DEPTH_STENCIL_EXT
:
527 case GL_DEPTH24_STENCIL8_EXT
:
528 if (rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_RV515
)
529 return MESA_FORMAT_S8_Z24
;
531 return MESA_FORMAT_Z16
;
533 case GL_DEPTH_COMPONENT
:
534 case GL_DEPTH_COMPONENT16
:
535 case GL_DEPTH_COMPONENT24
:
536 case GL_DEPTH_COMPONENT32
:
537 case GL_DEPTH_STENCIL_EXT
:
538 case GL_DEPTH24_STENCIL8_EXT
:
539 return MESA_FORMAT_S8_Z24
;
542 /* EXT_texture_sRGB */
546 case GL_SRGB8_ALPHA8
:
547 case GL_COMPRESSED_SRGB
:
548 case GL_COMPRESSED_SRGB_ALPHA
:
549 return MESA_FORMAT_SRGBA8
;
553 case GL_COMPRESSED_SLUMINANCE
:
554 return MESA_FORMAT_SL8
;
556 case GL_SLUMINANCE_ALPHA
:
557 case GL_SLUMINANCE8_ALPHA8
:
558 case GL_COMPRESSED_SLUMINANCE_ALPHA
:
559 return MESA_FORMAT_SLA8
;
561 case GL_COMPRESSED_SRGB_S3TC_DXT1_EXT
:
562 return MESA_FORMAT_SRGB_DXT1
;
563 case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT1_EXT
:
564 return MESA_FORMAT_SRGBA_DXT1
;
565 case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT3_EXT
:
566 return MESA_FORMAT_SRGBA_DXT3
;
567 case GL_COMPRESSED_SRGB_ALPHA_S3TC_DXT5_EXT
:
568 return MESA_FORMAT_SRGBA_DXT5
;
572 "unexpected internalFormat 0x%x in %s",
573 (int)internalFormat
, __func__
);
574 return MESA_FORMAT_NONE
;
577 return MESA_FORMAT_NONE
; /* never get here */
580 /** Check if given image is valid within current texture object.
582 static int image_matches_texture_obj(struct gl_texture_object
*texObj
,
583 struct gl_texture_image
*texImage
,
586 const struct gl_texture_image
*baseImage
= texObj
->Image
[0][texObj
->BaseLevel
];
591 if (level
< texObj
->BaseLevel
|| level
> texObj
->MaxLevel
)
594 const unsigned levelDiff
= level
- texObj
->BaseLevel
;
595 const unsigned refWidth
= MAX2(baseImage
->Width
>> levelDiff
, 1);
596 const unsigned refHeight
= MAX2(baseImage
->Height
>> levelDiff
, 1);
597 const unsigned refDepth
= MAX2(baseImage
->Depth
>> levelDiff
, 1);
599 return (texImage
->Width
== refWidth
&&
600 texImage
->Height
== refHeight
&&
601 texImage
->Depth
== refDepth
);
604 static void teximage_assign_miptree(radeonContextPtr rmesa
,
605 struct gl_texture_object
*texObj
,
606 struct gl_texture_image
*texImage
,
610 radeonTexObj
*t
= radeon_tex_obj(texObj
);
611 radeon_texture_image
* image
= get_radeon_texture_image(texImage
);
613 /* Since miptree holds only images for levels <BaseLevel..MaxLevel>
614 * don't allocate the miptree if the teximage won't fit.
616 if (!image_matches_texture_obj(texObj
, texImage
, level
))
619 /* Try using current miptree, or create new if there isn't any */
620 if (!t
->mt
|| !radeon_miptree_matches_image(t
->mt
, texImage
, face
, level
)) {
621 radeon_miptree_unreference(&t
->mt
);
622 radeon_try_alloc_miptree(rmesa
, t
);
623 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
624 "%s: texObj %p, texImage %p, face %d, level %d, "
625 "texObj miptree doesn't match, allocated new miptree %p\n",
626 __FUNCTION__
, texObj
, texImage
, face
, level
, t
->mt
);
629 /* Miptree alocation may have failed,
630 * when there was no image for baselevel specified */
632 image
->mtface
= face
;
633 image
->mtlevel
= level
;
634 radeon_miptree_reference(t
->mt
, &image
->mt
);
636 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
637 "%s Failed to allocate miptree.\n", __func__
);
640 static GLuint
* allocate_image_offsets(GLcontext
*ctx
,
641 unsigned alignedWidth
,
648 offsets
= malloc(depth
* sizeof(GLuint
)) ;
650 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "glTex[Sub]Image");
654 for (i
= 0; i
< depth
; ++i
) {
655 offsets
[i
] = alignedWidth
* height
* i
;
662 * Update a subregion of the given texture image.
664 static void radeon_store_teximage(GLcontext
* ctx
, int dims
,
665 GLint xoffset
, GLint yoffset
, GLint zoffset
,
666 GLsizei width
, GLsizei height
, GLsizei depth
,
668 GLenum format
, GLenum type
,
669 const GLvoid
* pixels
,
670 const struct gl_pixelstore_attrib
*packing
,
671 struct gl_texture_object
*texObj
,
672 struct gl_texture_image
*texImage
,
675 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
676 radeonTexObj
*t
= radeon_tex_obj(texObj
);
677 radeon_texture_image
* image
= get_radeon_texture_image(texImage
);
680 GLuint
*dstImageOffsets
;
682 radeon_print(RADEON_TEXTURE
, RADEON_TRACE
,
683 "%s(%p, tex %p, image %p) compressed %d\n",
684 __func__
, ctx
, texObj
, texImage
, compressed
);
687 dstRowStride
= image
->mt
->levels
[image
->mtlevel
].rowstride
;
690 dstRowStride
= get_texture_image_row_stride(rmesa
, texImage
->TexFormat
, width
, 0);
692 dstRowStride
= _mesa_format_row_stride(texImage
->TexFormat
, texImage
->Width
);
695 assert(dstRowStride
);
698 unsigned alignedWidth
= dstRowStride
/_mesa_get_format_bytes(texImage
->TexFormat
);
699 dstImageOffsets
= allocate_image_offsets(ctx
, alignedWidth
, texImage
->Height
, texImage
->Depth
);
700 if (!dstImageOffsets
) {
701 radeon_warning("%s Failed to allocate dstImaeOffset.\n", __func__
);
705 dstImageOffsets
= texImage
->ImageOffsets
;
708 radeon_teximage_map(image
, GL_TRUE
);
711 uint32_t srcRowStride
, bytesPerRow
, rows
, block_width
, block_height
;
714 _mesa_get_format_block_size(texImage
->TexFormat
, &block_width
, &block_height
);
717 dstRowStride
= _mesa_format_row_stride(texImage
->TexFormat
, texImage
->Width
);
718 img_start
= _mesa_compressed_image_address(xoffset
, yoffset
, 0,
720 texImage
->Width
, texImage
->Data
);
724 offset
= dstRowStride
/ _mesa_get_format_bytes(texImage
->TexFormat
) * yoffset
/ block_height
+ xoffset
/ block_width
;
725 offset
*= _mesa_get_format_bytes(texImage
->TexFormat
);
726 img_start
= texImage
->Data
+ offset
;
728 srcRowStride
= _mesa_format_row_stride(texImage
->TexFormat
, width
);
729 bytesPerRow
= srcRowStride
;
730 rows
= (height
+ block_height
- 1) / block_height
;
732 copy_rows(img_start
, dstRowStride
, pixels
, srcRowStride
, rows
, bytesPerRow
);
735 if (!_mesa_texstore(ctx
, dims
, texImage
->_BaseFormat
,
736 texImage
->TexFormat
, texImage
->Data
,
737 xoffset
, yoffset
, zoffset
,
740 width
, height
, depth
,
741 format
, type
, pixels
, packing
)) {
742 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "glTexSubImage");
747 free(dstImageOffsets
);
750 radeon_teximage_unmap(image
);
754 * All glTexImage calls go through this function.
756 static void radeon_teximage(
757 GLcontext
*ctx
, int dims
,
758 GLenum target
, GLint level
,
759 GLint internalFormat
,
760 GLint width
, GLint height
, GLint depth
,
762 GLenum format
, GLenum type
, const GLvoid
* pixels
,
763 const struct gl_pixelstore_attrib
*packing
,
764 struct gl_texture_object
*texObj
,
765 struct gl_texture_image
*texImage
,
768 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
769 radeonTexObj
* t
= radeon_tex_obj(texObj
);
770 radeon_texture_image
* image
= get_radeon_texture_image(texImage
);
771 GLint postConvWidth
= width
;
772 GLint postConvHeight
= height
;
773 GLuint face
= _mesa_tex_target_to_face(target
);
775 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
776 "%s %dd: texObj %p, texImage %p, face %d, level %d\n",
777 __func__
, dims
, texObj
, texImage
, face
, level
);
779 struct radeon_bo
*bo
;
780 bo
= !image
->mt
? image
->bo
: image
->mt
->bo
;
781 if (bo
&& radeon_bo_is_referenced_by_cs(bo
, rmesa
->cmdbuf
.cs
)) {
782 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
783 "%s Calling teximage for texture that is "
784 "queued for GPU processing.\n",
786 radeon_firevertices(rmesa
);
791 t
->validated
= GL_FALSE
;
793 if (ctx
->_ImageTransferState
& IMAGE_CONVOLUTION_BIT
) {
794 _mesa_adjust_image_for_convolution(ctx
, dims
, &postConvWidth
,
798 if (!_mesa_is_format_compressed(texImage
->TexFormat
)) {
799 GLuint texelBytes
= _mesa_get_format_bytes(texImage
->TexFormat
);
800 /* Minimum pitch of 32 bytes */
801 if (postConvWidth
* texelBytes
< 32) {
802 postConvWidth
= 32 / texelBytes
;
803 texImage
->RowStride
= postConvWidth
;
806 assert(texImage
->RowStride
== postConvWidth
);
810 /* Mesa core only clears texImage->Data but not image->mt */
811 radeonFreeTexImageData(ctx
, texImage
);
814 teximage_assign_miptree(rmesa
, texObj
, texImage
, face
, level
);
816 int size
= _mesa_format_image_size(texImage
->TexFormat
,
820 texImage
->Data
= _mesa_alloc_texmemory(size
);
821 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
822 "%s %dd: texObj %p, texImage %p, "
823 " no miptree assigned, using local memory %p\n",
824 __func__
, dims
, texObj
, texImage
, texImage
->Data
);
828 /* Upload texture image; note that the spec allows pixels to be NULL */
830 pixels
= _mesa_validate_pbo_compressed_teximage(
831 ctx
, imageSize
, pixels
, packing
, "glCompressedTexImage");
833 pixels
= _mesa_validate_pbo_teximage(
834 ctx
, dims
, width
, height
, depth
,
835 format
, type
, pixels
, packing
, "glTexImage");
839 radeon_store_teximage(ctx
, dims
,
841 width
, height
, depth
,
842 imageSize
, format
, type
,
848 _mesa_unmap_teximage_pbo(ctx
, packing
);
851 void radeonTexImage1D(GLcontext
* ctx
, GLenum target
, GLint level
,
852 GLint internalFormat
,
853 GLint width
, GLint border
,
854 GLenum format
, GLenum type
, const GLvoid
* pixels
,
855 const struct gl_pixelstore_attrib
*packing
,
856 struct gl_texture_object
*texObj
,
857 struct gl_texture_image
*texImage
)
859 radeon_teximage(ctx
, 1, target
, level
, internalFormat
, width
, 1, 1,
860 0, format
, type
, pixels
, packing
, texObj
, texImage
, 0);
863 void radeonTexImage2D(GLcontext
* ctx
, GLenum target
, GLint level
,
864 GLint internalFormat
,
865 GLint width
, GLint height
, GLint border
,
866 GLenum format
, GLenum type
, const GLvoid
* pixels
,
867 const struct gl_pixelstore_attrib
*packing
,
868 struct gl_texture_object
*texObj
,
869 struct gl_texture_image
*texImage
)
872 radeon_teximage(ctx
, 2, target
, level
, internalFormat
, width
, height
, 1,
873 0, format
, type
, pixels
, packing
, texObj
, texImage
, 0);
876 void radeonCompressedTexImage2D(GLcontext
* ctx
, GLenum target
,
877 GLint level
, GLint internalFormat
,
878 GLint width
, GLint height
, GLint border
,
879 GLsizei imageSize
, const GLvoid
* data
,
880 struct gl_texture_object
*texObj
,
881 struct gl_texture_image
*texImage
)
883 radeon_teximage(ctx
, 2, target
, level
, internalFormat
, width
, height
, 1,
884 imageSize
, 0, 0, data
, &ctx
->Unpack
, texObj
, texImage
, 1);
887 void radeonTexImage3D(GLcontext
* ctx
, GLenum target
, GLint level
,
888 GLint internalFormat
,
889 GLint width
, GLint height
, GLint depth
,
891 GLenum format
, GLenum type
, const GLvoid
* pixels
,
892 const struct gl_pixelstore_attrib
*packing
,
893 struct gl_texture_object
*texObj
,
894 struct gl_texture_image
*texImage
)
896 radeon_teximage(ctx
, 3, target
, level
, internalFormat
, width
, height
, depth
,
897 0, format
, type
, pixels
, packing
, texObj
, texImage
, 0);
901 * All glTexSubImage calls go through this function.
903 static void radeon_texsubimage(GLcontext
* ctx
, int dims
, GLenum target
, int level
,
904 GLint xoffset
, GLint yoffset
, GLint zoffset
,
905 GLsizei width
, GLsizei height
, GLsizei depth
,
907 GLenum format
, GLenum type
,
908 const GLvoid
* pixels
,
909 const struct gl_pixelstore_attrib
*packing
,
910 struct gl_texture_object
*texObj
,
911 struct gl_texture_image
*texImage
,
914 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
915 radeonTexObj
* t
= radeon_tex_obj(texObj
);
916 radeon_texture_image
* image
= get_radeon_texture_image(texImage
);
918 radeon_print(RADEON_TEXTURE
, RADEON_NORMAL
,
919 "%s %dd: texObj %p, texImage %p, face %d, level %d\n",
920 __func__
, dims
, texObj
, texImage
,
921 _mesa_tex_target_to_face(target
), level
);
923 struct radeon_bo
*bo
;
924 bo
= !image
->mt
? image
->bo
: image
->mt
->bo
;
925 if (bo
&& radeon_bo_is_referenced_by_cs(bo
, rmesa
->cmdbuf
.cs
)) {
926 radeon_print(RADEON_TEXTURE
, RADEON_VERBOSE
,
927 "%s Calling texsubimage for texture that is "
928 "queued for GPU processing.\n",
930 radeon_firevertices(rmesa
);
935 t
->validated
= GL_FALSE
;
937 pixels
= _mesa_validate_pbo_compressed_teximage(
938 ctx
, imageSize
, pixels
, packing
, "glCompressedTexSubImage");
940 pixels
= _mesa_validate_pbo_teximage(ctx
, dims
,
941 width
, height
, depth
, format
, type
, pixels
, packing
, "glTexSubImage");
945 radeon_store_teximage(ctx
, dims
,
946 xoffset
, yoffset
, zoffset
,
947 width
, height
, depth
,
948 imageSize
, format
, type
,
954 _mesa_unmap_teximage_pbo(ctx
, packing
);
957 void radeonTexSubImage1D(GLcontext
* ctx
, GLenum target
, GLint level
,
960 GLenum format
, GLenum type
,
961 const GLvoid
* pixels
,
962 const struct gl_pixelstore_attrib
*packing
,
963 struct gl_texture_object
*texObj
,
964 struct gl_texture_image
*texImage
)
966 radeon_texsubimage(ctx
, 1, target
, level
, xoffset
, 0, 0, width
, 1, 1, 0,
967 format
, type
, pixels
, packing
, texObj
, texImage
, 0);
970 void radeonTexSubImage2D(GLcontext
* ctx
, GLenum target
, GLint level
,
971 GLint xoffset
, GLint yoffset
,
972 GLsizei width
, GLsizei height
,
973 GLenum format
, GLenum type
,
974 const GLvoid
* pixels
,
975 const struct gl_pixelstore_attrib
*packing
,
976 struct gl_texture_object
*texObj
,
977 struct gl_texture_image
*texImage
)
979 radeon_texsubimage(ctx
, 2, target
, level
, xoffset
, yoffset
, 0, width
, height
, 1,
980 0, format
, type
, pixels
, packing
, texObj
, texImage
,
984 void radeonCompressedTexSubImage2D(GLcontext
* ctx
, GLenum target
,
985 GLint level
, GLint xoffset
,
986 GLint yoffset
, GLsizei width
,
987 GLsizei height
, GLenum format
,
988 GLsizei imageSize
, const GLvoid
* data
,
989 struct gl_texture_object
*texObj
,
990 struct gl_texture_image
*texImage
)
992 radeon_texsubimage(ctx
, 2, target
, level
, xoffset
, yoffset
, 0, width
, height
, 1,
993 imageSize
, format
, 0, data
, &ctx
->Unpack
, texObj
, texImage
, 1);
997 void radeonTexSubImage3D(GLcontext
* ctx
, GLenum target
, GLint level
,
998 GLint xoffset
, GLint yoffset
, GLint zoffset
,
999 GLsizei width
, GLsizei height
, GLsizei depth
,
1000 GLenum format
, GLenum type
,
1001 const GLvoid
* pixels
,
1002 const struct gl_pixelstore_attrib
*packing
,
1003 struct gl_texture_object
*texObj
,
1004 struct gl_texture_image
*texImage
)
1006 radeon_texsubimage(ctx
, 3, target
, level
, xoffset
, yoffset
, zoffset
, width
, height
, depth
, 0,
1007 format
, type
, pixels
, packing
, texObj
, texImage
, 0);
1010 unsigned radeonIsFormatRenderable(gl_format mesa_format
)
1012 if (mesa_format
== _dri_texformat_argb8888
|| mesa_format
== _dri_texformat_rgb565
||
1013 mesa_format
== _dri_texformat_argb1555
|| mesa_format
== _dri_texformat_argb4444
)
1016 switch (mesa_format
)
1018 case MESA_FORMAT_Z16
:
1019 case MESA_FORMAT_S8_Z24
: