projects / mesa.git / blob
? search:


8fc686581b5bfee9a9f1803f56a99dfbe2803ba1
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_texture.c
1 /*
2 * Copyright (C) 2008 Nicolai Haehnle.
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining
10 * a copy of this software and associated documentation files (the
11 * "Software"), to deal in the Software without restriction, including
12 * without limitation the rights to use, copy, modify, merge, publish,
13 * distribute, sublicense, and/or sell copies of the Software, and to
14 * permit persons to whom the Software is furnished to do so, subject to
15 * the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the
18 * next paragraph) shall be included in all copies or substantial
19 * portions of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 *
29 */
30
31 #include "main/glheader.h"
32 #include "main/imports.h"
33 #include "main/context.h"
34 #include "main/convolve.h"
35 #include "main/mipmap.h"
36 #include "main/texcompress.h"
37 #include "main/texstore.h"
38 #include "main/teximage.h"
39 #include "main/texobj.h"
40 #include "main/texgetimage.h"
41
42 #include "xmlpool.h" /* for symbolic values of enum-type options */
43
44 #include "radeon_common.h"
45
46 #include "radeon_mipmap_tree.h"
47
48
49 static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride,
50 GLuint numrows, GLuint rowsize)
51 {
52 assert(rowsize <= dststride);
53 assert(rowsize <= srcstride);
54
55 if (rowsize == srcstride && rowsize == dststride) {
56 memcpy(dst, src, numrows*rowsize);
57 } else {
58 GLuint i;
59 for(i = 0; i < numrows; ++i) {
60 memcpy(dst, src, rowsize);
61 dst += dststride;
62 src += srcstride;
63 }
64 }
65 }
66
67 /* textures */
68 /**
69 * Allocate an empty texture image object.
70 */
71 struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx)
72 {
73 return CALLOC(sizeof(radeon_texture_image));
74 }
75
76 /**
77 * Free memory associated with this texture image.
78 */
79 void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage)
80 {
81 radeon_texture_image* image = get_radeon_texture_image(timage);
82
83 if (image->mt) {
84 radeon_miptree_unreference(&image->mt);
85 assert(!image->base.Data);
86 } else {
87 _mesa_free_texture_image_data(ctx, timage);
88 }
89 if (image->bo) {
90 radeon_bo_unref(image->bo);
91 image->bo = NULL;
92 }
93 if (timage->Data) {
94 _mesa_free_texmemory(timage->Data);
95 timage->Data = NULL;
96 }
97 }
98
99 /* Set Data pointer and additional data for mapped texture image */
100 static void teximage_set_map_data(radeon_texture_image *image)
101 {
102 radeon_mipmap_level *lvl;
103
104 if (!image->mt)
105 return;
106
107 lvl = &image->mt->levels[image->mtlevel];
108
109 image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset;
110 image->base.RowStride = lvl->rowstride / image->mt->bpp;
111 }
112
113
114 /**
115 * Map a single texture image for glTexImage and friends.
116 */
117 void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable)
118 {
119 if (image->mt) {
120 assert(!image->base.Data);
121
122 radeon_bo_map(image->mt->bo, write_enable);
123 teximage_set_map_data(image);
124 }
125 }
126
127
128 void radeon_teximage_unmap(radeon_texture_image *image)
129 {
130 if (image->mt) {
131 assert(image->base.Data);
132
133 image->base.Data = 0;
134 radeon_bo_unmap(image->mt->bo);
135 }
136 }
137
138 static void map_override(GLcontext *ctx, radeonTexObj *t)
139 {
140 radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]);
141
142 radeon_bo_map(t->bo, GL_FALSE);
143
144 img->base.Data = t->bo->ptr;
145 }
146
147 static void unmap_override(GLcontext *ctx, radeonTexObj *t)
148 {
149 radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]);
150
151 radeon_bo_unmap(t->bo);
152
153 img->base.Data = NULL;
154 }
155
156 /**
157 * Map a validated texture for reading during software rendering.
158 */
159 void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj)
160 {
161 radeonTexObj* t = radeon_tex_obj(texObj);
162 int face, level;
163
164 if (!radeon_validate_texture_miptree(ctx, texObj))
165 return;
166
167 /* for r100 3D sw fallbacks don't have mt */
168 if (t->image_override && t->bo)
169 map_override(ctx, t);
170
171 if (!t->mt)
172 return;
173
174 radeon_bo_map(t->mt->bo, GL_FALSE);
175 for(face = 0; face < t->mt->faces; ++face) {
176 for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level)
177 teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level]));
178 }
179 }
180
181 void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj)
182 {
183 radeonTexObj* t = radeon_tex_obj(texObj);
184 int face, level;
185
186 if (t->image_override && t->bo)
187 unmap_override(ctx, t);
188 /* for r100 3D sw fallbacks don't have mt */
189 if (!t->mt)
190 return;
191
192 for(face = 0; face < t->mt->faces; ++face) {
193 for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level)
194 texObj->Image[face][level]->Data = 0;
195 }
196 radeon_bo_unmap(t->mt->bo);
197 }
198
199 GLuint radeon_face_for_target(GLenum target)
200 {
201 switch (target) {
202 case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
203 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
204 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
205 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
206 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
207 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
208 return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
209 default:
210 return 0;
211 }
212 }
213
214 /**
215 * Wraps Mesa's implementation to ensure that the base level image is mapped.
216 *
217 * This relies on internal details of _mesa_generate_mipmap, in particular
218 * the fact that the memory for recreated texture images is always freed.
219 */
220 static void radeon_generate_mipmap(GLcontext *ctx, GLenum target,
221 struct gl_texture_object *texObj)
222 {
223 radeonTexObj* t = radeon_tex_obj(texObj);
224 GLuint nr_faces = (t->base.Target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
225 int i, face;
226
227
228 _mesa_generate_mipmap(ctx, target, texObj);
229
230 for (face = 0; face < nr_faces; face++) {
231 for (i = texObj->BaseLevel + 1; i < texObj->MaxLevel; i++) {
232 radeon_texture_image *image;
233
234 image = get_radeon_texture_image(texObj->Image[face][i]);
235
236 if (image == NULL)
237 break;
238
239 image->mtlevel = i;
240 image->mtface = face;
241
242 radeon_miptree_unreference(&image->mt);
243 }
244 }
245
246 }
247
248 void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj)
249 {
250 GLuint face = radeon_face_for_target(target);
251 radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]);
252
253 radeon_teximage_map(baseimage, GL_FALSE);
254 radeon_generate_mipmap(ctx, target, texObj);
255 radeon_teximage_unmap(baseimage);
256 }
257
258
259 /* try to find a format which will only need a memcopy */
260 static gl_format radeonChoose8888TexFormat(radeonContextPtr rmesa,
261 GLenum srcFormat,
262 GLenum srcType, GLboolean fbo)
263 {
264 const GLuint ui = 1;
265 const GLubyte littleEndian = *((const GLubyte *)&ui);
266
267 /* r100 can only do this */
268 if (IS_R100_CLASS(rmesa->radeonScreen) || fbo)
269 return _dri_texformat_argb8888;
270
271 if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) ||
272 (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) ||
273 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) ||
274 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) {
275 return MESA_FORMAT_RGBA8888;
276 } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) ||
277 (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) ||
278 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) ||
279 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) {
280 return MESA_FORMAT_RGBA8888_REV;
281 } else if (IS_R200_CLASS(rmesa->radeonScreen)) {
282 return _dri_texformat_argb8888;
283 } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) ||
284 srcType == GL_UNSIGNED_INT_8_8_8_8)) {
285 return MESA_FORMAT_ARGB8888_REV;
286 } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) ||
287 srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) {
288 return MESA_FORMAT_ARGB8888;
289 } else
290 return _dri_texformat_argb8888;
291 }
292
293 gl_format radeonChooseTextureFormat_mesa(GLcontext * ctx,
294 GLint internalFormat,
295 GLenum format,
296 GLenum type)
297 {
298 return radeonChooseTextureFormat(ctx, internalFormat, format,
299 type, 0);
300 }
301
302 gl_format radeonChooseTextureFormat(GLcontext * ctx,
303 GLint internalFormat,
304 GLenum format,
305 GLenum type, GLboolean fbo)
306 {
307 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
308 const GLboolean do32bpt =
309 (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32);
310 const GLboolean force16bpt =
311 (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16);
312 (void)format;
313
314 #if 0
315 fprintf(stderr, "InternalFormat=%s(%d) type=%s format=%s\n",
316 _mesa_lookup_enum_by_nr(internalFormat), internalFormat,
317 _mesa_lookup_enum_by_nr(type), _mesa_lookup_enum_by_nr(format));
318 fprintf(stderr, "do32bpt=%d force16bpt=%d\n", do32bpt, force16bpt);
319 #endif
320
321 switch (internalFormat) {
322 case 4:
323 case GL_RGBA:
324 case GL_COMPRESSED_RGBA:
325 switch (type) {
326 case GL_UNSIGNED_INT_10_10_10_2:
327 case GL_UNSIGNED_INT_2_10_10_10_REV:
328 return do32bpt ? _dri_texformat_argb8888 :
329 _dri_texformat_argb1555;
330 case GL_UNSIGNED_SHORT_4_4_4_4:
331 case GL_UNSIGNED_SHORT_4_4_4_4_REV:
332 return _dri_texformat_argb4444;
333 case GL_UNSIGNED_SHORT_5_5_5_1:
334 case GL_UNSIGNED_SHORT_1_5_5_5_REV:
335 return _dri_texformat_argb1555;
336 default:
337 return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type, fbo) :
338 _dri_texformat_argb4444;
339 }
340
341 case 3:
342 case GL_RGB:
343 case GL_COMPRESSED_RGB:
344 switch (type) {
345 case GL_UNSIGNED_SHORT_4_4_4_4:
346 case GL_UNSIGNED_SHORT_4_4_4_4_REV:
347 return _dri_texformat_argb4444;
348 case GL_UNSIGNED_SHORT_5_5_5_1:
349 case GL_UNSIGNED_SHORT_1_5_5_5_REV:
350 return _dri_texformat_argb1555;
351 case GL_UNSIGNED_SHORT_5_6_5:
352 case GL_UNSIGNED_SHORT_5_6_5_REV:
353 return _dri_texformat_rgb565;
354 default:
355 return do32bpt ? _dri_texformat_argb8888 :
356 _dri_texformat_rgb565;
357 }
358
359 case GL_RGBA8:
360 case GL_RGB10_A2:
361 case GL_RGBA12:
362 case GL_RGBA16:
363 return !force16bpt ?
364 radeonChoose8888TexFormat(rmesa, format, type, fbo) :
365 _dri_texformat_argb4444;
366
367 case GL_RGBA4:
368 case GL_RGBA2:
369 return _dri_texformat_argb4444;
370
371 case GL_RGB5_A1:
372 return _dri_texformat_argb1555;
373
374 case GL_RGB8:
375 case GL_RGB10:
376 case GL_RGB12:
377 case GL_RGB16:
378 return !force16bpt ? _dri_texformat_argb8888 :
379 _dri_texformat_rgb565;
380
381 case GL_RGB5:
382 case GL_RGB4:
383 case GL_R3_G3_B2:
384 return _dri_texformat_rgb565;
385
386 case GL_ALPHA:
387 case GL_ALPHA4:
388 case GL_ALPHA8:
389 case GL_ALPHA12:
390 case GL_ALPHA16:
391 case GL_COMPRESSED_ALPHA:
392 /* r200: can't use a8 format since interpreting hw I8 as a8 would result
393 in wrong rgb values (same as alpha value instead of 0). */
394 if (IS_R200_CLASS(rmesa->radeonScreen))
395 return _dri_texformat_al88;
396 else
397 return _dri_texformat_a8;
398 case 1:
399 case GL_LUMINANCE:
400 case GL_LUMINANCE4:
401 case GL_LUMINANCE8:
402 case GL_LUMINANCE12:
403 case GL_LUMINANCE16:
404 case GL_COMPRESSED_LUMINANCE:
405 return _dri_texformat_l8;
406
407 case 2:
408 case GL_LUMINANCE_ALPHA:
409 case GL_LUMINANCE4_ALPHA4:
410 case GL_LUMINANCE6_ALPHA2:
411 case GL_LUMINANCE8_ALPHA8:
412 case GL_LUMINANCE12_ALPHA4:
413 case GL_LUMINANCE12_ALPHA12:
414 case GL_LUMINANCE16_ALPHA16:
415 case GL_COMPRESSED_LUMINANCE_ALPHA:
416 return _dri_texformat_al88;
417
418 case GL_INTENSITY:
419 case GL_INTENSITY4:
420 case GL_INTENSITY8:
421 case GL_INTENSITY12:
422 case GL_INTENSITY16:
423 case GL_COMPRESSED_INTENSITY:
424 return _dri_texformat_i8;
425
426 case GL_YCBCR_MESA:
427 if (type == GL_UNSIGNED_SHORT_8_8_APPLE ||
428 type == GL_UNSIGNED_BYTE)
429 return MESA_FORMAT_YCBCR;
430 else
431 return MESA_FORMAT_YCBCR_REV;
432
433 case GL_RGB_S3TC:
434 case GL_RGB4_S3TC:
435 case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
436 return MESA_FORMAT_RGB_DXT1;
437
438 case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
439 return MESA_FORMAT_RGBA_DXT1;
440
441 case GL_RGBA_S3TC:
442 case GL_RGBA4_S3TC:
443 case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT:
444 return MESA_FORMAT_RGBA_DXT3;
445
446 case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT:
447 return MESA_FORMAT_RGBA_DXT5;
448
449 case GL_ALPHA16F_ARB:
450 return MESA_FORMAT_ALPHA_FLOAT16;
451 case GL_ALPHA32F_ARB:
452 return MESA_FORMAT_ALPHA_FLOAT32;
453 case GL_LUMINANCE16F_ARB:
454 return MESA_FORMAT_LUMINANCE_FLOAT16;
455 case GL_LUMINANCE32F_ARB:
456 return MESA_FORMAT_LUMINANCE_FLOAT32;
457 case GL_LUMINANCE_ALPHA16F_ARB:
458 return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT16;
459 case GL_LUMINANCE_ALPHA32F_ARB:
460 return MESA_FORMAT_LUMINANCE_ALPHA_FLOAT32;
461 case GL_INTENSITY16F_ARB:
462 return MESA_FORMAT_INTENSITY_FLOAT16;
463 case GL_INTENSITY32F_ARB:
464 return MESA_FORMAT_INTENSITY_FLOAT32;
465 case GL_RGB16F_ARB:
466 return MESA_FORMAT_RGBA_FLOAT16;
467 case GL_RGB32F_ARB:
468 return MESA_FORMAT_RGBA_FLOAT32;
469 case GL_RGBA16F_ARB:
470 return MESA_FORMAT_RGBA_FLOAT16;
471 case GL_RGBA32F_ARB:
472 return MESA_FORMAT_RGBA_FLOAT32;
473
474 case GL_DEPTH_COMPONENT:
475 case GL_DEPTH_COMPONENT16:
476 case GL_DEPTH_COMPONENT24:
477 case GL_DEPTH_COMPONENT32:
478 case GL_DEPTH_STENCIL_EXT:
479 case GL_DEPTH24_STENCIL8_EXT:
480 return MESA_FORMAT_S8_Z24;
481
482 /* EXT_texture_sRGB */
483 case GL_SRGB:
484 case GL_SRGB8:
485 case GL_SRGB_ALPHA:
486 case GL_SRGB8_ALPHA8:
487 case GL_COMPRESSED_SRGB:
488 case GL_COMPRESSED_SRGB_ALPHA:
489 return MESA_FORMAT_SRGBA8;
490
491 case GL_SLUMINANCE:
492 case GL_SLUMINANCE8:
493 case GL_COMPRESSED_SLUMINANCE:
494 return MESA_FORMAT_SL8;
495
496 case GL_SLUMINANCE_ALPHA:
497 case GL_SLUMINANCE8_ALPHA8:
498 case GL_COMPRESSED_SLUMINANCE_ALPHA:
499 return MESA_FORMAT_SLA8;
500
501 default:
502 _mesa_problem(ctx,
503 "unexpected internalFormat 0x%x in %s",
504 (int)internalFormat, __func__);
505 return MESA_FORMAT_NONE;
506 }
507
508 return MESA_FORMAT_NONE; /* never get here */
509 }
510
511 static GLuint * allocate_image_offsets(GLcontext *ctx,
512 unsigned alignedWidth,
513 unsigned height,
514 unsigned depth)
515 {
516 int i;
517 GLuint *offsets;
518
519 offsets = _mesa_malloc(depth * sizeof(GLuint)) ;
520 if (!offsets) {
521 _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTex[Sub]Image");
522 return NULL;
523 }
524
525 for (i = 0; i < depth; ++i) {
526 offsets[i] = alignedWidth * height * i;
527 }
528
529 return offsets;
530 }
531
532 /**
533 * All glTexImage calls go through this function.
534 */
535 static void radeon_teximage(
536 GLcontext *ctx, int dims,
537 GLenum target, GLint level,
538 GLint internalFormat,
539 GLint width, GLint height, GLint depth,
540 GLsizei imageSize,
541 GLenum format, GLenum type, const GLvoid * pixels,
542 const struct gl_pixelstore_attrib *packing,
543 struct gl_texture_object *texObj,
544 struct gl_texture_image *texImage,
545 int compressed)
546 {
547 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
548 radeonTexObj* t = radeon_tex_obj(texObj);
549 radeon_texture_image* image = get_radeon_texture_image(texImage);
550 GLuint dstRowStride;
551 GLint postConvWidth = width;
552 GLint postConvHeight = height;
553 GLuint texelBytes;
554 GLuint face = radeon_face_for_target(target);
555
556 {
557 struct radeon_bo *bo;
558 bo = !image->mt ? image->bo : image->mt->bo;
559 if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) {
560 radeon_firevertices(rmesa);
561 }
562 }
563
564 t->validated = GL_FALSE;
565
566 if (ctx->_ImageTransferState & IMAGE_CONVOLUTION_BIT) {
567 _mesa_adjust_image_for_convolution(ctx, dims, &postConvWidth,
568 &postConvHeight);
569 }
570
571 if (_mesa_is_format_compressed(texImage->TexFormat)) {
572 texelBytes = 0;
573 } else {
574 texelBytes = _mesa_get_format_bytes(texImage->TexFormat);
575 /* Minimum pitch of 32 bytes */
576 if (postConvWidth * texelBytes < 32) {
577 postConvWidth = 32 / texelBytes;
578 texImage->RowStride = postConvWidth;
579 }
580 if (!image->mt) {
581 assert(texImage->RowStride == postConvWidth);
582 }
583 }
584
585 /* Allocate memory for image */
586 radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */
587
588 if (t->mt &&
589 t->mt->firstLevel == level &&
590 t->mt->lastLevel == level &&
591 t->mt->target != GL_TEXTURE_CUBE_MAP_ARB &&
592 !radeon_miptree_matches_image(t->mt, texImage, face, level)) {
593 radeon_miptree_unreference(&t->mt);
594 }
595
596 if (!t->mt)
597 radeon_try_alloc_miptree(rmesa, t, image, face, level);
598 if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) {
599 radeon_mipmap_level *lvl;
600 image->mtlevel = level - t->mt->firstLevel;
601 image->mtface = face;
602 radeon_miptree_reference(t->mt, &image->mt);
603 lvl = &image->mt->levels[image->mtlevel];
604 dstRowStride = lvl->rowstride;
605 } else {
606 int size;
607 if (_mesa_is_format_compressed(texImage->TexFormat)) {
608 size = _mesa_format_image_size(texImage->TexFormat,
609 texImage->Width,
610 texImage->Height,
611 texImage->Depth);
612 } else {
613 size = texImage->Width * texImage->Height * texImage->Depth * _mesa_get_format_bytes(texImage->TexFormat);
614 }
615 texImage->Data = _mesa_alloc_texmemory(size);
616 }
617
618 /* Upload texture image; note that the spec allows pixels to be NULL */
619 if (compressed) {
620 pixels = _mesa_validate_pbo_compressed_teximage(
621 ctx, imageSize, pixels, packing, "glCompressedTexImage");
622 } else {
623 pixels = _mesa_validate_pbo_teximage(
624 ctx, dims, width, height, depth,
625 format, type, pixels, packing, "glTexImage");
626 }
627
628 if (pixels) {
629 if (compressed) {
630 radeon_teximage_map(image, GL_TRUE);
631 if (image->mt) {
632 uint32_t srcRowStride, bytesPerRow, rows;
633 srcRowStride = _mesa_format_row_stride(texImage->TexFormat, width);
634 bytesPerRow = srcRowStride;
635 rows = (height + 3) / 4;
636 copy_rows(texImage->Data, image->mt->levels[level].rowstride,
637 pixels, srcRowStride, rows, bytesPerRow);
638 } else {
639 memcpy(texImage->Data, pixels, imageSize);
640 }
641 } else {
642 GLuint dstRowStride;
643 GLuint *dstImageOffsets;
644
645 if (image->mt) {
646 radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel];
647 dstRowStride = lvl->rowstride;
648 } else {
649 dstRowStride = texImage->Width * _mesa_get_format_bytes(texImage->TexFormat);
650 }
651
652 if (dims == 3) {
653 unsigned alignedWidth = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat);
654 dstImageOffsets = allocate_image_offsets(ctx, alignedWidth, height, depth);
655 if (!dstImageOffsets) {
656 return;
657 }
658 } else {
659 dstImageOffsets = texImage->ImageOffsets;
660 }
661
662 radeon_teximage_map(image, GL_TRUE);
663
664 if (!_mesa_texstore(ctx, dims,
665 texImage->_BaseFormat,
666 texImage->TexFormat,
667 texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */
668 dstRowStride,
669 dstImageOffsets,
670 width, height, depth,
671 format, type, pixels, packing)) {
672 _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage");
673 }
674
675 if (dims == 3)
676 _mesa_free(dstImageOffsets);
677 }
678 }
679
680 _mesa_unmap_teximage_pbo(ctx, packing);
681
682 if (pixels)
683 radeon_teximage_unmap(image);
684
685
686 }
687
688 void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level,
689 GLint internalFormat,
690 GLint width, GLint border,
691 GLenum format, GLenum type, const GLvoid * pixels,
692 const struct gl_pixelstore_attrib *packing,
693 struct gl_texture_object *texObj,
694 struct gl_texture_image *texImage)
695 {
696 radeon_teximage(ctx, 1, target, level, internalFormat, width, 1, 1,
697 0, format, type, pixels, packing, texObj, texImage, 0);
698 }
699
700 void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level,
701 GLint internalFormat,
702 GLint width, GLint height, GLint border,
703 GLenum format, GLenum type, const GLvoid * pixels,
704 const struct gl_pixelstore_attrib *packing,
705 struct gl_texture_object *texObj,
706 struct gl_texture_image *texImage)
707
708 {
709 radeon_teximage(ctx, 2, target, level, internalFormat, width, height, 1,
710 0, format, type, pixels, packing, texObj, texImage, 0);
711 }
712
713 void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target,
714 GLint level, GLint internalFormat,
715 GLint width, GLint height, GLint border,
716 GLsizei imageSize, const GLvoid * data,
717 struct gl_texture_object *texObj,
718 struct gl_texture_image *texImage)
719 {
720 radeon_teximage(ctx, 2, target, level, internalFormat, width, height, 1,
721 imageSize, 0, 0, data, &ctx->Unpack, texObj, texImage, 1);
722 }
723
724 void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level,
725 GLint internalFormat,
726 GLint width, GLint height, GLint depth,
727 GLint border,
728 GLenum format, GLenum type, const GLvoid * pixels,
729 const struct gl_pixelstore_attrib *packing,
730 struct gl_texture_object *texObj,
731 struct gl_texture_image *texImage)
732 {
733 radeon_teximage(ctx, 3, target, level, internalFormat, width, height, depth,
734 0, format, type, pixels, packing, texObj, texImage, 0);
735 }
736
737 /**
738 * Update a subregion of the given texture image.
739 */
740 static void radeon_texsubimage(GLcontext* ctx, int dims, GLenum target, int level,
741 GLint xoffset, GLint yoffset, GLint zoffset,
742 GLsizei width, GLsizei height, GLsizei depth,
743 GLsizei imageSize,
744 GLenum format, GLenum type,
745 const GLvoid * pixels,
746 const struct gl_pixelstore_attrib *packing,
747 struct gl_texture_object *texObj,
748 struct gl_texture_image *texImage,
749 int compressed)
750 {
751 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
752 radeonTexObj* t = radeon_tex_obj(texObj);
753 radeon_texture_image* image = get_radeon_texture_image(texImage);
754
755 {
756 struct radeon_bo *bo;
757 bo = !image->mt ? image->bo : image->mt->bo;
758 if (bo && radeon_bo_is_referenced_by_cs(bo, rmesa->cmdbuf.cs)) {
759 radeon_firevertices(rmesa);
760 }
761 }
762
763 t->validated = GL_FALSE;
764 if (compressed) {
765 pixels = _mesa_validate_pbo_compressed_teximage(
766 ctx, imageSize, pixels, packing, "glCompressedTexImage");
767 } else {
768 pixels = _mesa_validate_pbo_teximage(ctx, dims,
769 width, height, depth, format, type, pixels, packing, "glTexSubImage1D");
770 }
771
772 if (pixels) {
773 GLint dstRowStride;
774 GLuint *dstImageOffsets;
775
776 if (image->mt) {
777 radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel];
778 dstRowStride = lvl->rowstride;
779 } else {
780 dstRowStride = texImage->RowStride * _mesa_get_format_bytes(texImage->TexFormat);
781 }
782
783 if (dims == 3) {
784 unsigned alignedWidth = dstRowStride/_mesa_get_format_bytes(texImage->TexFormat);
785 dstImageOffsets = allocate_image_offsets(ctx, alignedWidth, height, depth);
786 if (!dstImageOffsets) {
787 return;
788 }
789 } else {
790 dstImageOffsets = texImage->ImageOffsets;
791 }
792
793 radeon_teximage_map(image, GL_TRUE);
794
795 if (compressed) {
796 uint32_t srcRowStride, bytesPerRow, rows;
797 GLubyte *img_start;
798 if (!image->mt) {
799 dstRowStride = _mesa_format_row_stride(texImage->TexFormat, texImage->Width);
800 img_start = _mesa_compressed_image_address(xoffset, yoffset, 0,
801 texImage->TexFormat,
802 texImage->Width, texImage->Data);
803 }
804 else {
805 uint32_t blocks_x = dstRowStride / (image->mt->bpp * 4);
806 img_start = texImage->Data + image->mt->bpp * 4 * (blocks_x * (yoffset / 4) + xoffset / 4);
807 }
808 srcRowStride = _mesa_format_row_stride(texImage->TexFormat, width);
809 bytesPerRow = srcRowStride;
810 rows = (height + 3) / 4;
811
812 copy_rows(img_start, dstRowStride, pixels, srcRowStride, rows, bytesPerRow);
813
814 }
815 else {
816 if (!_mesa_texstore(ctx, dims, texImage->_BaseFormat,
817 texImage->TexFormat, texImage->Data,
818 xoffset, yoffset, zoffset,
819 dstRowStride,
820 dstImageOffsets,
821 width, height, depth,
822 format, type, pixels, packing)) {
823 _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage");
824 }
825 }
826
827 if (dims == 3) {
828 _mesa_free(dstImageOffsets);
829 }
830 }
831
832 radeon_teximage_unmap(image);
833
834 _mesa_unmap_teximage_pbo(ctx, packing);
835
836
837 }
838
839 void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level,
840 GLint xoffset,
841 GLsizei width,
842 GLenum format, GLenum type,
843 const GLvoid * pixels,
844 const struct gl_pixelstore_attrib *packing,
845 struct gl_texture_object *texObj,
846 struct gl_texture_image *texImage)
847 {
848 radeon_texsubimage(ctx, 1, target, level, xoffset, 0, 0, width, 1, 1, 0,
849 format, type, pixels, packing, texObj, texImage, 0);
850 }
851
852 void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level,
853 GLint xoffset, GLint yoffset,
854 GLsizei width, GLsizei height,
855 GLenum format, GLenum type,
856 const GLvoid * pixels,
857 const struct gl_pixelstore_attrib *packing,
858 struct gl_texture_object *texObj,
859 struct gl_texture_image *texImage)
860 {
861 radeon_texsubimage(ctx, 2, target, level, xoffset, yoffset, 0, width, height, 1,
862 0, format, type, pixels, packing, texObj, texImage,
863 0);
864 }
865
866 void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target,
867 GLint level, GLint xoffset,
868 GLint yoffset, GLsizei width,
869 GLsizei height, GLenum format,
870 GLsizei imageSize, const GLvoid * data,
871 struct gl_texture_object *texObj,
872 struct gl_texture_image *texImage)
873 {
874 radeon_texsubimage(ctx, 2, target, level, xoffset, yoffset, 0, width, height, 1,
875 imageSize, format, 0, data, &ctx->Unpack, texObj, texImage, 1);
876 }
877
878
879 void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level,
880 GLint xoffset, GLint yoffset, GLint zoffset,
881 GLsizei width, GLsizei height, GLsizei depth,
882 GLenum format, GLenum type,
883 const GLvoid * pixels,
884 const struct gl_pixelstore_attrib *packing,
885 struct gl_texture_object *texObj,
886 struct gl_texture_image *texImage)
887 {
888 radeon_texsubimage(ctx, 3, target, level, xoffset, yoffset, zoffset, width, height, depth, 0,
889 format, type, pixels, packing, texObj, texImage, 0);
890 }
891
892
893
894 /**
895 * Ensure that the given image is stored in the given miptree from now on.
896 */
897 static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level)
898 {
899 radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel];
900 unsigned char *dest;
901
902 assert(image->mt != mt);
903 assert(dstlvl->width == image->base.Width);
904 assert(dstlvl->height == image->base.Height);
905 assert(dstlvl->depth == image->base.Depth);
906
907
908 radeon_bo_map(mt->bo, GL_TRUE);
909 dest = mt->bo->ptr + dstlvl->faces[face].offset;
910
911 if (image->mt) {
912 /* Format etc. should match, so we really just need a memcpy().
913 * In fact, that memcpy() could be done by the hardware in many
914 * cases, provided that we have a proper memory manager.
915 */
916 radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel-image->mt->firstLevel];
917
918 assert(srclvl->size == dstlvl->size);
919 assert(srclvl->rowstride == dstlvl->rowstride);
920
921 radeon_bo_map(image->mt->bo, GL_FALSE);
922
923 memcpy(dest,
924 image->mt->bo->ptr + srclvl->faces[face].offset,
925 dstlvl->size);
926 radeon_bo_unmap(image->mt->bo);
927
928 radeon_miptree_unreference(&image->mt);
929 } else {
930 uint32_t srcrowstride;
931 uint32_t height;
932 /* need to confirm this value is correct */
933 if (mt->compressed) {
934 height = (image->base.Height + 3) / 4;
935 srcrowstride = _mesa_format_row_stride(image->base.TexFormat, image->base.Width);
936 } else {
937 height = image->base.Height * image->base.Depth;
938 srcrowstride = image->base.Width * _mesa_get_format_bytes(image->base.TexFormat);
939 }
940
941 // if (mt->tilebits)
942 // WARN_ONCE("%s: tiling not supported yet", __FUNCTION__);
943
944 copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
945 height, srcrowstride);
946
947 _mesa_free_texmemory(image->base.Data);
948 image->base.Data = 0;
949 }
950
951 radeon_bo_unmap(mt->bo);
952
953 image->mtface = face;
954 image->mtlevel = level;
955 radeon_miptree_reference(mt, &image->mt);
956 }
957
958 int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj)
959 {
960 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
961 radeonTexObj *t = radeon_tex_obj(texObj);
962 radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]);
963 int face, level;
964
965 if (t->validated || t->image_override)
966 return GL_TRUE;
967
968 if (RADEON_DEBUG & RADEON_TEXTURE)
969 fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj);
970
971 if (baseimage->base.Border > 0)
972 return GL_FALSE;
973
974 /* Ensure a matching miptree exists.
975 *
976 * Differing mipmap trees can result when the app uses TexImage to
977 * change texture dimensions.
978 *
979 * Prefer to use base image's miptree if it
980 * exists, since that most likely contains more valid data (remember
981 * that the base level is usually significantly larger than the rest
982 * of the miptree, so cubemaps are the only possible exception).
983 */
984 if (baseimage->mt &&
985 baseimage->mt != t->mt &&
986 radeon_miptree_matches_texture(baseimage->mt, &t->base)) {
987 radeon_miptree_unreference(&t->mt);
988 radeon_miptree_reference(baseimage->mt, &t->mt);
989 } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) {
990 radeon_miptree_unreference(&t->mt);
991 }
992
993 if (!t->mt) {
994 if (RADEON_DEBUG & RADEON_TEXTURE)
995 fprintf(stderr, " Allocate new miptree\n");
996 radeon_try_alloc_miptree(rmesa, t, baseimage, 0, texObj->BaseLevel);
997 if (!t->mt) {
998 _mesa_problem(ctx, "radeon_validate_texture failed to alloc miptree");
999 return GL_FALSE;
1000 }
1001 }
1002
1003 /* Ensure all images are stored in the single main miptree */
1004 for(face = 0; face < t->mt->faces; ++face) {
1005 for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) {
1006 radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]);
1007 if (RADEON_DEBUG & RADEON_TEXTURE)
1008 fprintf(stderr, " face %i, level %i... %p vs %p ", face, level, t->mt, image->mt);
1009 if (t->mt == image->mt || (!image->mt && !image->base.Data)) {
1010 if (RADEON_DEBUG & RADEON_TEXTURE)
1011 fprintf(stderr, "OK\n");
1012
1013 continue;
1014 }
1015
1016 if (RADEON_DEBUG & RADEON_TEXTURE)
1017 fprintf(stderr, "migrating\n");
1018 migrate_image_to_miptree(t->mt, image, face, level);
1019 }
1020 }
1021
1022 return GL_TRUE;
1023 }
1024
1025
1026 /**
1027 * Need to map texture image into memory before copying image data,
1028 * then unmap it.
1029 */
1030 static void
1031 radeon_get_tex_image(GLcontext * ctx, GLenum target, GLint level,
1032 GLenum format, GLenum type, GLvoid * pixels,
1033 struct gl_texture_object *texObj,
1034 struct gl_texture_image *texImage, int compressed)
1035 {
1036 radeon_texture_image *image = get_radeon_texture_image(texImage);
1037
1038 if (image->mt) {
1039 /* Map the texture image read-only */
1040 radeon_teximage_map(image, GL_FALSE);
1041 } else {
1042 /* Image hasn't been uploaded to a miptree yet */
1043 assert(image->base.Data);
1044 }
1045
1046 if (compressed) {
1047 /* FIXME: this can't work for small textures (mips) which
1048 use different hw stride */
1049 _mesa_get_compressed_teximage(ctx, target, level, pixels,
1050 texObj, texImage);
1051 } else {
1052 _mesa_get_teximage(ctx, target, level, format, type, pixels,
1053 texObj, texImage);
1054 }
1055
1056 if (image->mt) {
1057 radeon_teximage_unmap(image);
1058 }
1059 }
1060
1061 void
1062 radeonGetTexImage(GLcontext * ctx, GLenum target, GLint level,
1063 GLenum format, GLenum type, GLvoid * pixels,
1064 struct gl_texture_object *texObj,
1065 struct gl_texture_image *texImage)
1066 {
1067 radeon_get_tex_image(ctx, target, level, format, type, pixels,
1068 texObj, texImage, 0);
1069 }
1070
1071 void
1072 radeonGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level,
1073 GLvoid *pixels,
1074 struct gl_texture_object *texObj,
1075 struct gl_texture_image *texImage)
1076 {
1077 radeon_get_tex_image(ctx, target, level, 0, 0, pixels,
1078 texObj, texImage, 1);
1079 }