r300: fix 3D textures
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_texture.c
1 /*
2 * Copyright (C) 2008 Nicolai Haehnle.
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining
10 * a copy of this software and associated documentation files (the
11 * "Software"), to deal in the Software without restriction, including
12 * without limitation the rights to use, copy, modify, merge, publish,
13 * distribute, sublicense, and/or sell copies of the Software, and to
14 * permit persons to whom the Software is furnished to do so, subject to
15 * the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the
18 * next paragraph) shall be included in all copies or substantial
19 * portions of the Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 *
29 */
30
31 #include "main/glheader.h"
32 #include "main/imports.h"
33 #include "main/context.h"
34 #include "main/convolve.h"
35 #include "main/mipmap.h"
36 #include "main/texcompress.h"
37 #include "main/texformat.h"
38 #include "main/texstore.h"
39 #include "main/teximage.h"
40 #include "main/texobj.h"
41 #include "main/texgetimage.h"
42
43 #include "xmlpool.h" /* for symbolic values of enum-type options */
44
45 #include "radeon_common.h"
46
47 #include "radeon_mipmap_tree.h"
48
49
50 static void copy_rows(void* dst, GLuint dststride, const void* src, GLuint srcstride,
51 GLuint numrows, GLuint rowsize)
52 {
53 assert(rowsize <= dststride);
54 assert(rowsize <= srcstride);
55
56 if (rowsize == srcstride && rowsize == dststride) {
57 memcpy(dst, src, numrows*rowsize);
58 } else {
59 GLuint i;
60 for(i = 0; i < numrows; ++i) {
61 memcpy(dst, src, rowsize);
62 dst += dststride;
63 src += srcstride;
64 }
65 }
66 }
67
68 /* textures */
69 /**
70 * Allocate an empty texture image object.
71 */
72 struct gl_texture_image *radeonNewTextureImage(GLcontext *ctx)
73 {
74 return CALLOC(sizeof(radeon_texture_image));
75 }
76
77 /**
78 * Free memory associated with this texture image.
79 */
80 void radeonFreeTexImageData(GLcontext *ctx, struct gl_texture_image *timage)
81 {
82 radeon_texture_image* image = get_radeon_texture_image(timage);
83
84 if (image->mt) {
85 radeon_miptree_unreference(image->mt);
86 image->mt = 0;
87 assert(!image->base.Data);
88 } else {
89 _mesa_free_texture_image_data(ctx, timage);
90 }
91 if (image->bo) {
92 radeon_bo_unref(image->bo);
93 image->bo = NULL;
94 }
95 if (timage->Data) {
96 _mesa_free_texmemory(timage->Data);
97 timage->Data = NULL;
98 }
99 }
100
101 /* Set Data pointer and additional data for mapped texture image */
102 static void teximage_set_map_data(radeon_texture_image *image)
103 {
104 radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel];
105
106 image->base.Data = image->mt->bo->ptr + lvl->faces[image->mtface].offset;
107 image->base.RowStride = lvl->rowstride / image->mt->bpp;
108 }
109
110
111 /**
112 * Map a single texture image for glTexImage and friends.
113 */
114 void radeon_teximage_map(radeon_texture_image *image, GLboolean write_enable)
115 {
116 if (image->mt) {
117 assert(!image->base.Data);
118
119 radeon_bo_map(image->mt->bo, write_enable);
120 teximage_set_map_data(image);
121 }
122 }
123
124
125 void radeon_teximage_unmap(radeon_texture_image *image)
126 {
127 if (image->mt) {
128 assert(image->base.Data);
129
130 image->base.Data = 0;
131 radeon_bo_unmap(image->mt->bo);
132 }
133 }
134
135 static void map_override(GLcontext *ctx, radeonTexObj *t)
136 {
137 radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]);
138
139 radeon_bo_map(t->bo, GL_FALSE);
140
141 img->base.Data = t->bo->ptr;
142 _mesa_set_fetch_functions(&img->base, 2);
143 }
144
145 static void unmap_override(GLcontext *ctx, radeonTexObj *t)
146 {
147 radeon_texture_image *img = get_radeon_texture_image(t->base.Image[0][0]);
148
149 radeon_bo_unmap(t->bo);
150
151 img->base.Data = NULL;
152 }
153
154 /**
155 * Map a validated texture for reading during software rendering.
156 */
157 void radeonMapTexture(GLcontext *ctx, struct gl_texture_object *texObj)
158 {
159 radeonTexObj* t = radeon_tex_obj(texObj);
160 int face, level;
161
162 if (!radeon_validate_texture_miptree(ctx, texObj))
163 return;
164
165 /* for r100 3D sw fallbacks don't have mt */
166 if (t->image_override && t->bo)
167 map_override(ctx, t);
168
169 if (!t->mt)
170 return;
171
172 radeon_bo_map(t->mt->bo, GL_FALSE);
173 for(face = 0; face < t->mt->faces; ++face) {
174 for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level)
175 teximage_set_map_data(get_radeon_texture_image(texObj->Image[face][level]));
176 }
177 }
178
179 void radeonUnmapTexture(GLcontext *ctx, struct gl_texture_object *texObj)
180 {
181 radeonTexObj* t = radeon_tex_obj(texObj);
182 int face, level;
183
184 if (t->image_override && t->bo)
185 unmap_override(ctx, t);
186 /* for r100 3D sw fallbacks don't have mt */
187 if (!t->mt)
188 return;
189
190 for(face = 0; face < t->mt->faces; ++face) {
191 for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level)
192 texObj->Image[face][level]->Data = 0;
193 }
194 radeon_bo_unmap(t->mt->bo);
195 }
196
197 GLuint radeon_face_for_target(GLenum target)
198 {
199 switch (target) {
200 case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
201 case GL_TEXTURE_CUBE_MAP_NEGATIVE_X:
202 case GL_TEXTURE_CUBE_MAP_POSITIVE_Y:
203 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Y:
204 case GL_TEXTURE_CUBE_MAP_POSITIVE_Z:
205 case GL_TEXTURE_CUBE_MAP_NEGATIVE_Z:
206 return (GLuint) target - (GLuint) GL_TEXTURE_CUBE_MAP_POSITIVE_X;
207 default:
208 return 0;
209 }
210 }
211
212 /**
213 * Wraps Mesa's implementation to ensure that the base level image is mapped.
214 *
215 * This relies on internal details of _mesa_generate_mipmap, in particular
216 * the fact that the memory for recreated texture images is always freed.
217 */
218 static void radeon_generate_mipmap(GLcontext *ctx, GLenum target,
219 struct gl_texture_object *texObj)
220 {
221 radeonTexObj* t = radeon_tex_obj(texObj);
222 GLuint nr_faces = (t->base.Target == GL_TEXTURE_CUBE_MAP) ? 6 : 1;
223 int i, face;
224
225
226 _mesa_generate_mipmap(ctx, target, texObj);
227
228 for (face = 0; face < nr_faces; face++) {
229 for (i = texObj->BaseLevel + 1; i < texObj->MaxLevel; i++) {
230 radeon_texture_image *image;
231
232 image = get_radeon_texture_image(texObj->Image[face][i]);
233
234 if (image == NULL)
235 break;
236
237 image->mtlevel = i;
238 image->mtface = face;
239
240 radeon_miptree_unreference(image->mt);
241 image->mt = NULL;
242 }
243 }
244
245 }
246
247 void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj)
248 {
249 GLuint face = radeon_face_for_target(target);
250 radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[face][texObj->BaseLevel]);
251
252 radeon_teximage_map(baseimage, GL_FALSE);
253 radeon_generate_mipmap(ctx, target, texObj);
254 radeon_teximage_unmap(baseimage);
255 }
256
257
258 /* try to find a format which will only need a memcopy */
259 static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa,
260 GLenum srcFormat,
261 GLenum srcType, GLboolean fbo)
262 {
263 const GLuint ui = 1;
264 const GLubyte littleEndian = *((const GLubyte *)&ui);
265
266 /* r100 can only do this */
267 if (IS_R100_CLASS(rmesa->radeonScreen) || fbo)
268 return _dri_texformat_argb8888;
269
270 if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) ||
271 (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && !littleEndian) ||
272 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) ||
273 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && littleEndian)) {
274 return &_mesa_texformat_rgba8888;
275 } else if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8_REV) ||
276 (srcFormat == GL_RGBA && srcType == GL_UNSIGNED_BYTE && littleEndian) ||
277 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_INT_8_8_8_8) ||
278 (srcFormat == GL_ABGR_EXT && srcType == GL_UNSIGNED_BYTE && !littleEndian)) {
279 return &_mesa_texformat_rgba8888_rev;
280 } else if (IS_R200_CLASS(rmesa->radeonScreen)) {
281 return _dri_texformat_argb8888;
282 } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && !littleEndian) ||
283 srcType == GL_UNSIGNED_INT_8_8_8_8)) {
284 return &_mesa_texformat_argb8888_rev;
285 } else if (srcFormat == GL_BGRA && ((srcType == GL_UNSIGNED_BYTE && littleEndian) ||
286 srcType == GL_UNSIGNED_INT_8_8_8_8_REV)) {
287 return &_mesa_texformat_argb8888;
288 } else
289 return _dri_texformat_argb8888;
290 }
291
292 const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx,
293 GLint internalFormat,
294 GLenum format,
295 GLenum type)
296 {
297 return radeonChooseTextureFormat(ctx, internalFormat, format,
298 type, 0);
299 }
300
301 const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx,
302 GLint internalFormat,
303 GLenum format,
304 GLenum type, GLboolean fbo)
305 {
306 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
307 const GLboolean do32bpt =
308 (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32);
309 const GLboolean force16bpt =
310 (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_FORCE_16);
311 (void)format;
312
313 #if 0
314 fprintf(stderr, "InternalFormat=%s(%d) type=%s format=%s\n",
315 _mesa_lookup_enum_by_nr(internalFormat), internalFormat,
316 _mesa_lookup_enum_by_nr(type), _mesa_lookup_enum_by_nr(format));
317 fprintf(stderr, "do32bpt=%d force16bpt=%d\n", do32bpt, force16bpt);
318 #endif
319
320 switch (internalFormat) {
321 case 4:
322 case GL_RGBA:
323 case GL_COMPRESSED_RGBA:
324 switch (type) {
325 case GL_UNSIGNED_INT_10_10_10_2:
326 case GL_UNSIGNED_INT_2_10_10_10_REV:
327 return do32bpt ? _dri_texformat_argb8888 :
328 _dri_texformat_argb1555;
329 case GL_UNSIGNED_SHORT_4_4_4_4:
330 case GL_UNSIGNED_SHORT_4_4_4_4_REV:
331 return _dri_texformat_argb4444;
332 case GL_UNSIGNED_SHORT_5_5_5_1:
333 case GL_UNSIGNED_SHORT_1_5_5_5_REV:
334 return _dri_texformat_argb1555;
335 default:
336 return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type, fbo) :
337 _dri_texformat_argb4444;
338 }
339
340 case 3:
341 case GL_RGB:
342 case GL_COMPRESSED_RGB:
343 switch (type) {
344 case GL_UNSIGNED_SHORT_4_4_4_4:
345 case GL_UNSIGNED_SHORT_4_4_4_4_REV:
346 return _dri_texformat_argb4444;
347 case GL_UNSIGNED_SHORT_5_5_5_1:
348 case GL_UNSIGNED_SHORT_1_5_5_5_REV:
349 return _dri_texformat_argb1555;
350 case GL_UNSIGNED_SHORT_5_6_5:
351 case GL_UNSIGNED_SHORT_5_6_5_REV:
352 return _dri_texformat_rgb565;
353 default:
354 return do32bpt ? _dri_texformat_argb8888 :
355 _dri_texformat_rgb565;
356 }
357
358 case GL_RGBA8:
359 case GL_RGB10_A2:
360 case GL_RGBA12:
361 case GL_RGBA16:
362 return !force16bpt ?
363 radeonChoose8888TexFormat(rmesa, format, type, fbo) :
364 _dri_texformat_argb4444;
365
366 case GL_RGBA4:
367 case GL_RGBA2:
368 return _dri_texformat_argb4444;
369
370 case GL_RGB5_A1:
371 return _dri_texformat_argb1555;
372
373 case GL_RGB8:
374 case GL_RGB10:
375 case GL_RGB12:
376 case GL_RGB16:
377 return !force16bpt ? _dri_texformat_argb8888 :
378 _dri_texformat_rgb565;
379
380 case GL_RGB5:
381 case GL_RGB4:
382 case GL_R3_G3_B2:
383 return _dri_texformat_rgb565;
384
385 case GL_ALPHA:
386 case GL_ALPHA4:
387 case GL_ALPHA8:
388 case GL_ALPHA12:
389 case GL_ALPHA16:
390 case GL_COMPRESSED_ALPHA:
391 /* r200: can't use a8 format since interpreting hw I8 as a8 would result
392 in wrong rgb values (same as alpha value instead of 0). */
393 if (IS_R200_CLASS(rmesa->radeonScreen))
394 return _dri_texformat_al88;
395 else
396 return _dri_texformat_a8;
397 case 1:
398 case GL_LUMINANCE:
399 case GL_LUMINANCE4:
400 case GL_LUMINANCE8:
401 case GL_LUMINANCE12:
402 case GL_LUMINANCE16:
403 case GL_COMPRESSED_LUMINANCE:
404 return _dri_texformat_l8;
405
406 case 2:
407 case GL_LUMINANCE_ALPHA:
408 case GL_LUMINANCE4_ALPHA4:
409 case GL_LUMINANCE6_ALPHA2:
410 case GL_LUMINANCE8_ALPHA8:
411 case GL_LUMINANCE12_ALPHA4:
412 case GL_LUMINANCE12_ALPHA12:
413 case GL_LUMINANCE16_ALPHA16:
414 case GL_COMPRESSED_LUMINANCE_ALPHA:
415 return _dri_texformat_al88;
416
417 case GL_INTENSITY:
418 case GL_INTENSITY4:
419 case GL_INTENSITY8:
420 case GL_INTENSITY12:
421 case GL_INTENSITY16:
422 case GL_COMPRESSED_INTENSITY:
423 return _dri_texformat_i8;
424
425 case GL_YCBCR_MESA:
426 if (type == GL_UNSIGNED_SHORT_8_8_APPLE ||
427 type == GL_UNSIGNED_BYTE)
428 return &_mesa_texformat_ycbcr;
429 else
430 return &_mesa_texformat_ycbcr_rev;
431
432 case GL_RGB_S3TC:
433 case GL_RGB4_S3TC:
434 case GL_COMPRESSED_RGB_S3TC_DXT1_EXT:
435 return &_mesa_texformat_rgb_dxt1;
436
437 case GL_COMPRESSED_RGBA_S3TC_DXT1_EXT:
438 return &_mesa_texformat_rgba_dxt1;
439
440 case GL_RGBA_S3TC:
441 case GL_RGBA4_S3TC:
442 case GL_COMPRESSED_RGBA_S3TC_DXT3_EXT:
443 return &_mesa_texformat_rgba_dxt3;
444
445 case GL_COMPRESSED_RGBA_S3TC_DXT5_EXT:
446 return &_mesa_texformat_rgba_dxt5;
447
448 case GL_ALPHA16F_ARB:
449 return &_mesa_texformat_alpha_float16;
450 case GL_ALPHA32F_ARB:
451 return &_mesa_texformat_alpha_float32;
452 case GL_LUMINANCE16F_ARB:
453 return &_mesa_texformat_luminance_float16;
454 case GL_LUMINANCE32F_ARB:
455 return &_mesa_texformat_luminance_float32;
456 case GL_LUMINANCE_ALPHA16F_ARB:
457 return &_mesa_texformat_luminance_alpha_float16;
458 case GL_LUMINANCE_ALPHA32F_ARB:
459 return &_mesa_texformat_luminance_alpha_float32;
460 case GL_INTENSITY16F_ARB:
461 return &_mesa_texformat_intensity_float16;
462 case GL_INTENSITY32F_ARB:
463 return &_mesa_texformat_intensity_float32;
464 case GL_RGB16F_ARB:
465 return &_mesa_texformat_rgba_float16;
466 case GL_RGB32F_ARB:
467 return &_mesa_texformat_rgba_float32;
468 case GL_RGBA16F_ARB:
469 return &_mesa_texformat_rgba_float16;
470 case GL_RGBA32F_ARB:
471 return &_mesa_texformat_rgba_float32;
472
473 case GL_DEPTH_COMPONENT:
474 case GL_DEPTH_COMPONENT16:
475 case GL_DEPTH_COMPONENT24:
476 case GL_DEPTH_COMPONENT32:
477 case GL_DEPTH_STENCIL_EXT:
478 case GL_DEPTH24_STENCIL8_EXT:
479 return &_mesa_texformat_s8_z24;
480
481 /* EXT_texture_sRGB */
482 case GL_SRGB:
483 case GL_SRGB8:
484 case GL_SRGB_ALPHA:
485 case GL_SRGB8_ALPHA8:
486 case GL_COMPRESSED_SRGB:
487 case GL_COMPRESSED_SRGB_ALPHA:
488 return &_mesa_texformat_srgba8;
489
490 case GL_SLUMINANCE:
491 case GL_SLUMINANCE8:
492 case GL_COMPRESSED_SLUMINANCE:
493 return &_mesa_texformat_sl8;
494
495 case GL_SLUMINANCE_ALPHA:
496 case GL_SLUMINANCE8_ALPHA8:
497 case GL_COMPRESSED_SLUMINANCE_ALPHA:
498 return &_mesa_texformat_sla8;
499
500 default:
501 _mesa_problem(ctx,
502 "unexpected internalFormat 0x%x in %s",
503 (int)internalFormat, __func__);
504 return NULL;
505 }
506
507 return NULL; /* never get here */
508 }
509
510 /**
511 * All glTexImage calls go through this function.
512 */
513 static void radeon_teximage(
514 GLcontext *ctx, int dims,
515 GLint face, GLint level,
516 GLint internalFormat,
517 GLint width, GLint height, GLint depth,
518 GLsizei imageSize,
519 GLenum format, GLenum type, const GLvoid * pixels,
520 const struct gl_pixelstore_attrib *packing,
521 struct gl_texture_object *texObj,
522 struct gl_texture_image *texImage,
523 int compressed)
524 {
525 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
526 radeonTexObj* t = radeon_tex_obj(texObj);
527 radeon_texture_image* image = get_radeon_texture_image(texImage);
528 GLuint dstRowStride;
529 GLint postConvWidth = width;
530 GLint postConvHeight = height;
531 GLuint texelBytes;
532
533 radeon_firevertices(rmesa);
534
535 t->validated = GL_FALSE;
536
537 if (ctx->_ImageTransferState & IMAGE_CONVOLUTION_BIT) {
538 _mesa_adjust_image_for_convolution(ctx, dims, &postConvWidth,
539 &postConvHeight);
540 }
541
542 /* Choose and fill in the texture format for this image */
543 texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type, 0);
544 _mesa_set_fetch_functions(texImage, dims);
545
546 if (texImage->TexFormat->TexelBytes == 0) {
547 texelBytes = 0;
548 texImage->IsCompressed = GL_TRUE;
549 texImage->CompressedSize =
550 ctx->Driver.CompressedTextureSize(ctx, texImage->Width,
551 texImage->Height, texImage->Depth,
552 texImage->TexFormat->MesaFormat);
553 } else {
554 texImage->IsCompressed = GL_FALSE;
555 texImage->CompressedSize = 0;
556
557 texelBytes = texImage->TexFormat->TexelBytes;
558 /* Minimum pitch of 32 bytes */
559 if (postConvWidth * texelBytes < 32) {
560 postConvWidth = 32 / texelBytes;
561 texImage->RowStride = postConvWidth;
562 }
563 if (!image->mt) {
564 assert(texImage->RowStride == postConvWidth);
565 }
566 }
567
568 /* Allocate memory for image */
569 radeonFreeTexImageData(ctx, texImage); /* Mesa core only clears texImage->Data but not image->mt */
570
571 if (t->mt &&
572 t->mt->firstLevel == level &&
573 t->mt->lastLevel == level &&
574 t->mt->target != GL_TEXTURE_CUBE_MAP_ARB &&
575 !radeon_miptree_matches_image(t->mt, texImage, face, level)) {
576 radeon_miptree_unreference(t->mt);
577 t->mt = NULL;
578 }
579
580 if (!t->mt)
581 radeon_try_alloc_miptree(rmesa, t, texImage, face, level);
582 if (t->mt && radeon_miptree_matches_image(t->mt, texImage, face, level)) {
583 radeon_mipmap_level *lvl;
584 image->mt = t->mt;
585 image->mtlevel = level - t->mt->firstLevel;
586 image->mtface = face;
587 radeon_miptree_reference(t->mt);
588 lvl = &image->mt->levels[image->mtlevel];
589 dstRowStride = lvl->rowstride;
590 } else {
591 int size;
592 if (texImage->IsCompressed) {
593 size = texImage->CompressedSize;
594 } else {
595 size = texImage->Width * texImage->Height * texImage->Depth * texImage->TexFormat->TexelBytes;
596 }
597 texImage->Data = _mesa_alloc_texmemory(size);
598 }
599
600 /* Upload texture image; note that the spec allows pixels to be NULL */
601 if (compressed) {
602 pixels = _mesa_validate_pbo_compressed_teximage(
603 ctx, imageSize, pixels, packing, "glCompressedTexImage");
604 } else {
605 pixels = _mesa_validate_pbo_teximage(
606 ctx, dims, width, height, depth,
607 format, type, pixels, packing, "glTexImage");
608 }
609
610 if (pixels) {
611 radeon_teximage_map(image, GL_TRUE);
612
613 if (compressed) {
614 memcpy(texImage->Data, pixels, imageSize);
615 } else {
616 GLuint dstRowStride;
617 GLuint *dstImageOffsets;
618
619 if (image->mt) {
620 radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel];
621 dstRowStride = lvl->rowstride;
622 } else {
623 dstRowStride = texImage->Width * texImage->TexFormat->TexelBytes;
624 }
625
626 if (dims == 3) {
627 int i;
628
629 dstImageOffsets = _mesa_malloc(depth * sizeof(GLuint)) ;
630 if (!dstImageOffsets)
631 _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage");
632
633 for (i = 0; i < depth; ++i) {
634 dstImageOffsets[i] = dstRowStride/texImage->TexFormat->TexelBytes * height * i;
635 }
636 } else {
637 dstImageOffsets = texImage->ImageOffsets;
638 }
639
640 if (!texImage->TexFormat->StoreImage(ctx, dims,
641 texImage->_BaseFormat,
642 texImage->TexFormat,
643 texImage->Data, 0, 0, 0, /* dstX/Y/Zoffset */
644 dstRowStride,
645 dstImageOffsets,
646 width, height, depth,
647 format, type, pixels, packing))
648 _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexImage");
649
650 if (dims == 3)
651 _mesa_free(dstImageOffsets);
652 }
653
654 /* SGIS_generate_mipmap */
655 if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
656 radeon_generate_mipmap(ctx, texObj->Target, texObj);
657 }
658 }
659
660 _mesa_unmap_teximage_pbo(ctx, packing);
661
662 if (pixels)
663 radeon_teximage_unmap(image);
664
665
666 }
667
668 void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level,
669 GLint internalFormat,
670 GLint width, GLint border,
671 GLenum format, GLenum type, const GLvoid * pixels,
672 const struct gl_pixelstore_attrib *packing,
673 struct gl_texture_object *texObj,
674 struct gl_texture_image *texImage)
675 {
676 radeon_teximage(ctx, 1, 0, level, internalFormat, width, 1, 1,
677 0, format, type, pixels, packing, texObj, texImage, 0);
678 }
679
680 void radeonTexImage2D(GLcontext * ctx, GLenum target, GLint level,
681 GLint internalFormat,
682 GLint width, GLint height, GLint border,
683 GLenum format, GLenum type, const GLvoid * pixels,
684 const struct gl_pixelstore_attrib *packing,
685 struct gl_texture_object *texObj,
686 struct gl_texture_image *texImage)
687
688 {
689 GLuint face = radeon_face_for_target(target);
690
691 radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1,
692 0, format, type, pixels, packing, texObj, texImage, 0);
693 }
694
695 void radeonCompressedTexImage2D(GLcontext * ctx, GLenum target,
696 GLint level, GLint internalFormat,
697 GLint width, GLint height, GLint border,
698 GLsizei imageSize, const GLvoid * data,
699 struct gl_texture_object *texObj,
700 struct gl_texture_image *texImage)
701 {
702 GLuint face = radeon_face_for_target(target);
703
704 radeon_teximage(ctx, 2, face, level, internalFormat, width, height, 1,
705 imageSize, 0, 0, data, &ctx->Unpack, texObj, texImage, 1);
706 }
707
708 void radeonTexImage3D(GLcontext * ctx, GLenum target, GLint level,
709 GLint internalFormat,
710 GLint width, GLint height, GLint depth,
711 GLint border,
712 GLenum format, GLenum type, const GLvoid * pixels,
713 const struct gl_pixelstore_attrib *packing,
714 struct gl_texture_object *texObj,
715 struct gl_texture_image *texImage)
716 {
717 radeon_teximage(ctx, 3, 0, level, internalFormat, width, height, depth,
718 0, format, type, pixels, packing, texObj, texImage, 0);
719 }
720
721 /**
722 * Update a subregion of the given texture image.
723 */
724 static void radeon_texsubimage(GLcontext* ctx, int dims, int level,
725 GLint xoffset, GLint yoffset, GLint zoffset,
726 GLsizei width, GLsizei height, GLsizei depth,
727 GLsizei imageSize,
728 GLenum format, GLenum type,
729 const GLvoid * pixels,
730 const struct gl_pixelstore_attrib *packing,
731 struct gl_texture_object *texObj,
732 struct gl_texture_image *texImage,
733 int compressed)
734 {
735 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
736 radeonTexObj* t = radeon_tex_obj(texObj);
737 radeon_texture_image* image = get_radeon_texture_image(texImage);
738
739 radeon_firevertices(rmesa);
740
741 t->validated = GL_FALSE;
742 if (compressed) {
743 pixels = _mesa_validate_pbo_compressed_teximage(
744 ctx, imageSize, pixels, packing, "glCompressedTexImage");
745 } else {
746 pixels = _mesa_validate_pbo_teximage(ctx, dims,
747 width, height, depth, format, type, pixels, packing, "glTexSubImage1D");
748 }
749
750 if (pixels) {
751 GLint dstRowStride;
752 radeon_teximage_map(image, GL_TRUE);
753
754 if (image->mt) {
755 radeon_mipmap_level *lvl = &image->mt->levels[image->mtlevel];
756 dstRowStride = lvl->rowstride;
757 } else {
758 dstRowStride = texImage->RowStride * texImage->TexFormat->TexelBytes;
759 }
760
761 if (compressed) {
762 uint32_t srcRowStride, bytesPerRow, rows;
763 dstRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, texImage->Width);
764 srcRowStride = _mesa_compressed_row_stride(texImage->TexFormat->MesaFormat, width);
765 bytesPerRow = srcRowStride;
766 rows = height / 4;
767
768 copy_rows(texImage->Data, dstRowStride, image->base.Data, srcRowStride, rows,
769 bytesPerRow);
770
771 } else {
772 if (!texImage->TexFormat->StoreImage(ctx, dims, texImage->_BaseFormat,
773 texImage->TexFormat, texImage->Data,
774 xoffset, yoffset, zoffset,
775 dstRowStride,
776 texImage->ImageOffsets,
777 width, height, depth,
778 format, type, pixels, packing))
779 _mesa_error(ctx, GL_OUT_OF_MEMORY, "glTexSubImage");
780 }
781
782 /* GL_SGIS_generate_mipmap */
783 if (level == texObj->BaseLevel && texObj->GenerateMipmap) {
784 radeon_generate_mipmap(ctx, texObj->Target, texObj);
785 }
786 }
787
788 radeon_teximage_unmap(image);
789
790 _mesa_unmap_teximage_pbo(ctx, packing);
791
792
793 }
794
795 void radeonTexSubImage1D(GLcontext * ctx, GLenum target, GLint level,
796 GLint xoffset,
797 GLsizei width,
798 GLenum format, GLenum type,
799 const GLvoid * pixels,
800 const struct gl_pixelstore_attrib *packing,
801 struct gl_texture_object *texObj,
802 struct gl_texture_image *texImage)
803 {
804 radeon_texsubimage(ctx, 1, level, xoffset, 0, 0, width, 1, 1, 0,
805 format, type, pixels, packing, texObj, texImage, 0);
806 }
807
808 void radeonTexSubImage2D(GLcontext * ctx, GLenum target, GLint level,
809 GLint xoffset, GLint yoffset,
810 GLsizei width, GLsizei height,
811 GLenum format, GLenum type,
812 const GLvoid * pixels,
813 const struct gl_pixelstore_attrib *packing,
814 struct gl_texture_object *texObj,
815 struct gl_texture_image *texImage)
816 {
817 radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1,
818 0, format, type, pixels, packing, texObj, texImage,
819 0);
820 }
821
822 void radeonCompressedTexSubImage2D(GLcontext * ctx, GLenum target,
823 GLint level, GLint xoffset,
824 GLint yoffset, GLsizei width,
825 GLsizei height, GLenum format,
826 GLsizei imageSize, const GLvoid * data,
827 struct gl_texture_object *texObj,
828 struct gl_texture_image *texImage)
829 {
830 radeon_texsubimage(ctx, 2, level, xoffset, yoffset, 0, width, height, 1,
831 imageSize, format, 0, data, &ctx->Unpack, texObj, texImage, 1);
832 }
833
834
835 void radeonTexSubImage3D(GLcontext * ctx, GLenum target, GLint level,
836 GLint xoffset, GLint yoffset, GLint zoffset,
837 GLsizei width, GLsizei height, GLsizei depth,
838 GLenum format, GLenum type,
839 const GLvoid * pixels,
840 const struct gl_pixelstore_attrib *packing,
841 struct gl_texture_object *texObj,
842 struct gl_texture_image *texImage)
843 {
844 radeon_texsubimage(ctx, 3, level, xoffset, yoffset, zoffset, width, height, depth, 0,
845 format, type, pixels, packing, texObj, texImage, 0);
846 }
847
848
849
850 /**
851 * Ensure that the given image is stored in the given miptree from now on.
852 */
853 static void migrate_image_to_miptree(radeon_mipmap_tree *mt, radeon_texture_image *image, int face, int level)
854 {
855 radeon_mipmap_level *dstlvl = &mt->levels[level - mt->firstLevel];
856 unsigned char *dest;
857
858 assert(image->mt != mt);
859 assert(dstlvl->width == image->base.Width);
860 assert(dstlvl->height == image->base.Height);
861 assert(dstlvl->depth == image->base.Depth);
862
863
864 radeon_bo_map(mt->bo, GL_TRUE);
865 dest = mt->bo->ptr + dstlvl->faces[face].offset;
866
867 if (image->mt) {
868 /* Format etc. should match, so we really just need a memcpy().
869 * In fact, that memcpy() could be done by the hardware in many
870 * cases, provided that we have a proper memory manager.
871 */
872 radeon_mipmap_level *srclvl = &image->mt->levels[image->mtlevel-image->mt->firstLevel];
873
874 assert(srclvl->size == dstlvl->size);
875 assert(srclvl->rowstride == dstlvl->rowstride);
876
877 radeon_bo_map(image->mt->bo, GL_FALSE);
878
879 memcpy(dest,
880 image->mt->bo->ptr + srclvl->faces[face].offset,
881 dstlvl->size);
882 radeon_bo_unmap(image->mt->bo);
883
884 radeon_miptree_unreference(image->mt);
885 } else {
886 uint32_t srcrowstride;
887 uint32_t height;
888 /* need to confirm this value is correct */
889 if (mt->compressed) {
890 height = image->base.Height / 4;
891 srcrowstride = image->base.RowStride * mt->bpp;
892 } else {
893 height = image->base.Height * image->base.Depth;
894 srcrowstride = image->base.Width * image->base.TexFormat->TexelBytes;
895 }
896
897 // if (mt->tilebits)
898 // WARN_ONCE("%s: tiling not supported yet", __FUNCTION__);
899
900 copy_rows(dest, dstlvl->rowstride, image->base.Data, srcrowstride,
901 height, srcrowstride);
902
903 _mesa_free_texmemory(image->base.Data);
904 image->base.Data = 0;
905 }
906
907 radeon_bo_unmap(mt->bo);
908
909 image->mt = mt;
910 image->mtface = face;
911 image->mtlevel = level;
912 radeon_miptree_reference(image->mt);
913 }
914
915 int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj)
916 {
917 radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
918 radeonTexObj *t = radeon_tex_obj(texObj);
919 radeon_texture_image *baseimage = get_radeon_texture_image(texObj->Image[0][texObj->BaseLevel]);
920 int face, level;
921
922 if (t->validated || t->image_override)
923 return GL_TRUE;
924
925 if (RADEON_DEBUG & DEBUG_TEXTURE)
926 fprintf(stderr, "%s: Validating texture %p now\n", __FUNCTION__, texObj);
927
928 if (baseimage->base.Border > 0)
929 return GL_FALSE;
930
931 /* Ensure a matching miptree exists.
932 *
933 * Differing mipmap trees can result when the app uses TexImage to
934 * change texture dimensions.
935 *
936 * Prefer to use base image's miptree if it
937 * exists, since that most likely contains more valid data (remember
938 * that the base level is usually significantly larger than the rest
939 * of the miptree, so cubemaps are the only possible exception).
940 */
941 if (baseimage->mt &&
942 baseimage->mt != t->mt &&
943 radeon_miptree_matches_texture(baseimage->mt, &t->base)) {
944 radeon_miptree_unreference(t->mt);
945 t->mt = baseimage->mt;
946 radeon_miptree_reference(t->mt);
947 } else if (t->mt && !radeon_miptree_matches_texture(t->mt, &t->base)) {
948 radeon_miptree_unreference(t->mt);
949 t->mt = 0;
950 }
951
952 if (!t->mt) {
953 if (RADEON_DEBUG & DEBUG_TEXTURE)
954 fprintf(stderr, " Allocate new miptree\n");
955 radeon_try_alloc_miptree(rmesa, t, &baseimage->base, 0, texObj->BaseLevel);
956 if (!t->mt) {
957 _mesa_problem(ctx, "r300_validate_texture failed to alloc miptree");
958 return GL_FALSE;
959 }
960 }
961
962 /* Ensure all images are stored in the single main miptree */
963 for(face = 0; face < t->mt->faces; ++face) {
964 for(level = t->mt->firstLevel; level <= t->mt->lastLevel; ++level) {
965 radeon_texture_image *image = get_radeon_texture_image(texObj->Image[face][level]);
966 if (RADEON_DEBUG & DEBUG_TEXTURE)
967 fprintf(stderr, " face %i, level %i... %p vs %p ", face, level, t->mt, image->mt);
968 if (t->mt == image->mt) {
969 if (RADEON_DEBUG & DEBUG_TEXTURE)
970 fprintf(stderr, "OK\n");
971 continue;
972 }
973
974 if (RADEON_DEBUG & DEBUG_TEXTURE)
975 fprintf(stderr, "migrating\n");
976 migrate_image_to_miptree(t->mt, image, face, level);
977 }
978 }
979
980 return GL_TRUE;
981 }
982
983
984 /**
985 * Need to map texture image into memory before copying image data,
986 * then unmap it.
987 */
988 static void
989 radeon_get_tex_image(GLcontext * ctx, GLenum target, GLint level,
990 GLenum format, GLenum type, GLvoid * pixels,
991 struct gl_texture_object *texObj,
992 struct gl_texture_image *texImage, int compressed)
993 {
994 radeon_texture_image *image = get_radeon_texture_image(texImage);
995
996 if (image->mt) {
997 /* Map the texture image read-only */
998 radeon_teximage_map(image, GL_FALSE);
999 } else {
1000 /* Image hasn't been uploaded to a miptree yet */
1001 assert(image->base.Data);
1002 }
1003
1004 if (compressed) {
1005 _mesa_get_compressed_teximage(ctx, target, level, pixels,
1006 texObj, texImage);
1007 } else {
1008 _mesa_get_teximage(ctx, target, level, format, type, pixels,
1009 texObj, texImage);
1010 }
1011
1012 if (image->mt) {
1013 radeon_teximage_unmap(image);
1014 }
1015 }
1016
1017 void
1018 radeonGetTexImage(GLcontext * ctx, GLenum target, GLint level,
1019 GLenum format, GLenum type, GLvoid * pixels,
1020 struct gl_texture_object *texObj,
1021 struct gl_texture_image *texImage)
1022 {
1023 radeon_get_tex_image(ctx, target, level, format, type, pixels,
1024 texObj, texImage, 0);
1025 }
1026
1027 void
1028 radeonGetCompressedTexImage(GLcontext *ctx, GLenum target, GLint level,
1029 GLvoid *pixels,
1030 struct gl_texture_object *texObj,
1031 struct gl_texture_image *texImage)
1032 {
1033 radeon_get_tex_image(ctx, target, level, 0, 0, pixels,
1034 texObj, texImage, 1);
1035 }