1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c,v 1.2 2002/12/21 17:02:16 dawes Exp $ */
2 /**************************************************************************
4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
5 Tungsten Graphics Inc., Cedar Park, Texas.
9 Permission is hereby granted, free of charge, to any person obtaining
10 a copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sublicense, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial
19 portions of the Software.
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 **************************************************************************/
33 * Keith Whitwell <keith@tungstengraphics.com>
38 #include "simple_list.h"
39 #include "radeon_vtxfmt.h"
41 #if defined(USE_X86_ASM)
43 #define EXTERN( FUNC ) \
44 extern const char *FUNC; \
45 extern const char *FUNC##_end
47 EXTERN ( _x86_Attribute2fv
);
48 EXTERN ( _x86_Attribute2f
);
49 EXTERN ( _x86_Attribute3fv
);
50 EXTERN ( _x86_Attribute3f
);
51 EXTERN ( _x86_Vertex3fv_6
);
52 EXTERN ( _x86_Vertex3fv_8
);
53 EXTERN ( _x86_Vertex3fv
);
54 EXTERN ( _x86_Vertex3f_4
);
55 EXTERN ( _x86_Vertex3f_6
);
56 EXTERN ( _x86_Vertex3f
);
57 EXTERN ( _x86_Color4ubv_ub
);
58 EXTERN ( _x86_Color4ubv_4f
);
59 EXTERN ( _x86_Color4ub_ub
);
60 EXTERN ( _x86_MultiTexCoord2fv
);
61 EXTERN ( _x86_MultiTexCoord2fv_2
);
62 EXTERN ( _x86_MultiTexCoord2f
);
63 EXTERN ( _x86_MultiTexCoord2f_2
);
66 /* Build specialized versions of the immediate calls on the fly for
67 * the current state. Generic x86 versions.
70 struct dynfn
*radeon_makeX86Vertex3f( GLcontext
*ctx
, int key
)
72 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
73 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
75 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
76 fprintf(stderr
, "%s 0x%08x %d\n", __FUNCTION__
, key
, rmesa
->vb
.vertex_size
);
78 switch (rmesa
->vb
.vertex_size
) {
81 DFN ( _x86_Vertex3f_4
, rmesa
->vb
.dfn_cache
.Vertex3f
);
82 FIXUP(dfn
->code
, 2, 0x0, (int)&rmesa
->vb
.dmaptr
);
83 FIXUP(dfn
->code
, 25, 0x0, (int)&rmesa
->vb
.vertex
[3]);
84 FIXUP(dfn
->code
, 36, 0x0, (int)&rmesa
->vb
.counter
);
85 FIXUP(dfn
->code
, 46, 0x0, (int)&rmesa
->vb
.dmaptr
);
86 FIXUP(dfn
->code
, 51, 0x0, (int)&rmesa
->vb
.counter
);
87 FIXUP(dfn
->code
, 60, 0x0, (int)&rmesa
->vb
.notify
);
92 DFN ( _x86_Vertex3f_6
, rmesa
->vb
.dfn_cache
.Vertex3f
);
93 FIXUP(dfn
->code
, 3, 0x0, (int)&rmesa
->vb
.dmaptr
);
94 FIXUP(dfn
->code
, 28, 0x0, (int)&rmesa
->vb
.vertex
[3]);
95 FIXUP(dfn
->code
, 34, 0x0, (int)&rmesa
->vb
.vertex
[4]);
96 FIXUP(dfn
->code
, 40, 0x0, (int)&rmesa
->vb
.vertex
[5]);
97 FIXUP(dfn
->code
, 57, 0x0, (int)&rmesa
->vb
.counter
);
98 FIXUP(dfn
->code
, 63, 0x0, (int)&rmesa
->vb
.dmaptr
);
99 FIXUP(dfn
->code
, 70, 0x0, (int)&rmesa
->vb
.counter
);
100 FIXUP(dfn
->code
, 79, 0x0, (int)&rmesa
->vb
.notify
);
105 DFN ( _x86_Vertex3f
, rmesa
->vb
.dfn_cache
.Vertex3f
);
106 FIXUP(dfn
->code
, 3, 0x0, (int)&rmesa
->vb
.vertex
[3]);
107 FIXUP(dfn
->code
, 9, 0x0, (int)&rmesa
->vb
.dmaptr
);
108 FIXUP(dfn
->code
, 37, 0x0, rmesa
->vb
.vertex_size
-3);
109 FIXUP(dfn
->code
, 44, 0x0, (int)&rmesa
->vb
.counter
);
110 FIXUP(dfn
->code
, 50, 0x0, (int)&rmesa
->vb
.dmaptr
);
111 FIXUP(dfn
->code
, 56, 0x0, (int)&rmesa
->vb
.counter
);
112 FIXUP(dfn
->code
, 67, 0x0, (int)&rmesa
->vb
.notify
);
122 struct dynfn
*radeon_makeX86Vertex3fv( GLcontext
*ctx
, int key
)
124 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
125 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
127 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
128 fprintf(stderr
, "%s 0x%08x %d\n", __FUNCTION__
, key
, rmesa
->vb
.vertex_size
);
130 switch (rmesa
->vb
.vertex_size
) {
133 DFN ( _x86_Vertex3fv_6
, rmesa
->vb
.dfn_cache
.Vertex3fv
);
134 FIXUP(dfn
->code
, 1, 0x00000000, (int)&rmesa
->vb
.dmaptr
);
135 FIXUP(dfn
->code
, 27, 0x0000001c, (int)&rmesa
->vb
.vertex
[3]);
136 FIXUP(dfn
->code
, 33, 0x00000020, (int)&rmesa
->vb
.vertex
[4]);
137 FIXUP(dfn
->code
, 45, 0x00000024, (int)&rmesa
->vb
.vertex
[5]);
138 FIXUP(dfn
->code
, 56, 0x00000000, (int)&rmesa
->vb
.dmaptr
);
139 FIXUP(dfn
->code
, 61, 0x00000004, (int)&rmesa
->vb
.counter
);
140 FIXUP(dfn
->code
, 67, 0x00000004, (int)&rmesa
->vb
.counter
);
141 FIXUP(dfn
->code
, 76, 0x00000008, (int)&rmesa
->vb
.notify
);
148 DFN ( _x86_Vertex3fv_8
, rmesa
->vb
.dfn_cache
.Vertex3fv
);
149 FIXUP(dfn
->code
, 1, 0x00000000, (int)&rmesa
->vb
.dmaptr
);
150 FIXUP(dfn
->code
, 27, 0x0000001c, (int)&rmesa
->vb
.vertex
[3]);
151 FIXUP(dfn
->code
, 33, 0x00000020, (int)&rmesa
->vb
.vertex
[4]);
152 FIXUP(dfn
->code
, 45, 0x0000001c, (int)&rmesa
->vb
.vertex
[5]);
153 FIXUP(dfn
->code
, 51, 0x00000020, (int)&rmesa
->vb
.vertex
[6]);
154 FIXUP(dfn
->code
, 63, 0x00000024, (int)&rmesa
->vb
.vertex
[7]);
155 FIXUP(dfn
->code
, 74, 0x00000000, (int)&rmesa
->vb
.dmaptr
);
156 FIXUP(dfn
->code
, 79, 0x00000004, (int)&rmesa
->vb
.counter
);
157 FIXUP(dfn
->code
, 85, 0x00000004, (int)&rmesa
->vb
.counter
);
158 FIXUP(dfn
->code
, 94, 0x00000008, (int)&rmesa
->vb
.notify
);
166 DFN ( _x86_Vertex3fv
, rmesa
->vb
.dfn_cache
.Vertex3fv
);
167 FIXUP(dfn
->code
, 8, 0x01010101, (int)&rmesa
->vb
.dmaptr
);
168 FIXUP(dfn
->code
, 32, 0x00000006, rmesa
->vb
.vertex_size
-3);
169 FIXUP(dfn
->code
, 37, 0x00000058, (int)&rmesa
->vb
.vertex
[3]);
170 FIXUP(dfn
->code
, 45, 0x01010101, (int)&rmesa
->vb
.dmaptr
);
171 FIXUP(dfn
->code
, 50, 0x02020202, (int)&rmesa
->vb
.counter
);
172 FIXUP(dfn
->code
, 58, 0x02020202, (int)&rmesa
->vb
.counter
);
173 FIXUP(dfn
->code
, 67, 0x0, (int)&rmesa
->vb
.notify
);
181 static struct dynfn
*
182 radeon_makeX86Attribute2fv( struct dynfn
* cache
, int key
,
183 const char * name
, void * dest
)
185 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
187 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
188 fprintf(stderr
, "%s 0x%08x\n", name
, key
);
190 DFN ( _x86_Attribute2fv
, (*cache
) );
191 FIXUP(dfn
->code
, 11, 0x0, (int)dest
);
192 FIXUP(dfn
->code
, 16, 0x4, 4+(int)dest
);
197 static struct dynfn
*
198 radeon_makeX86Attribute2f( struct dynfn
* cache
, int key
,
199 const char * name
, void * dest
)
201 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
203 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
204 fprintf(stderr
, "%s 0x%08x\n", name
, key
);
206 DFN ( _x86_Attribute2f
, (*cache
) );
207 FIXUP(dfn
->code
, 1, 0x0, (int)dest
);
213 static struct dynfn
*
214 radeon_makeX86Attribute3fv( struct dynfn
* cache
, int key
,
215 const char * name
, void * dest
)
217 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
219 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
220 fprintf(stderr
, "%s 0x%08x\n", name
, key
);
222 DFN ( _x86_Attribute3fv
, (*cache
) );
223 FIXUP(dfn
->code
, 14, 0x0, (int)dest
);
224 FIXUP(dfn
->code
, 20, 0x4, 4+(int)dest
);
225 FIXUP(dfn
->code
, 25, 0x8, 8+(int)dest
);
230 static struct dynfn
*
231 radeon_makeX86Attribute3f( struct dynfn
* cache
, int key
,
232 const char * name
, void * dest
)
234 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
236 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
237 fprintf(stderr
, "%s 0x%08x\n", name
, key
);
239 DFN ( _x86_Attribute3f
, (*cache
) );
240 FIXUP(dfn
->code
, 14, 0x0, (int)dest
);
241 FIXUP(dfn
->code
, 20, 0x4, 4+(int)dest
);
242 FIXUP(dfn
->code
, 25, 0x8, 8+(int)dest
);
247 struct dynfn
*radeon_makeX86Normal3fv( GLcontext
*ctx
, int key
)
249 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
251 return radeon_makeX86Attribute3fv( & rmesa
->vb
.dfn_cache
.Normal3fv
, key
,
252 __FUNCTION__
, rmesa
->vb
.normalptr
);
255 struct dynfn
*radeon_makeX86Normal3f( GLcontext
*ctx
, int key
)
257 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
259 return radeon_makeX86Attribute3f( & rmesa
->vb
.dfn_cache
.Normal3f
, key
,
260 __FUNCTION__
, rmesa
->vb
.normalptr
);
263 struct dynfn
*radeon_makeX86Color4ubv( GLcontext
*ctx
, int key
)
265 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
266 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
269 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
270 fprintf(stderr
, "%s 0x%08x\n", __FUNCTION__
, key
);
272 if (key
& RADEON_CP_VC_FRMT_PKCOLOR
) {
273 DFN ( _x86_Color4ubv_ub
, rmesa
->vb
.dfn_cache
.Color4ubv
);
274 FIXUP(dfn
->code
, 5, 0x12345678, (int)rmesa
->vb
.colorptr
);
279 DFN ( _x86_Color4ubv_4f
, rmesa
->vb
.dfn_cache
.Color4ubv
);
280 FIXUP(dfn
->code
, 2, 0x00000000, (int)_mesa_ubyte_to_float_color_tab
);
281 FIXUP(dfn
->code
, 27, 0xdeadbeaf, (int)rmesa
->vb
.floatcolorptr
);
282 FIXUP(dfn
->code
, 33, 0xdeadbeaf, (int)rmesa
->vb
.floatcolorptr
+4);
283 FIXUP(dfn
->code
, 55, 0xdeadbeaf, (int)rmesa
->vb
.floatcolorptr
+8);
284 FIXUP(dfn
->code
, 61, 0xdeadbeaf, (int)rmesa
->vb
.floatcolorptr
+12);
289 struct dynfn
*radeon_makeX86Color4ub( GLcontext
*ctx
, int key
)
291 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
292 fprintf(stderr
, "%s 0x%08x\n", __FUNCTION__
, key
);
294 if (key
& RADEON_CP_VC_FRMT_PKCOLOR
) {
295 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
296 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
298 DFN ( _x86_Color4ub_ub
, rmesa
->vb
.dfn_cache
.Color4ub
);
299 FIXUP(dfn
->code
, 18, 0x0, (int)rmesa
->vb
.colorptr
);
300 FIXUP(dfn
->code
, 24, 0x0, (int)rmesa
->vb
.colorptr
+1);
301 FIXUP(dfn
->code
, 30, 0x0, (int)rmesa
->vb
.colorptr
+2);
302 FIXUP(dfn
->code
, 36, 0x0, (int)rmesa
->vb
.colorptr
+3);
310 struct dynfn
*radeon_makeX86Color3fv( GLcontext
*ctx
, int key
)
312 if (key
& (RADEON_CP_VC_FRMT_PKCOLOR
|RADEON_CP_VC_FRMT_FPALPHA
))
316 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
318 return radeon_makeX86Attribute3fv( & rmesa
->vb
.dfn_cache
.Color3fv
, key
,
319 __FUNCTION__
, rmesa
->vb
.floatcolorptr
);
323 struct dynfn
*radeon_makeX86Color3f( GLcontext
*ctx
, int key
)
325 if (key
& (RADEON_CP_VC_FRMT_PKCOLOR
|RADEON_CP_VC_FRMT_FPALPHA
))
329 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
331 return radeon_makeX86Attribute3f( & rmesa
->vb
.dfn_cache
.Color3f
, key
,
332 __FUNCTION__
, rmesa
->vb
.floatcolorptr
);
338 struct dynfn
*radeon_makeX86TexCoord2fv( GLcontext
*ctx
, int key
)
340 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
342 return radeon_makeX86Attribute2fv( & rmesa
->vb
.dfn_cache
.TexCoord2fv
, key
,
343 __FUNCTION__
, rmesa
->vb
.texcoordptr
[0] );
346 struct dynfn
*radeon_makeX86TexCoord2f( GLcontext
*ctx
, int key
)
348 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
350 return radeon_makeX86Attribute2f( & rmesa
->vb
.dfn_cache
.TexCoord2f
, key
,
351 __FUNCTION__
, rmesa
->vb
.texcoordptr
[0] );
354 #if 0 /* Temporarily disabled - probably needs adjustments for more than 2 tex units -rs */
355 struct dynfn
*radeon_makeX86MultiTexCoord2fvARB( GLcontext
*ctx
, int key
)
357 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
358 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
360 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
361 fprintf(stderr
, "%s 0x%08x\n", __FUNCTION__
, key
);
363 if ((key
& (RADEON_CP_VC_FRMT_ST0
|RADEON_CP_VC_FRMT_ST1
)) ==
364 (RADEON_CP_VC_FRMT_ST0
|RADEON_CP_VC_FRMT_ST1
)) {
365 DFN ( _x86_MultiTexCoord2fv
, rmesa
->vb
.dfn_cache
.MultiTexCoord2fvARB
);
366 FIXUP(dfn
->code
, 21, 0xdeadbeef, (int)rmesa
->vb
.texcoordptr
[0]);
367 FIXUP(dfn
->code
, 27, 0xdeadbeef, (int)rmesa
->vb
.texcoordptr
[0]+4);
369 DFN ( _x86_MultiTexCoord2fv_2
, rmesa
->vb
.dfn_cache
.MultiTexCoord2fvARB
);
370 FIXUP(dfn
->code
, 14, 0x0, (int)rmesa
->vb
.texcoordptr
);
375 struct dynfn
*radeon_makeX86MultiTexCoord2fARB( GLcontext
*ctx
,
378 struct dynfn
*dfn
= MALLOC_STRUCT( dynfn
);
379 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
381 if (RADEON_DEBUG
& DEBUG_CODEGEN
)
382 fprintf(stderr
, "%s 0x%08x\n", __FUNCTION__
, key
);
384 if ((key
& (RADEON_CP_VC_FRMT_ST0
|RADEON_CP_VC_FRMT_ST1
)) ==
385 (RADEON_CP_VC_FRMT_ST0
|RADEON_CP_VC_FRMT_ST1
)) {
386 DFN ( _x86_MultiTexCoord2f
, rmesa
->vb
.dfn_cache
.MultiTexCoord2fARB
);
387 FIXUP(dfn
->code
, 20, 0xdeadbeef, (int)rmesa
->vb
.texcoordptr
[0]);
388 FIXUP(dfn
->code
, 26, 0xdeadbeef, (int)rmesa
->vb
.texcoordptr
[0]+4);
391 /* Note: this might get generated multiple times, even though the
392 * actual emitted code is the same.
394 DFN ( _x86_MultiTexCoord2f_2
, rmesa
->vb
.dfn_cache
.MultiTexCoord2fARB
);
395 FIXUP(dfn
->code
, 18, 0x0, (int)rmesa
->vb
.texcoordptr
);
401 void radeonInitX86Codegen( struct dfn_generators
*gen
)
403 gen
->Vertex3f
= radeon_makeX86Vertex3f
;
404 gen
->Vertex3fv
= radeon_makeX86Vertex3fv
;
405 gen
->Color4ub
= radeon_makeX86Color4ub
; /* PKCOLOR only */
406 gen
->Color4ubv
= radeon_makeX86Color4ubv
; /* PKCOLOR only */
407 gen
->Normal3f
= radeon_makeX86Normal3f
;
408 gen
->Normal3fv
= radeon_makeX86Normal3fv
;
409 gen
->TexCoord2f
= radeon_makeX86TexCoord2f
;
410 gen
->TexCoord2fv
= radeon_makeX86TexCoord2fv
;
411 #if 0 /* Temporarily disabled - probably needs adjustments for more than 2 tex units -rs */
412 gen
->MultiTexCoord2fARB
= radeon_makeX86MultiTexCoord2fARB
;
413 gen
->MultiTexCoord2fvARB
= radeon_makeX86MultiTexCoord2fvARB
;
415 gen
->Color3f
= radeon_makeX86Color3f
;
416 gen
->Color3fv
= radeon_makeX86Color3fv
;
420 /* gen->Vertex2f = radeon_makeX86Vertex2f; */
421 /* gen->Vertex2fv = radeon_makeX86Vertex2fv; */
422 /* gen->Color3ub = radeon_makeX86Color3ub; */
423 /* gen->Color3ubv = radeon_makeX86Color3ubv; */
424 /* gen->Color4f = radeon_makeX86Color4f; */
425 /* gen->Color4fv = radeon_makeX86Color4fv; */
426 /* gen->TexCoord1f = radeon_makeX86TexCoord1f; */
427 /* gen->TexCoord1fv = radeon_makeX86TexCoord1fv; */
428 /* gen->MultiTexCoord1fARB = radeon_makeX86MultiTexCoord1fARB; */
429 /* gen->MultiTexCoord1fvARB = radeon_makeX86MultiTexCoord1fvARB; */
435 void radeonInitX86Codegen( struct dfn_generators
*gen
)