src/mesa/drivers/dri/radeon/radeon_vtxfmt_x86.c

   1 /* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_vtxfmt_x86.c,v 1.2 2002/12/21 17:02:16 dawes Exp $ */
   2 /**************************************************************************
   3
   4 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
   5                      Tungsten Graphics Inc., Cedar Park, Texas.
   6
   7 All Rights Reserved.
   8
   9 Permission is hereby granted, free of charge, to any person obtaining
  10 a copy of this software and associated documentation files (the
  11 "Software"), to deal in the Software without restriction, including
  12 without limitation the rights to use, copy, modify, merge, publish,
  13 distribute, sublicense, and/or sell copies of the Software, and to
  14 permit persons to whom the Software is furnished to do so, subject to
  15 the following conditions:
  16
  17 The above copyright notice and this permission notice (including the
  18 next paragraph) shall be included in all copies or substantial
  19 portions of the Software.
  20
  21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  22 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  24 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  25 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  26 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  27 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  28
  29 **************************************************************************/
  30
  31 /*
  32  * Authors:
  33  *   Keith Whitwell <keith@tungstengraphics.com>
  34  */
  35
  36 #include "glheader.h"
  37 #include "imports.h"
  38 #include "simple_list.h"
  39 #include "radeon_vtxfmt.h"
  40
  41 #if defined(USE_X86_ASM)
  42
  43 #define EXTERN( FUNC )          \
  44 extern const char *FUNC;        \
  45 extern const char *FUNC##_end
  46
  47 EXTERN ( _x86_Attribute2fv );
  48 EXTERN ( _x86_Attribute2f );
  49 EXTERN ( _x86_Attribute3fv );
  50 EXTERN ( _x86_Attribute3f );
  51 EXTERN ( _x86_Vertex3fv_6 );
  52 EXTERN ( _x86_Vertex3fv_8 );
  53 EXTERN ( _x86_Vertex3fv );
  54 EXTERN ( _x86_Vertex3f_4 );
  55 EXTERN ( _x86_Vertex3f_6 );
  56 EXTERN ( _x86_Vertex3f );
  57 EXTERN ( _x86_Color4ubv_ub );
  58 EXTERN ( _x86_Color4ubv_4f );
  59 EXTERN ( _x86_Color4ub_ub );
  60 EXTERN ( _x86_MultiTexCoord2fv );
  61 EXTERN ( _x86_MultiTexCoord2fv_2 );
  62 EXTERN ( _x86_MultiTexCoord2f );
  63 EXTERN ( _x86_MultiTexCoord2f_2 );
  64
  65
  66 /* Build specialized versions of the immediate calls on the fly for
  67  * the current state.  Generic x86 versions.
  68  */
  69
  70 struct dynfn *radeon_makeX86Vertex3f( GLcontext *ctx, int key )
  71 {
  72    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
  73    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
  74
  75    if (RADEON_DEBUG & DEBUG_CODEGEN)
  76       fprintf(stderr, "%s 0x%08x %d\n", __FUNCTION__, key, rmesa->vb.vertex_size );
  77
  78    switch (rmesa->vb.vertex_size) {
  79    case 4: {
  80
  81       DFN ( _x86_Vertex3f_4, rmesa->vb.dfn_cache.Vertex3f );
  82       FIXUP(dfn->code, 2, 0x0, (int)&rmesa->vb.dmaptr);
  83       FIXUP(dfn->code, 25, 0x0, (int)&rmesa->vb.vertex[3]);
  84       FIXUP(dfn->code, 36, 0x0, (int)&rmesa->vb.counter);
  85       FIXUP(dfn->code, 46, 0x0, (int)&rmesa->vb.dmaptr);
  86       FIXUP(dfn->code, 51, 0x0, (int)&rmesa->vb.counter);
  87       FIXUP(dfn->code, 60, 0x0, (int)&rmesa->vb.notify);
  88       break;
  89    }
  90    case 6: {
  91
  92       DFN ( _x86_Vertex3f_6, rmesa->vb.dfn_cache.Vertex3f );
  93       FIXUP(dfn->code, 3, 0x0, (int)&rmesa->vb.dmaptr);
  94       FIXUP(dfn->code, 28, 0x0, (int)&rmesa->vb.vertex[3]);
  95       FIXUP(dfn->code, 34, 0x0, (int)&rmesa->vb.vertex[4]);
  96       FIXUP(dfn->code, 40, 0x0, (int)&rmesa->vb.vertex[5]);
  97       FIXUP(dfn->code, 57, 0x0, (int)&rmesa->vb.counter);
  98       FIXUP(dfn->code, 63, 0x0, (int)&rmesa->vb.dmaptr);
  99       FIXUP(dfn->code, 70, 0x0, (int)&rmesa->vb.counter);
 100       FIXUP(dfn->code, 79, 0x0, (int)&rmesa->vb.notify);
 101       break;
 102    }
 103    default: {
 104
 105       DFN ( _x86_Vertex3f, rmesa->vb.dfn_cache.Vertex3f );
 106       FIXUP(dfn->code, 3, 0x0, (int)&rmesa->vb.vertex[3]);
 107       FIXUP(dfn->code, 9, 0x0, (int)&rmesa->vb.dmaptr);
 108       FIXUP(dfn->code, 37, 0x0, rmesa->vb.vertex_size-3);
 109       FIXUP(dfn->code, 44, 0x0, (int)&rmesa->vb.counter);
 110       FIXUP(dfn->code, 50, 0x0, (int)&rmesa->vb.dmaptr);
 111       FIXUP(dfn->code, 56, 0x0, (int)&rmesa->vb.counter);
 112       FIXUP(dfn->code, 67, 0x0, (int)&rmesa->vb.notify);
 113    break;
 114    }
 115    }
 116
 117    return dfn;
 118 }
 119
 120
 121
 122 struct dynfn *radeon_makeX86Vertex3fv( GLcontext *ctx, int key )
 123 {
 124    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 125    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 126
 127    if (RADEON_DEBUG & DEBUG_CODEGEN)
 128       fprintf(stderr, "%s 0x%08x %d\n", __FUNCTION__, key, rmesa->vb.vertex_size );
 129
 130    switch (rmesa->vb.vertex_size) {
 131    case 6: {
 132
 133       DFN ( _x86_Vertex3fv_6, rmesa->vb.dfn_cache.Vertex3fv );
 134       FIXUP(dfn->code, 1, 0x00000000, (int)&rmesa->vb.dmaptr);
 135       FIXUP(dfn->code, 27, 0x0000001c, (int)&rmesa->vb.vertex[3]);
 136       FIXUP(dfn->code, 33, 0x00000020, (int)&rmesa->vb.vertex[4]);
 137       FIXUP(dfn->code, 45, 0x00000024, (int)&rmesa->vb.vertex[5]);
 138       FIXUP(dfn->code, 56, 0x00000000, (int)&rmesa->vb.dmaptr);
 139       FIXUP(dfn->code, 61, 0x00000004, (int)&rmesa->vb.counter);
 140       FIXUP(dfn->code, 67, 0x00000004, (int)&rmesa->vb.counter);
 141       FIXUP(dfn->code, 76, 0x00000008, (int)&rmesa->vb.notify);
 142       break;
 143    }
 144
 145
 146    case 8: {
 147
 148       DFN ( _x86_Vertex3fv_8, rmesa->vb.dfn_cache.Vertex3fv );
 149       FIXUP(dfn->code, 1, 0x00000000, (int)&rmesa->vb.dmaptr);
 150       FIXUP(dfn->code, 27, 0x0000001c, (int)&rmesa->vb.vertex[3]);
 151       FIXUP(dfn->code, 33, 0x00000020, (int)&rmesa->vb.vertex[4]);
 152       FIXUP(dfn->code, 45, 0x0000001c, (int)&rmesa->vb.vertex[5]);
 153       FIXUP(dfn->code, 51, 0x00000020, (int)&rmesa->vb.vertex[6]);
 154       FIXUP(dfn->code, 63, 0x00000024, (int)&rmesa->vb.vertex[7]);
 155       FIXUP(dfn->code, 74, 0x00000000, (int)&rmesa->vb.dmaptr);
 156       FIXUP(dfn->code, 79, 0x00000004, (int)&rmesa->vb.counter);
 157       FIXUP(dfn->code, 85, 0x00000004, (int)&rmesa->vb.counter);
 158       FIXUP(dfn->code, 94, 0x00000008, (int)&rmesa->vb.notify);
 159       break;
 160    }
 161
 162
 163
 164    default: {
 165
 166       DFN ( _x86_Vertex3fv, rmesa->vb.dfn_cache.Vertex3fv );
 167       FIXUP(dfn->code, 8, 0x01010101, (int)&rmesa->vb.dmaptr);
 168       FIXUP(dfn->code, 32, 0x00000006, rmesa->vb.vertex_size-3);
 169       FIXUP(dfn->code, 37, 0x00000058, (int)&rmesa->vb.vertex[3]);
 170       FIXUP(dfn->code, 45, 0x01010101, (int)&rmesa->vb.dmaptr);
 171       FIXUP(dfn->code, 50, 0x02020202, (int)&rmesa->vb.counter);
 172       FIXUP(dfn->code, 58, 0x02020202, (int)&rmesa->vb.counter);
 173       FIXUP(dfn->code, 67, 0x0, (int)&rmesa->vb.notify);
 174    break;
 175    }
 176    }
 177
 178    return dfn;
 179 }
 180
 181 static struct dynfn *
 182 radeon_makeX86Attribute2fv( struct dynfn * cache, int key,
 183                             const char * name, void * dest )
 184 {
 185    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 186
 187    if (RADEON_DEBUG & DEBUG_CODEGEN)
 188       fprintf(stderr, "%s 0x%08x\n", name, key );
 189
 190    DFN ( _x86_Attribute2fv, (*cache) );
 191    FIXUP(dfn->code, 11, 0x0, (int)dest);
 192    FIXUP(dfn->code, 16, 0x4, 4+(int)dest);
 193
 194    return dfn;
 195 }
 196
 197 static struct dynfn *
 198 radeon_makeX86Attribute2f( struct dynfn * cache, int key,
 199                            const char * name, void * dest )
 200 {
 201    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 202
 203    if (RADEON_DEBUG & DEBUG_CODEGEN)
 204       fprintf(stderr, "%s 0x%08x\n", name, key );
 205
 206    DFN ( _x86_Attribute2f, (*cache) );
 207    FIXUP(dfn->code, 1, 0x0, (int)dest);
 208
 209    return dfn;
 210 }
 211
 212
 213 static struct dynfn *
 214 radeon_makeX86Attribute3fv( struct dynfn * cache, int key,
 215                             const char * name, void * dest )
 216 {
 217    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 218
 219    if (RADEON_DEBUG & DEBUG_CODEGEN)
 220       fprintf(stderr, "%s 0x%08x\n", name, key );
 221
 222    DFN ( _x86_Attribute3fv, (*cache) );
 223    FIXUP(dfn->code, 14, 0x0, (int)dest);
 224    FIXUP(dfn->code, 20, 0x4, 4+(int)dest);
 225    FIXUP(dfn->code, 25, 0x8, 8+(int)dest);
 226
 227    return dfn;
 228 }
 229
 230 static struct dynfn *
 231 radeon_makeX86Attribute3f( struct dynfn * cache, int key,
 232                          const char * name, void * dest )
 233 {
 234    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 235
 236    if (RADEON_DEBUG & DEBUG_CODEGEN)
 237       fprintf(stderr, "%s 0x%08x\n", name, key );
 238
 239    DFN ( _x86_Attribute3f, (*cache) );
 240    FIXUP(dfn->code, 14, 0x0, (int)dest);
 241    FIXUP(dfn->code, 20, 0x4, 4+(int)dest);
 242    FIXUP(dfn->code, 25, 0x8, 8+(int)dest);
 243
 244    return dfn;
 245 }
 246
 247 struct dynfn *radeon_makeX86Normal3fv( GLcontext *ctx, int key )
 248 {
 249    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 250
 251    return radeon_makeX86Attribute3fv( & rmesa->vb.dfn_cache.Normal3fv, key,
 252                                       __FUNCTION__, rmesa->vb.normalptr );
 253 }
 254
 255 struct dynfn *radeon_makeX86Normal3f( GLcontext *ctx, int key )
 256 {
 257    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 258
 259    return radeon_makeX86Attribute3f( & rmesa->vb.dfn_cache.Normal3f, key,
 260                                      __FUNCTION__, rmesa->vb.normalptr );
 261 }
 262
 263 struct dynfn *radeon_makeX86Color4ubv( GLcontext *ctx, int key )
 264 {
 265    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 266    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 267
 268
 269    if (RADEON_DEBUG & DEBUG_CODEGEN)
 270       fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
 271
 272    if (key & RADEON_CP_VC_FRMT_PKCOLOR) {
 273       DFN ( _x86_Color4ubv_ub, rmesa->vb.dfn_cache.Color4ubv);
 274       FIXUP(dfn->code, 5, 0x12345678, (int)rmesa->vb.colorptr);
 275       return dfn;
 276    }
 277    else {
 278
 279       DFN ( _x86_Color4ubv_4f, rmesa->vb.dfn_cache.Color4ubv);
 280       FIXUP(dfn->code, 2, 0x00000000, (int)_mesa_ubyte_to_float_color_tab);
 281       FIXUP(dfn->code, 27, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr);
 282       FIXUP(dfn->code, 33, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr+4);
 283       FIXUP(dfn->code, 55, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr+8);
 284       FIXUP(dfn->code, 61, 0xdeadbeaf, (int)rmesa->vb.floatcolorptr+12);
 285       return dfn;
 286    }
 287 }
 288
 289 struct dynfn *radeon_makeX86Color4ub( GLcontext *ctx, int key )
 290 {
 291    if (RADEON_DEBUG & DEBUG_CODEGEN)
 292       fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
 293
 294    if (key & RADEON_CP_VC_FRMT_PKCOLOR) {
 295       struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 296       radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 297
 298       DFN ( _x86_Color4ub_ub, rmesa->vb.dfn_cache.Color4ub );
 299       FIXUP(dfn->code, 18, 0x0, (int)rmesa->vb.colorptr);
 300       FIXUP(dfn->code, 24, 0x0, (int)rmesa->vb.colorptr+1);
 301       FIXUP(dfn->code, 30, 0x0, (int)rmesa->vb.colorptr+2);
 302       FIXUP(dfn->code, 36, 0x0, (int)rmesa->vb.colorptr+3);
 303       return dfn;
 304    }
 305    else
 306       return 0;
 307 }
 308
 309
 310 struct dynfn *radeon_makeX86Color3fv( GLcontext *ctx, int key )
 311 {
 312    if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
 313       return 0;
 314    else
 315    {
 316       radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 317
 318       return radeon_makeX86Attribute3fv( & rmesa->vb.dfn_cache.Color3fv, key,
 319                                          __FUNCTION__, rmesa->vb.floatcolorptr );
 320    }
 321 }
 322
 323 struct dynfn *radeon_makeX86Color3f( GLcontext *ctx, int key )
 324 {
 325    if (key & (RADEON_CP_VC_FRMT_PKCOLOR|RADEON_CP_VC_FRMT_FPALPHA))
 326       return 0;
 327    else
 328    {
 329       radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 330
 331       return radeon_makeX86Attribute3f( & rmesa->vb.dfn_cache.Color3f, key,
 332                                         __FUNCTION__, rmesa->vb.floatcolorptr );
 333    }
 334 }
 335
 336
 337
 338 struct dynfn *radeon_makeX86TexCoord2fv( GLcontext *ctx, int key )
 339 {
 340    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 341
 342    return radeon_makeX86Attribute2fv( & rmesa->vb.dfn_cache.TexCoord2fv, key,
 343                                       __FUNCTION__, rmesa->vb.texcoordptr[0] );
 344 }
 345
 346 struct dynfn *radeon_makeX86TexCoord2f( GLcontext *ctx, int key )
 347 {
 348    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 349
 350    return radeon_makeX86Attribute2f( & rmesa->vb.dfn_cache.TexCoord2f, key,
 351                                      __FUNCTION__, rmesa->vb.texcoordptr[0] );
 352 }
 353
 354 struct dynfn *radeon_makeX86MultiTexCoord2fvARB( GLcontext *ctx, int key )
 355 {
 356    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 357    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 358
 359    if (RADEON_DEBUG & DEBUG_CODEGEN)
 360       fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
 361
 362    if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
 363       (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
 364       DFN ( _x86_MultiTexCoord2fv, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
 365       FIXUP(dfn->code, 21, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
 366       FIXUP(dfn->code, 27, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]+4);
 367    } else {
 368       DFN ( _x86_MultiTexCoord2fv_2, rmesa->vb.dfn_cache.MultiTexCoord2fvARB );
 369       FIXUP(dfn->code, 14, 0x0, (int)rmesa->vb.texcoordptr);
 370    }
 371    return dfn;
 372 }
 373
 374 struct dynfn *radeon_makeX86MultiTexCoord2fARB( GLcontext *ctx,
 375                                                 int key )
 376 {
 377    struct dynfn *dfn = MALLOC_STRUCT( dynfn );
 378    radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
 379
 380    if (RADEON_DEBUG & DEBUG_CODEGEN)
 381       fprintf(stderr, "%s 0x%08x\n", __FUNCTION__, key );
 382
 383    if ((key & (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) ==
 384        (RADEON_CP_VC_FRMT_ST0|RADEON_CP_VC_FRMT_ST1)) {
 385       DFN ( _x86_MultiTexCoord2f, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
 386       FIXUP(dfn->code, 20, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]);
 387       FIXUP(dfn->code, 26, 0xdeadbeef, (int)rmesa->vb.texcoordptr[0]+4);
 388    }
 389    else {
 390       /* Note: this might get generated multiple times, even though the
 391        * actual emitted code is the same.
 392        */
 393       DFN ( _x86_MultiTexCoord2f_2, rmesa->vb.dfn_cache.MultiTexCoord2fARB );
 394       FIXUP(dfn->code, 18, 0x0, (int)rmesa->vb.texcoordptr);
 395    }
 396    return dfn;
 397 }
 398
 399
 400 void radeonInitX86Codegen( struct dfn_generators *gen )
 401 {
 402    gen->Vertex3f = radeon_makeX86Vertex3f;
 403    gen->Vertex3fv = radeon_makeX86Vertex3fv;
 404    gen->Color4ub = radeon_makeX86Color4ub; /* PKCOLOR only */
 405    gen->Color4ubv = radeon_makeX86Color4ubv; /* PKCOLOR only */
 406    gen->Normal3f = radeon_makeX86Normal3f;
 407    gen->Normal3fv = radeon_makeX86Normal3fv;
 408    gen->TexCoord2f = radeon_makeX86TexCoord2f;
 409    gen->TexCoord2fv = radeon_makeX86TexCoord2fv;
 410    gen->MultiTexCoord2fARB = radeon_makeX86MultiTexCoord2fARB;
 411    gen->MultiTexCoord2fvARB = radeon_makeX86MultiTexCoord2fvARB;
 412    gen->Color3f = radeon_makeX86Color3f;
 413    gen->Color3fv = radeon_makeX86Color3fv;
 414
 415    /* Not done:
 416     */
 417 /*     gen->Vertex2f = radeon_makeX86Vertex2f; */
 418 /*     gen->Vertex2fv = radeon_makeX86Vertex2fv; */
 419 /*     gen->Color3ub = radeon_makeX86Color3ub; */
 420 /*     gen->Color3ubv = radeon_makeX86Color3ubv; */
 421 /*     gen->Color4f = radeon_makeX86Color4f; */
 422 /*     gen->Color4fv = radeon_makeX86Color4fv; */
 423 /*     gen->TexCoord1f = radeon_makeX86TexCoord1f; */
 424 /*     gen->TexCoord1fv = radeon_makeX86TexCoord1fv; */
 425 /*     gen->MultiTexCoord1fARB = radeon_makeX86MultiTexCoord1fARB; */
 426 /*     gen->MultiTexCoord1fvARB = radeon_makeX86MultiTexCoord1fvARB; */
 427 }
 428
 429
 430 #else
 431
 432 void radeonInitX86Codegen( struct dfn_generators *gen )
 433 {
 434    (void) gen;
 435 }
 436
 437 #endif